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Lines Matching refs:opnd

52 /* Get the DWARF register number for the given OPND.  If OPND is an address,
53    the returned register is the base register.  If OPND spans multiple
57 ginsn_dw2_regnum (aarch64_opnd_info *opnd)
62   opnd_class = aarch64_get_operand_class (opnd->type);
67       dw2reg_num = opnd->reg.regno + 64;
70       dw2reg_num = opnd->reglist.first_regno + 64;
73       dw2reg_num = opnd->addr.base_regno;
79       if (aarch64_zero_register_p (opnd))
84 	dw2reg_num = opnd->reg.regno;
100 /* Generate ginsn for addsub instructions with immediate opnd.  */
109   aarch64_opnd_info *dst, *opnd;
125   opnd = &base->operands[1];
138   opnd_reg = ginsn_dw2_regnum (opnd);
153 /* Generate ginsn for addsub instructions with reg opnd.  */
295   /* Load store pair where only one of the opnd registers is a zero register
561 /* Generate ginsn for mov instructions with reg opnd.  */
599 /* Generate ginsn for mov instructions with imm opnd.  */
662   aarch64_opnd_info *opnd = NULL;
678   opnd = &base->operands[0];
685       opnd_reg = ginsn_dw2_regnum (opnd);
732   aarch64_opnd_info *opnd;
771 		  opnd = &base->operands[i];
772 		  opnd_reg = ginsn_dw2_regnum (opnd);
774 		      && aarch64_get_qualifier_esize (opnd->qualifier) >= 8)
789       opnd = &base->operands[0];
792       opnd_reg = ginsn_dw2_regnum (opnd);