Lines Matching refs:qualifier
804 to a corresponding operand qualifier. */
858 qualifier for the vector type. The operand qualifiers are regular
921 /* Return the operand qualifier associated with all uses of REG, or
963 entry on success, setting *QUALIFIER to the register qualifier.
970 aarch64_opnd_qualifier_t *qualifier)
987 *qualifier = AARCH64_OPND_QLF_S_S;
990 *qualifier = AARCH64_OPND_QLF_S_D;
1001 *qualifier = inherent_reg_qualifier (reg);
1011 on success, setting *QUALIFIER to the register qualifier. Return null
1017 aarch64_reg_parse_32_64 (char **ccp, aarch64_opnd_qualifier_t *qualifier)
1019 return aarch64_addr_reg_parse (ccp, REG_TYPE_R_ZR_SP, qualifier);
1022 /* Parse the qualifier of a vector register or vector element of type
2703 return (operand->qualifier == AARCH64_OPND_QLF_NIL
2704 || aarch64_get_qualifier_esize (operand->qualifier) == 8);
3805 aarch64_opnd_qualifier_t qualifier;
3809 reg = aarch64_reg_parse_32_64 (str, &qualifier);
3825 operand->qualifier = qualifier;
3851 aarch64_opnd_qualifier_t qualifier;
3852 const reg_entry *reg = aarch64_reg_parse_32_64 (str, &qualifier);
3863 operand->qualifier = qualifier;
4412 operand->qualifier = AARCH64_OPND_QLF_X;
4632 /* Parse STR for reg of REG_TYPE and following '.' and QUALIFIER.
4633 Function returns REG_ENTRY struct and QUALIFIER [bhsdq] or NULL
4636 REG_TYPE.QUALIFIER
4644 aarch64_opnd_qualifier_t *qualifier, unsigned int flags)
4653 *qualifier = AARCH64_OPND_QLF_NIL;
4656 *qualifier = vectype_to_qualifier (&vectype);
4657 if (*qualifier == AARCH64_OPND_QLF_NIL)
4775 qualifier and that is indexed by two values: a 32-bit register,
4780 the operand and setting QUALIFIER to the register qualifier.
4794 aarch64_opnd_qualifier_t *qualifier,
4797 const reg_entry *reg = parse_reg_with_qual (str, reg_type, qualifier, flags);
4813 aarch64_opnd_qualifier_t *qualifier)
4821 if (!parse_dual_indexed_reg (str, REG_TYPE_ZATHV, opnd, qualifier,
4848 aarch64_opnd_qualifier_t qualifier;
4856 &qualifier, ptr_flags);
4862 if (qualifier != AARCH64_OPND_QLF_NIL)
4873 if (qualifier == AARCH64_OPND_QLF_S_B)
4878 else if (qualifier == AARCH64_OPND_QLF_S_H)
4880 else if (qualifier == AARCH64_OPND_QLF_S_S)
4882 else if (qualifier == AARCH64_OPND_QLF_S_D)
4884 else if (qualifier == AARCH64_OPND_QLF_S_Q)
4890 else if (qualifier == AARCH64_OPND_QLF_NIL)
5111 info->qualifier = inherent_reg_qualifier (reg); \
5569 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
5571 Return -1 if there is no qualifier sequence; return the first match
5599 DEBUG_TRACE_IF (i == 0, "empty list of qualifier sequence");
5604 if (*qualifiers == instr->operands[j].qualifier)
5618 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
5629 instr->operands[i].qualifier = *qualifiers;
5884 2) manipulating the IR, e.g. replacing the operand qualifier;
5924 /* Find the most matched qualifier sequence. */
5948 First NIL qualifier indicates the end in the list. */
6463 is32 = inst.base.operands[0].qualifier == AARCH64_OPND_QLF_W ? 1 : 0;
6563 enum aarch64_opnd_qualifier opd0_qlf = inst.base.operands[0].qualifier;
6564 enum aarch64_opnd_qualifier opd1_qlf = inst.base.operands[1].qualifier;
6634 (_("relocation qualifier does not match instruction size"));
6728 aarch64_opnd_qualifier_t qualifier, base_qualifier, offset_qualifier;
6903 contexts. Rely on F_STRICT qualifier checking to catch
6905 info->qualifier = AARCH64_OPND_QLF_NIL;
6908 info->qualifier = vectype_to_qualifier (&vectype);
6909 if (info->qualifier == AARCH64_OPND_QLF_NIL)
6930 info->qualifier = AARCH64_OPND_QLF_S_D;
6996 info->qualifier = AARCH64_OPND_QLF_NIL;
7001 info->qualifier = vectype_to_qualifier (&vectype);
7002 if (info->qualifier == AARCH64_OPND_QLF_NIL)
7022 info->qualifier = AARCH64_OPND_QLF_NIL;
7115 info->qualifier = vectype_to_qualifier (&vectype);
7116 if (info->qualifier == AARCH64_OPND_QLF_NIL)
7148 info->qualifier = AARCH64_OPND_QLF_CR;
7692 /* Qualifier to be deduced by libopcodes. */
7798 /* Leave qualifier to be determined by libopcodes. */
7820 /* No qualifier. */
7835 &info->indexed_za, &qualifier, 0))
7837 info->qualifier = qualifier;
7962 info->qualifier = offset_qualifier;
7980 info->qualifier = base_qualifier;
8005 info->qualifier = base_qualifier;
8019 the qualifier checking routines. */
8029 info->qualifier = base_qualifier;
8238 info->qualifier = AARCH64_OPND_QLF_NIL;
8240 info->qualifier = vectype_to_qualifier (&vectype);
8261 reg = parse_reg_with_qual (&str, REG_TYPE_ZAT, &qualifier, 0);
8265 info->qualifier = qualifier;
8276 &qualifier)
8278 &info->indexed_za, &qualifier, 0))
8280 info->qualifier = qualifier;
8298 &info->indexed_za, &qualifier, 0))
8300 info->qualifier = qualifier;
8313 &info->indexed_za, &qualifier, 0))
8315 info->qualifier = qualifier;
8473 if (operands[0].qualifier == AARCH64_OPND_QLF_W)
8481 operands[0].qualifier = AARCH64_OPND_QLF_X;
8494 int size = aarch64_get_qualifier_esize (operands[0].qualifier);
8525 && operands[1].qualifier == AARCH64_OPND_QLF_W
8526 && operands[0].qualifier == AARCH64_OPND_QLF_X)
8527 operands[0].qualifier = AARCH64_OPND_QLF_W;
8541 if (operands[0].qualifier == AARCH64_OPND_QLF_X
8542 && operands[idx].qualifier == AARCH64_OPND_QLF_X
8546 operands[idx].qualifier = AARCH64_OPND_QLF_W;
9001 like ZA0H, supporting qualifier suffixes and indexing. */
9432 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
9433 qualifier matching may fail because the out-of-date qualifier will
9434 prevent the operand being updated with a new and correct qualifier. */
9438 instr->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
Indexes created Thu May 14 00:25:00 UTC 2026