Lines Matching defs:Rm
2408 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
5529 <Rm>
5530 <Rm>, <shift>
5730 <Rm>
5731 <Rm>, <shift>
5813 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5814 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5822 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5823 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
6753 Case 13: VMOV <Sd>, <Rm> */
6783 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6829 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
9260 the same instruction but with REG_PC in the Rm field. */
9347 BLX{<condition>} <Rm> ie BLX(2)
9601 unsigned Rd, Rn, Rm;
9606 Rm = inst.operands[2].reg;
9610 constraint ((Rm == REG_PC), BAD_PC);
9614 inst.instruction |= Rm << 8;
9755 strex rN, rM, foo
9758 strex rN, rM, rX
9886 as_tsktsk (_("Rd and Rm should be different in mla"));
10103 "{C|S}PSR_<field>, Rm",
10136 as_tsktsk (_("Rd and Rm should be different in mul"));
10140 UMULL RdLo, RdHi, Rm, Rs
10141 SMULL RdLo, RdHi, Rm, Rs
10142 UMLAL RdLo, RdHi, Rm, Rs
10143 SMLAL RdLo, RdHi, Rm, Rs. */
10157 /* rdhi, rdlo and rm must all be different before armv6. */
10161 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10179 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10181 Error if Rd, Rn or Rm are R15. */
10201 into pkhbt rd, rm, rn. */
10344 unsigned int Rm = (inst.operands[1].present
10349 inst.instruction |= Rm;
10350 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
10405 SMLAxy{cond} Rd,Rm,Rs,Rn
10406 SMLAWy{cond} Rd,Rm,Rs,Rn
10419 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10436 SMULxy{cond} Rd,Rm,Rs
10555 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10570 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
11066 MIAcc acc0,Rm,Rs
11067 MIAPHcc acc0,Rm,Rs
11068 MIAxycc acc0,Rm,Rs. */
11854 the same instruction but with REG_PC in the Rm field. */
11896 BLX <Rm> which is BLX(2)
12056 int Rm;
12059 Rm = inst.operands[0].reg;
12060 reject_bad_reg (Rm);
12061 inst.instruction |= Rm << 16;
12068 unsigned Rm;
12071 Rm = inst.operands[1].reg;
12074 reject_bad_reg (Rm);
12077 inst.instruction |= Rm << 16;
12078 inst.instruction |= Rm;
12085 unsigned Rd, Rn, Rm;
12098 Rm = inst.operands[2].reg;
12101 constraint (Rm == REG_SP, BAD_SP);
12112 Rm = Rn;
12121 Rm = REG_PC;
12131 inst.instruction |= Rm;
12214 unsigned Rd, Rn, Rm;
12219 Rm = inst.operands[2].reg;
12223 reject_bad_reg (Rm);
12227 inst.instruction |= Rm;
12637 /* Only [Rn,Rm] is acceptable. */
12745 unsigned Rd, Rn, Rm, Ra;
12749 Rm = inst.operands[2].reg;
12754 reject_bad_reg (Rm);
12759 inst.instruction |= Rm;
12766 unsigned RdLo, RdHi, Rn, Rm;
12771 Rm = inst.operands[3].reg;
12776 reject_bad_reg (Rm);
12781 inst.instruction |= Rm;
12787 unsigned Rn, Rm;
12790 Rm = inst.operands[1].reg;
12803 low_regs = (Rn <= 7 && Rm <= 7);
12817 && Rm == REG_LR)
12828 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12830 warn_deprecated_sp (Rm);
12831 /* R15 was documented as a valid choice for Rm in ARMv6,
12834 constraint (Rm == REG_PC, BAD_PC);
12837 reject_bad_reg (Rm);
12847 reject_bad_reg (Rm);
12853 && (Rm == REG_SP || Rm == REG_PC))
12857 "register."), Rm, Rn);
12864 constraint (Rm == REG_PC, BAD_PC);
12866 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
12923 if (Rn != Rm)
12956 inst.instruction |= Rm << 16;
12988 inst.instruction |= Rm << 3;
13016 inst.instruction |= Rm << 3;
13024 inst.instruction |= Rm << 3;
13032 inst.instruction |= Rm << 3;
13039 inst.instruction |= Rm << 3;
13054 if (Rn < 8 && Rm < 8)
13064 inst.instruction |= Rm << 3;
13120 unsigned Rn, Rm;
13123 Rm = inst.operands[1].reg;
13130 reject_bad_reg (Rm);
13141 || Rn > 7 || Rm > 7)
13168 inst.instruction |= Rm << 3;
13188 constraint (Rn > 7 || Rm > 7,
13193 inst.instruction |= Rm << 3;
13296 unsigned Rd, Rn, Rm;
13303 Rm = inst.operands[2].reg;
13309 && Rd != Rm)
13311 || Rm > 7)
13321 constraint (Rn > 7 || Rm > 7,
13333 inst.instruction |= Rm << 3;
13334 else if (Rd == Rm)
13347 inst.instruction |= Rm << 0;
13351 reject_bad_reg (Rm);
13358 unsigned RdLo, RdHi, Rn, Rm;
13363 Rm = inst.operands[3].reg;
13368 reject_bad_reg (Rm);
13373 inst.instruction |= Rm;
13475 unsigned Rm;
13477 Rm = inst.operands[2].reg;
13478 reject_bad_reg (Rm);
13490 unsigned Rd, Rn, Rm;
13494 Rm = inst.operands[2].reg;
13498 reject_bad_reg (Rm);
13502 inst.instruction |= Rm;
13522 /* PR 10168. Swap the Rm and Rn registers. */
13605 unsigned Rd, Rm;
13608 Rm = inst.operands[1].reg;
13611 reject_bad_reg (Rm);
13614 inst.instruction |= Rm << 16;
13615 inst.instruction |= Rm;
13621 unsigned Rd, Rm;
13624 Rm = inst.operands[1].reg;
13627 reject_bad_reg (Rm);
13629 if (Rd <= 7 && Rm <= 7
13634 inst.instruction |= Rm << 3;
13640 inst.instruction |= Rm << 16;
13641 inst.instruction |= Rm;
13650 unsigned Rd, Rm;
13653 Rm = inst.operands[1].reg;
13656 reject_bad_reg (Rm);
13659 inst.instruction |= Rm;
13880 unsigned Rd, Rn, Rm;
13884 Rm = inst.operands[2].reg;
13888 reject_bad_reg (Rm);
13892 inst.instruction |= Rm;
13898 unsigned Rd, Rn, Rm;
13901 Rm = inst.operands[1].reg;
13906 reject_bad_reg (Rm);
13910 inst.instruction |= Rm;
14037 unsigned Rd, Rn, Rm;
14041 Rm = inst.operands[2].reg;
14045 reject_bad_reg (Rm);
14049 inst.instruction |= Rm;
14056 unsigned Rd, Rm;
14059 Rm = inst.operands[1].reg;
14062 reject_bad_reg (Rm);
14066 && Rd <= 7 && Rm <= 7
14071 inst.instruction |= Rm << 3;
14078 inst.instruction |= Rm;
14098 unsigned Rn, Rm;
14107 Rm = inst.operands[0].imm;
14111 reject_bad_reg (Rm);
14115 inst.instruction |= (Rn << 16) | Rm;
14331 /* Assuming Rm is already checked not to be 11x1. */
14352 /* Assuming Rm is already checked not to be 11x1. */
16009 unsigned Rm;
16014 Rm = 7;
16026 Rm = inst.operands[2].reg >> 1;
16033 inst.instruction |= Rm << 1;
16586 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16605 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
17637 scalars, which are encoded in 5 bits, M : Rm.
17638 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17639 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
18802 int rm;
18851 case neon_cvt_mode_a: rm = 0; break;
18852 case neon_cvt_mode_n: rm = 1; break;
18853 case neon_cvt_mode_p: rm = 2; break;
18854 case neon_cvt_mode_m: rm = 3; break;
18868 inst.instruction |= rm << 16;
19409 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19507 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19595 unsigned rm
19598 inst.instruction |= rm;
19610 /* Redo Rn and Rm. */
19876 (Register operations, which are VORR with Rm = Rn.)
19896 13. VMOV <Sd>, <Rm>
19900 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
21597 unsigned imm, Rd, Rn, Rm;
21607 Rm = inst.operands[4].reg;
21613 Rm = inst.operands[3].reg;
21624 inst.instruction |= Rm << 12;
22042 unsigned int Rm = inst.operands[2].reg;
22047 inst.instruction |= LOW4 (Rm);
22051 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
Indexes created Sun Mar 01 05:31:48 UTC 2026