Lines Matching defs:Rn
2408 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
5812 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5813 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5814 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5821 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5822 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5823 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5828 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5832 [Rn]{!} shorthand for [Rn,#0]{!}
6054 /* [Rn], {expr} - unindexed, with option */
6137 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6752 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6783 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6871 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
9121 unsigned Rn = inst.operands[2].reg;
9125 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
9126 _("Rn must not overlap other operands"));
9139 inst.instruction |= Rn << 16;
9535 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9545 Result unpredictable if Rd or Rn is R15. */
9550 unsigned Rd, Rn;
9553 Rn = inst.operands[3].reg;
9558 reject_bad_reg (Rn);
9563 constraint (Rn == REG_PC, BAD_PC);
9569 /* If Rd == Rn, error that the operation is
9571 constraint (Rd == Rn, BAD_OVERLAP);
9577 inst.instruction |= Rn << 16;
9601 unsigned Rd, Rn, Rm;
9604 Rn = (inst.operands[1].present
9609 constraint ((Rn == REG_PC), BAD_PC);
9613 inst.instruction |= Rn << 0;
9755 strex rN, rM, foo
9758 strex rN, rM, rX
9821 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9822 reject [Rn,...]. */
9853 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9854 reject [Rn,...]. */
10179 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10181 Error if Rd, Rn or Rm are R15. */
10201 into pkhbt rd, rm, rn. */
10270 Error if Rn is R15. */
10405 SMLAxy{cond} Rd,Rm,Rs,Rn
10406 SMLAWy{cond} Rd,Rm,Rs,Rn
10555 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10937 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
11144 reject PC in Rn. */
11358 int Rd, Rn;
11361 Rn = inst.operands[1].reg;
11363 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11365 if (Rn == REG_SP)
11370 inst.instruction |= (Rn << 16) | (Rd << 8);
11380 int Rd, Rs, Rn;
11494 Rn = inst.operands[2].reg;
11498 if (Rd > 7 || Rs > 7 || Rn > 7)
11507 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
11511 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
11515 if (Rd > 7 || Rn > 7
11519 if (Rd == Rn)
11521 Rn = Rs;
11527 inst.instruction |= Rn << 3;
11537 reject_bad_reg (Rn);
11571 Rn = inst.operands[2].reg;
11574 /* We now have Rd, Rs, and Rn set to registers. */
11575 if (Rd > 7 || Rs > 7 || Rn > 7)
11583 inst.instruction |= Rn << 3;
11584 else if (Rn == Rd)
11593 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
11647 int Rd, Rs, Rn;
11653 Rn = inst.operands[2].reg;
11658 reject_bad_reg (Rn);
11682 if (Rd > 7 || Rn > 7 || Rs > 7)
11694 inst.instruction |= Rn << 3;
11717 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
11723 inst.instruction |= Rn << 3;
11735 int Rd, Rs, Rn;
11741 Rn = inst.operands[2].reg;
11746 reject_bad_reg (Rn);
11770 if (Rd > 7 || Rn > 7 || Rs > 7)
11783 inst.instruction |= Rn << 3;
11786 if (Rd == Rn)
11814 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
11820 inst.instruction |= Rn << 3;
11821 else if (Rd == Rn)
11847 int Rd, Rn;
11856 Rn = REG_PC;
11859 Rn = inst.operands[1].reg;
11860 reject_bad_reg (Rn);
11868 inst.instruction |= Rn << 16;
11877 unsigned Rd, Rn;
11880 Rn = inst.operands[1].reg;
11883 reject_bad_reg (Rn);
11888 inst.instruction |= Rn << 16;
12085 unsigned Rd, Rn, Rm;
12097 Rn = inst.operands[1].reg;
12100 constraint (Rn == REG_SP, BAD_SP);
12107 Rn = inst.operands[1].reg;
12111 constraint (Rn == REG_SP, BAD_SP);
12112 Rm = Rn;
12120 Rn = REG_PC;
12130 inst.instruction |= Rn << 16;
12214 unsigned Rd, Rn, Rm;
12217 Rn = (inst.operands[1].present
12222 reject_bad_reg (Rn);
12226 inst.instruction |= Rn << 16;
12529 int Rn;
12554 Rn = inst.operands[1].reg;
12558 /* [Rn, Rik] */
12559 if (Rn <= 7 && inst.operands[1].imm <= 7)
12564 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
12566 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
12567 || (Rn == REG_SP && opcode == T_MNEM_str))
12569 /* [Rn, #const] */
12570 if (Rn > 7)
12572 if (Rn == REG_PC)
12637 /* Only [Rn,Rm] is acceptable. */
12745 unsigned Rd, Rn, Rm, Ra;
12748 Rn = inst.operands[1].reg;
12753 reject_bad_reg (Rn);
12758 inst.instruction |= Rn << 16;
12766 unsigned RdLo, RdHi, Rn, Rm;
12770 Rn = inst.operands[2].reg;
12775 reject_bad_reg (Rn);
12780 inst.instruction |= Rn << 16;
12787 unsigned Rn, Rm;
12789 Rn = inst.operands[0].reg;
12792 if (Rn == REG_PC)
12803 low_regs = (Rn <= 7 && Rm <= 7);
12816 && Rn == REG_PC
12825 constraint (Rn == REG_PC, BAD_PC);
12846 reject_bad_reg (Rn);
12852 if ((Rn == REG_SP || Rn == REG_PC)
12857 "register."), Rm, Rn);
12863 constraint (Rn == REG_PC, BAD_PC);
12866 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
12870 reject_bad_reg (Rn);
12881 inst.instruction |= Rn << 8;
12901 inst.instruction |= Rn << r0off;
12923 if (Rn != Rm)
12947 inst.instruction |= Rn;
12955 inst.instruction |= Rn << 8;
12987 inst.instruction |= Rn;
12994 inst.instruction |= Rn << r0off;
13014 inst.instruction |= (Rn & 0x8) << 4;
13015 inst.instruction |= (Rn & 0x7);
13023 inst.instruction |= Rn;
13031 inst.instruction |= Rn;
13037 inst.instruction |= (Rn & 0x8) << 4;
13038 inst.instruction |= (Rn & 0x7);
13054 if (Rn < 8 && Rm < 8)
13063 inst.instruction |= Rn;
13077 constraint (Rn > 7,
13079 inst.instruction |= Rn << 8;
13120 unsigned Rn, Rm;
13122 Rn = inst.operands[0].reg;
13127 constraint (Rn == REG_PC, BAD_PC);
13129 reject_bad_reg (Rn);
13141 || Rn > 7 || Rm > 7)
13158 inst.instruction |= Rn << r0off;
13167 inst.instruction |= Rn;
13177 inst.instruction |= Rn << r0off;
13188 constraint (Rn > 7 || Rm > 7,
13192 inst.instruction |= Rn;
13249 unsigned Rn;
13282 Rn = inst.operands[1].reg;
13283 reject_bad_reg (Rn);
13289 inst.instruction |= Rn << 16;
13296 unsigned Rd, Rn, Rm;
13302 Rn = inst.operands[1].reg;
13308 || (Rd != Rn
13310 || Rn > 7
13321 constraint (Rn > 7 || Rm > 7,
13332 if (Rd == Rn)
13335 inst.instruction |= Rn << 3;
13346 inst.instruction |= Rn << 16;
13350 reject_bad_reg (Rn);
13358 unsigned RdLo, RdHi, Rn, Rm;
13362 Rn = inst.operands[2].reg;
13367 reject_bad_reg (Rn);
13372 inst.instruction |= Rn << 16;
13456 unsigned Rd, Rn;
13459 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
13462 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13463 reject_bad_reg (Rn);
13466 inst.instruction |= Rn << 16;
13490 unsigned Rd, Rn, Rm;
13493 Rn = inst.operands[1].reg;
13497 reject_bad_reg (Rn);
13501 inst.instruction |= Rn << 16;
13522 /* PR 10168. Swap the Rm and Rn registers. */
13838 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
13880 unsigned Rd, Rn, Rm;
13883 Rn = inst.operands[1].reg;
13887 reject_bad_reg (Rn);
13891 inst.instruction |= Rn << 16;
13898 unsigned Rd, Rn, Rm;
13902 Rn = inst.operands[2].reg;
13905 reject_bad_reg (Rn);
13909 inst.instruction |= Rn << 16;
13943 unsigned Rd, Rn;
13946 Rn = inst.operands[2].reg;
13949 reject_bad_reg (Rn);
13953 inst.instruction |= Rn << 16;
13987 unsigned Rd, Rn;
13990 Rn = inst.operands[2].reg;
13993 reject_bad_reg (Rn);
13997 inst.instruction |= Rn << 16;
14037 unsigned Rd, Rn, Rm;
14040 Rn = inst.operands[1].reg;
14044 reject_bad_reg (Rn);
14048 inst.instruction |= Rn << 16;
14098 unsigned Rn, Rm;
14106 Rn = inst.operands[0].reg;
14110 constraint (Rn == REG_SP, BAD_SP);
14115 inst.instruction |= (Rn << 16) | Rm;
14151 unsigned Rd, Rn;
14154 Rn = inst.operands[2].reg;
14157 reject_bad_reg (Rn);
14161 inst.instruction |= Rn << 16;
16586 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
19409 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19602 /* Redo Rn as well. */
19610 /* Redo Rn and Rm. */
19876 (Register operations, which are VORR with Rm = Rn.)
19882 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
19886 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
19900 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
21558 unsigned imm, Rd, Rn;
21567 Rn = inst.operands[3].reg;
21572 Rn = inst.operands[2].reg;
21581 inst.instruction |= Rn << 16;
21597 unsigned imm, Rd, Rn, Rm;
21606 Rn = inst.operands[3].reg;
21612 Rn = inst.operands[2].reg;
21623 inst.instruction |= Rn << 16;
22041 unsigned int Rn = inst.operands[1].reg;
22046 inst.instruction |= LOW4 (Rn) << 16;
22051 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
23658 REGSET(r, RN), REGSET(R, RN),
23661 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
23662 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
23663 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
23665 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
23666 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
23667 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
23670 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
23671 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
23673 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
23674 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
25636 ToC("vlldm", ec300a00, 1, (RRnpc), rn),
25637 ToC("vlstm", ec200a00, 1, (RRnpc), rn),
28092 but with the Rn field [19:16] set to 1111. */
Indexes created Mon May 04 00:23:20 UTC 2026