Lines Matching refs:inst
568 static struct arm_it inst;
1009 return inst.cond != COND_ALWAYS;
1023 inst.pred_insn_type = type; \
1032 inst.pred_insn_type = type; \
1041 if (inst.cond == COND_ALWAYS) \
1159 inst.error = _("immediate expression requires a # prefix");
1186 if (inst.error == NULL)
1187 inst.error = (ep->X_op == O_absent
1202 inst.error = _("invalid constant");
1564 if (!inst.error)
1565 inst.error = err;
2014 inst.error = _("invalid register mask");
2033 if (inst.relocs[0].type != 0)
2035 inst.error = _("expression too complex");
2039 memcpy (&inst.relocs[0].exp, &exp, sizeof (expressionS));
2040 inst.relocs[0].type = BFD_RELOC_ARM_MULTI;
2041 inst.relocs[0].pc_rel = 0;
2091 inst.error = _("expecting {");
2222 inst.error = gettext (reg_expected_msgs[regtype]);
2237 inst.error = _("register range not in ascending order");
2245 inst.error = _("invalid register list");
2276 inst.error = _("non-contiguous register range");
3498 /* Add the literal in the global 'inst'
3514 imm1 = inst.operands[1].imm;
3515 imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg
3516 : inst.relocs[0].exp.X_unsigned ? 0
3517 : (int64_t) inst.operands[1].imm >> 32);
3521 imm2 = inst.operands[1].imm;
3532 if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
3533 && (inst.relocs[0].exp.X_op == O_constant)
3535 == inst.relocs[0].exp.X_add_number)
3538 == inst.relocs[0].exp.X_unsigned))
3541 if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
3542 && (inst.relocs[0].exp.X_op == O_symbol)
3544 == inst.relocs[0].exp.X_add_number)
3546 == inst.relocs[0].exp.X_add_symbol)
3548 == inst.relocs[0].exp.X_op_symbol)
3558 == inst.relocs[0].exp.X_unsigned)
3562 == inst.relocs[0].exp.X_unsigned))
3577 inst.error = _("literal pool overflow");
3594 if (!(inst.relocs[0].exp.X_op == O_constant
3595 || inst.relocs[0].exp.X_op == O_big))
3597 inst.error = _("invalid type for literal pool");
3604 inst.error = _("literal pool overflow");
3608 pool->literals[entry] = inst.relocs[0].exp;
3617 inst.error = _("literal pool overflow");
3621 pool->literals[entry] = inst.relocs[0].exp;
3624 pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
3626 pool->literals[entry] = inst.relocs[0].exp;
3629 pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
3636 pool->literals[entry] = inst.relocs[0].exp;
3652 pool->literals[entry] = inst.relocs[0].exp;
3656 inst.relocs[0].exp.X_op = O_symbol;
3657 inst.relocs[0].exp.X_add_number = pool_size;
3658 inst.relocs[0].exp.X_add_symbol = pool->symbol;
3941 as_bad (_(".inst.n operand too big. "\
3942 "Use .inst.w instead"));
3962 "Use .inst.n/.inst.w instead"));
5124 { "inst.n", s_arm_elf_inst, 2 },
5125 { "inst.w", s_arm_elf_inst, 4 },
5126 { "inst", s_arm_elf_inst, 0 },
5199 inst.error = _("constant expression required");
5205 inst.error = _("immediate value out of range");
5215 instructions. Puts the result directly in inst.operands[i]. */
5229 inst.operands[i].imm = exp_p->X_add_number & 0xffffffff;
5236 inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16)
5238 inst.operands[i].regisimm = 1;
5268 inst.operands[i].imm = 0;
5270 inst.operands[i].imm |= ((unsigned) generic_bignum[idx]
5272 inst.operands[i].reg = 0;
5274 inst.operands[i].reg |= ((unsigned) generic_bignum[idx]
5276 inst.operands[i].regisimm = 1;
5446 inst.error = _("shift expression expected");
5454 inst.error = _("shift expression expected");
5466 inst.error = _("'UXTW' not allowed here");
5474 inst.error = _("'LSL' or 'ASR' required");
5482 inst.error = _("'LSL' required");
5490 inst.error = _("'ASR' required");
5497 inst.error = _("'UXTW' required");
5513 inst.operands[i].imm = reg;
5514 inst.operands[i].immisreg = 1;
5516 else if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
5519 inst.operands[i].shift_kind = shift;
5520 inst.operands[i].shifted = 1;
5544 inst.operands[i].reg = value;
5545 inst.operands[i].isreg = 1;
5548 inst.relocs[0].exp.X_op = O_constant;
5549 inst.relocs[0].exp.X_add_number = 0;
5558 if (my_get_expression (&inst.relocs[0].exp, str, GE_IMM_PREFIX))
5567 if (exp.X_op != O_constant || inst.relocs[0].exp.X_op != O_constant)
5569 inst.error = _("constant expression expected");
5576 inst.error = _("invalid rotation");
5579 if (inst.relocs[0].exp.X_add_number < 0
5580 || inst.relocs[0].exp.X_add_number > 255)
5582 inst.error = _("invalid constant");
5587 inst.operands[i].imm = inst.relocs[0].exp.X_add_number | value << 7;
5591 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
5592 inst.relocs[0].pc_rel = 0;
5758 inst.error = _("unknown group relocation");
5764 if (my_get_expression (&inst.relocs[0].exp, str, GE_NO_PREFIX))
5768 inst.relocs[0].type = (bfd_reloc_code_real_type) entry->alu_code;
5769 gas_assert (inst.relocs[0].type != 0);
5781 inst.operands[i]. We assume the initial ':' has been skipped.
5794 inst.error = _("alignment must be constant");
5798 inst.operands[i].imm = exp.X_add_number << 8;
5799 inst.operands[i].immisalign = 1;
5801 inst.operands[i].preind = 0;
5808 to inst.operands[i] and/or inst.relocs[0].
5837 supported by the instruction, and to set inst.relocs[0].type. */
5853 inst.error = BAD_SYNTAX;
5859 inst.relocs[0].pc_rel = 1;
5860 inst.operands[i].reg = REG_PC;
5861 inst.operands[i].isreg = 1;
5862 inst.operands[i].preind = 1;
5864 if (my_get_expression (&inst.relocs[0].exp, &p, GE_OPT_PREFIX_BIG))
5867 else if (parse_big_immediate (&p, i, &inst.relocs[0].exp,
5884 inst.operands[i].isquad = 1;
5888 inst.error = BAD_ADDR_MODE;
5895 inst.error = BAD_ADDR_MODE;
5897 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5900 inst.operands[i].reg = reg;
5901 inst.operands[i].isreg = 1;
5905 inst.operands[i].preind = 1;
5908 else if (*p == '-') p++, inst.operands[i].negative = 1;
5915 inst.operands[i].immisreg = 2;
5916 inst.operands[i].imm = reg;
5922 inst.operands[i].imm |= inst.relocs[0].exp.X_add_number << 5;
5923 inst.relocs[0].exp.X_add_number = 0;
5931 inst.operands[i].imm = reg;
5932 inst.operands[i].immisreg = 1;
5950 if (inst.operands[i].negative)
5952 inst.operands[i].negative = 0;
5971 inst.error = _("unknown group relocation");
5978 if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
5985 inst.relocs[0].type
5990 inst.relocs[0].type
5995 inst.relocs[0].type
6003 if (inst.relocs[0].type == 0)
6005 inst.error = _("this group relocation is not allowed on this instruction");
6013 if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
6016 if (inst.relocs[0].exp.X_op == O_constant
6017 && inst.relocs[0].exp.X_add_number == 0)
6026 inst.operands[i].negative = 1;
6043 inst.error = _("']' expected");
6048 inst.operands[i].writeback = 1;
6055 if (parse_immediate (&p, &inst.operands[i].imm,
6061 inst.error = _("'}' expected at end of 'option' field");
6064 if (inst.operands[i].preind)
6066 inst.error = _("cannot combine index with option");
6074 inst.operands[i].postind = 1;
6075 inst.operands[i].writeback = 1;
6077 if (inst.operands[i].preind)
6079 inst.error = _("cannot combine pre- and post-indexing");
6084 else if (*p == '-') p++, inst.operands[i].negative = 1;
6091 inst.operands[i].immisreg = 2;
6092 inst.operands[i].imm = reg;
6098 if (inst.operands[i].immisalign)
6099 inst.operands[i].imm |= reg;
6101 inst.operands[i].imm = reg;
6102 inst.operands[i].immisreg = 1;
6112 if (inst.operands[i].negative)
6114 inst.operands[i].negative = 0;
6117 if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
6120 if (inst.relocs[0].exp.X_op == O_constant
6121 && inst.relocs[0].exp.X_add_number == 0)
6130 inst.operands[i].negative = 1;
6138 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
6140 inst.operands[i].preind = 1;
6141 inst.relocs[0].exp.X_op = O_constant;
6142 inst.relocs[0].exp.X_add_number = 0;
6170 inst.relocs[0].type = BFD_RELOC_ARM_MOVW;
6172 inst.relocs[0].type = BFD_RELOC_ARM_MOVT;
6174 if (inst.relocs[0].type != BFD_RELOC_UNUSED)
6180 if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
6183 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
6185 if (inst.relocs[0].exp.X_op != O_constant)
6187 inst.error = _("constant expression expected");
6190 if (inst.relocs[0].exp.X_add_number < 0
6191 || inst.relocs[0].exp.X_add_number > 0xffff)
6193 inst.error = _("immediate value out of range");
6330 inst.error = _("unexpected bit specified after APSR");
6342 inst.error = _("selected processor does not "
6354 inst.error = _("bad bitmask specified after APSR");
6389 inst.error = _("selected processor does not support requested special "
6394 inst.error = _("flag for {c}psr instruction expected");
6458 inst.error = _("unrecognized CPS flag");
6465 inst.error = _("missing CPS flags");
6488 inst.error = _("valid endian specifiers are be or le");
6494 inst.error = _("valid endian specifiers are be or le");
6516 inst.error = _("missing rotation field after comma");
6531 inst.error = _("rotation can only be 0, 8, 16, or 24");
6560 inst.error = _("condition required");
6601 inst.error = _("'[' expected");
6607 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6610 inst.operands[0].reg = reg;
6614 inst.error = _("',' expected");
6620 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6623 inst.operands[0].imm = reg;
6629 if (inst.relocs[0].exp.X_add_number != 1)
6631 inst.error = _("invalid shift");
6634 inst.operands[0].shifted = 1;
6639 inst.error = _("']' expected");
6664 inst.operands[i].reg = val;
6665 inst.operands[i].isvec = 1;
6666 inst.operands[i].isscalar = 2;
6667 inst.operands[i].vectype = optype;
6668 inst.operands[i++].present = 1;
6676 inst.operands[i].reg = val;
6677 inst.operands[i].isreg = 1;
6678 inst.operands[i].present = 1;
6683 inst.operands[i].reg = val;
6684 inst.operands[i].isvec = 1;
6685 inst.operands[i].isscalar = 2;
6686 inst.operands[i].vectype = optype;
6687 inst.operands[i++].present = 1;
6695 inst.operands[i].reg = val;
6696 inst.operands[i].isreg = 1;
6697 inst.operands[i++].present = 1;
6705 inst.operands[i].reg = val;
6706 inst.operands[i].isreg = 1;
6707 inst.operands[i].present = 1;
6718 inst.operands[i].reg = val;
6719 inst.operands[i].isscalar = 1;
6720 inst.operands[i].vectype = optype;
6721 inst.operands[i++].present = 1;
6729 inst.operands[i].reg = val;
6730 inst.operands[i].isreg = 1;
6731 inst.operands[i].present = 1;
6742 inst.operands[i].reg = val;
6743 inst.operands[i].isreg = 1;
6744 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6745 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6746 inst.operands[i].isvec = 1;
6747 inst.operands[i].vectype = optype;
6748 inst.operands[i++].present = 1;
6754 inst.operands[i].reg = val;
6755 inst.operands[i].isreg = 1;
6756 inst.operands[i].present = 1;
6770 inst.operands[i].reg = val;
6771 inst.operands[i].isreg = 1;
6772 inst.operands[i].present = 1;
6785 inst.operands[i].reg = val;
6786 inst.operands[i].isreg = 1;
6787 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6788 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6789 inst.operands[i].isvec = 1;
6790 inst.operands[i].vectype = optype;
6791 inst.operands[i].present = 1;
6801 inst.operands[i].reg = val;
6802 inst.operands[i].isreg = 1;
6803 inst.operands[i++].present = 1;
6811 inst.operands[i].reg = val;
6812 inst.operands[i].isreg = 1;
6813 inst.operands[i].present = 1;
6816 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
6821 inst.operands[i].immisfloat = 1;
6836 inst.operands[i].reg = val;
6837 inst.operands[i].isreg = 1;
6838 inst.operands[i++].present = 1;
6846 inst.operands[i].reg = val;
6847 inst.operands[i].isscalar = 2;
6848 inst.operands[i].present = 1;
6849 inst.operands[i].vectype = optype;
6854 inst.operands[i].reg = val;
6855 inst.operands[i].isscalar = 1;
6856 inst.operands[i].present = 1;
6857 inst.operands[i].vectype = optype;
6861 inst.operands[i].reg = val;
6862 inst.operands[i].isreg = 1;
6863 inst.operands[i++].present = 1;
6873 inst.operands[i].reg = val;
6874 inst.operands[i].isreg = 1;
6875 inst.operands[i].isvec = 1;
6876 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6877 inst.operands[i].vectype = optype;
6878 inst.operands[i].present = 1;
6892 inst.operands[i].reg = val;
6893 inst.operands[i].isreg = 1;
6894 inst.operands[i].isvec = 1;
6895 inst.operands[i].issingle = 1;
6896 inst.operands[i].vectype = optype;
6897 inst.operands[i].present = 1;
6906 inst.operands[i].reg = val;
6907 inst.operands[i].isvec = 1;
6908 inst.operands[i].isscalar = 2;
6909 inst.operands[i].vectype = optype;
6910 inst.operands[i++].present = 1;
6921 inst.operands[i].reg = val;
6922 inst.operands[i].isvec = 1;
6923 inst.operands[i].isscalar = 2;
6924 inst.operands[i].vectype = optype;
6925 inst.operands[i].present = 1;
6939 inst.operands[i].reg = val;
6940 inst.operands[i].isreg = 1;
6941 inst.operands[i].isvec = 1;
6942 inst.operands[i].issingle = 1;
6943 inst.operands[i].vectype = optype;
6944 inst.operands[i].present = 1;
7161 semantic validation; it merely squirrels values away in the inst
7188 & inst.operands[i].vectype); \
7194 inst.operands[i].reg = val; \
7195 inst.operands[i].isreg = 1; \
7196 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7197 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7198 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7201 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7209 & inst.operands[i].vectype); \
7213 inst.operands[i].reg = val; \
7214 inst.operands[i].isreg = 1; \
7215 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7216 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7217 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7220 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7229 inst.operands[i].imm = val; \
7240 inst.error = _("constant expression required"); \
7245 inst.error = _("immediate value 48 or 64 expected"); \
7248 inst.operands[i].imm = exp.X_add_number; \
7255 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7259 inst.operands[i].reg = val; \
7260 inst.operands[i].isscalar = 1; \
7291 || ((inst.instruction & 0xf0) == 0x60 \
7294 inst.error = _("invalid barrier type"); \
7314 backtrack_error = inst.error;
7318 if (i > 0 && (i > 1 || inst.operands[0].present))
7368 inst.operands[i].isreg = 1;
7369 inst.operands[i].reg = 13;
7423 inst.error = 0;
7459 inst.operands[i].imm = 0;
7462 inst.error
7489 inst.error = 0;
7493 inst.error = 0;
7558 inst.error = _("immediate value is out of range");
7591 inst.operands[i].writeback = 1;
7639 inst.operands[i].writeback = 1;
7649 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
7654 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
7659 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
7661 if (inst.relocs[0].exp.X_op == O_symbol)
7666 inst.error = _("unrecognized relocation suffix");
7671 inst.operands[i].imm = val;
7672 inst.operands[i].hasreloc = 1;
7678 po_misc_or_fail (my_get_expression (&inst.relocs[i].exp, &str,
7680 if (inst.relocs[i].exp.X_op == O_symbol)
7682 inst.operands[i].hasreloc = 1;
7684 else if (inst.relocs[i].exp.X_op == O_constant)
7686 inst.operands[i].imm = inst.relocs[i].exp.X_add_number;
7687 inst.operands[i].hasreloc = 0;
7719 inst.error = _("iWMMXt data or control register expected");
7722 inst.operands[i].reg = rege->number;
7723 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
7734 inst.error = _("iWMMXt control register expected");
7737 inst.operands[i].reg = rege->number;
7738 inst.operands[i].isreg = 1;
7760 inst.error = _("Banked registers are not available with this "
7797 inst.operands[i].isvec = 1;
7799 inst.operands[i].reg = REG_PC;
7814 inst.operands[i].writeback = 1;
7824 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S,
7829 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D,
7835 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7839 inst.error = NULL;
7840 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7842 inst.operands[i].issingle = 1;
7847 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7851 inst.error = NULL;
7852 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7854 inst.operands[i].issingle = 1;
7859 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7865 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
7866 1, &inst.operands[i].vectype);
7871 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
7872 0, &inst.operands[i].vectype);
7948 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
7949 inst.error = BAD_PC;
7955 if (inst.operands[i].isreg)
7957 if (inst.operands[i].reg == REG_PC)
7958 inst.error = BAD_PC;
7959 else if (inst.operands[i].reg == REG_SP
7965 inst.error = BAD_SP;
7971 if (inst.operands[i].isreg
7972 && inst.operands[i].reg == REG_PC
7973 && (inst.operands[i].writeback || thumb))
7974 inst.error = BAD_PC;
7979 if (inst.operands[i].isreg)
8002 inst.operands[i].imm = val;
8007 if (inst.operands[i].reg != REG_LR)
8008 inst.error = _("operand must be LR register");
8012 if (inst.operands[i].reg != REG_SP)
8013 inst.error = _("operand must be SP register");
8017 if (inst.operands[i].reg != REG_R12)
8018 inst.error = _("operand must be r12");
8024 if (!inst.operands[i].iszr && inst.operands[i].reg == REG_PC)
8025 inst.error = BAD_PC;
8029 if (inst.operands[i].isreg
8030 && (inst.operands[i].reg & 0x00000001) != 0)
8031 inst.error = BAD_ODD;
8035 if (inst.operands[i].isreg)
8037 if ((inst.operands[i].reg & 0x00000001) != 1)
8038 inst.error = BAD_EVEN;
8039 else if (inst.operands[i].reg == REG_SP)
8041 else if (inst.operands[i].reg == REG_PC)
8042 inst.error = BAD_PC;
8051 inst.operands[i].present = 1;
8055 inst.error = BAD_ARGS;
8060 /* The parse routine should already have set inst
8062 if (!inst.error)
8063 inst.error = BAD_SYNTAX;
8074 if (!inst.error)
8075 inst.error = BAD_SYNTAX;
8081 inst.error = backtrack_error;
8082 inst.operands[backtrack_index].present = 0;
8088 if (*str != '\0' && !inst.error)
8089 inst.error = _("garbage following instruction");
8091 return inst.error ? FAIL : SUCCESS;
8107 inst.error = err; \
8123 inst.error = BAD_PC; \
8129 inst.error = BAD_SP; \
8146 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8156 if (inst.cond < COND_ALWAYS)
8162 inst.instruction = (inst.instruction & 0xfffff0ff) | 0x900;
8213 /* Encode a VFP SP or DP register number into inst.instruction. */
8240 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
8244 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
8248 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
8252 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
8256 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
8260 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
8274 if (inst.operands[i].immisreg)
8282 if (inst.operands[op_index].present && inst.operands[op_index].isreg
8283 && inst.operands[op_index].reg == REG_PC)
8287 if (inst.operands[i].imm == REG_PC)
8291 if (inst.operands[i].shift_kind == SHIFT_RRX)
8292 inst.instruction |= SHIFT_ROR << 5;
8295 inst.instruction |= inst.operands[i].shift_kind << 5;
8296 if (inst.operands[i].immisreg)
8298 inst.instruction |= SHIFT_BY_REG;
8299 inst.instruction |= inst.operands[i].imm << 8;
8302 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
8309 if (inst.operands[i].isreg)
8311 inst.instruction |= inst.operands[i].reg;
8316 inst.instruction |= INST_IMMEDIATE;
8317 if (inst.relocs[0].type != BFD_RELOC_ARM_IMMEDIATE)
8318 inst.instruction |= inst.operands[i].imm;
8328 constraint (!inst.operands[i].isreg,
8331 inst.instruction |= inst.operands[i].reg << 16;
8333 if (inst.operands[i].preind)
8337 inst.error = _("instruction does not accept preindexed addressing");
8340 inst.instruction |= PRE_INDEX;
8341 if (inst.operands[i].writeback)
8342 inst.instruction |= WRITE_BACK;
8345 else if (inst.operands[i].postind)
8347 gas_assert (inst.operands[i].writeback);
8349 inst.instruction |= WRITE_BACK;
8353 inst.error = _("instruction does not accept unindexed addressing");
8357 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
8358 && (((inst.instruction & 0x000f0000) >> 16)
8359 == ((inst.instruction & 0x0000f000) >> 12)))
8360 as_warn ((inst.instruction & LOAD_BIT)
8365 /* inst.operands[i] was set up by parse_address. Encode it into an
8372 const bool is_pc = (inst.operands[i].reg == REG_PC);
8376 if (inst.operands[i].immisreg)
8378 constraint ((inst.operands[i].imm == REG_PC
8379 || (is_pc && inst.operands[i].writeback)),
8381 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
8382 inst.instruction |= inst.operands[i].imm;
8383 if (!inst.operands[i].negative)
8384 inst.instruction |= INDEX_UP;
8385 if (inst.operands[i].shifted)
8387 if (inst.operands[i].shift_kind == SHIFT_RRX)
8388 inst.instruction |= SHIFT_ROR << 5;
8391 inst.instruction |= inst.operands[i].shift_kind << 5;
8392 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
8396 else /* immediate offset in inst.relocs[0] */
8398 if (is_pc && !inst.relocs[0].pc_rel)
8400 const bool is_load = ((inst.instruction & LOAD_BIT) != 0);
8405 constraint ((is_t || inst.operands[i].writeback),
8415 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
8418 if (!inst.operands[i].negative)
8419 inst.instruction |= INDEX_UP;
8420 inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM;
8425 /* inst.operands[i] was set up by parse_address. Encode it into an
8433 if (inst.operands[i].immisreg && inst.operands[i].shifted)
8435 inst.error = _("instruction does not accept scaled register index");
8441 if (inst.operands[i].immisreg)
8443 constraint ((inst.operands[i].imm == REG_PC
8444 || (is_t && inst.operands[i].reg == REG_PC)),
8446 constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback,
8448 inst.instruction |= inst.operands[i].imm;
8449 if (!inst.operands[i].negative)
8450 inst.instruction |= INDEX_UP;
8452 else /* immediate offset in inst.relocs[0] */
8454 constraint ((inst.operands[i].reg == REG_PC && !inst.relocs[0].pc_rel
8455 && inst.operands[i].writeback),
8457 inst.instruction |= HWOFFSET_IMM;
8458 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
8461 if (!inst.operands[i].negative)
8462 inst.instruction |= INDEX_UP;
8464 inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM8;
8479 inst.instruction |= immbits & 0xf;
8480 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
8481 inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24);
8715 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8717 it can, convert inst.instruction to that move instruction and
8718 return true; if it can't, convert inst.instruction to a literal-pool
8720 current context, set inst.error and return TRUE.
8722 inst.operands[i] describes the destination register. */
8732 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
8736 if ((inst.instruction & tbit) == 0)
8738 inst.error = _("invalid pseudo operation");
8742 if (inst.relocs[0].exp.X_op != O_constant
8743 && inst.relocs[0].exp.X_op != O_symbol
8744 && inst.relocs[0].exp.X_op != O_big)
8746 inst.error = _("constant expression expected");
8750 if (inst.relocs[0].exp.X_op == O_constant
8751 || inst.relocs[0].exp.X_op == O_big)
8754 if (inst.relocs[0].exp.X_op == O_big)
8758 if (inst.relocs[0].exp.X_add_number <= 0) /* FP value. */
8780 inst.error = _("constant expression not supported");
8795 v = inst.relocs[0].exp.X_add_number;
8797 if (!inst.operands[i].issingle)
8806 && inst.operands[i].reg != 13
8807 && inst.operands[i].reg != 15)
8826 inst.instruction = (0xf04f0000 /* MOV.W. */
8827 | (inst.operands[i].reg << 8));
8829 inst.instruction |= (isNegated ? 0x200000 : 0);
8830 inst.instruction |= (newimm & 0x800) << 15;
8831 inst.instruction |= (newimm & 0x700) << 4;
8832 inst.instruction |= (newimm & 0x0ff);
8841 inst.instruction = 0xf2400000; /* MOVW. */
8842 inst.instruction |= (inst.operands[i].reg << 8);
8843 inst.instruction |= (imm & 0xf000) << 4;
8844 inst.instruction |= (imm & 0x0800) << 15;
8845 inst.instruction |= (imm & 0x0700) << 4;
8846 inst.instruction |= (imm & 0x00ff);
8851 inst.size_req = 0;
8863 inst.instruction &= LITERAL_MASK;
8864 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
8865 inst.instruction |= value & 0xfff;
8873 inst.instruction &= LITERAL_MASK;
8874 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
8875 inst.instruction |= value & 0xfff;
8883 unsigned immlo = inst.operands[1].imm;
8884 unsigned immhi = inst.operands[1].regisimm
8885 ? inst.operands[1].reg
8886 : inst.relocs[0].exp.X_unsigned
8902 inst.instruction = (inst.instruction & VLDR_VMOV_SAME)
8910 inst.instruction |= (0x7U << 29) | (0xF << 24);
8912 inst.instruction |= (0xFU << 28) | (0x1 << 25);
8922 if (inst.operands[i].issingle
8923 && is_quarter_float (inst.operands[1].imm)
8926 inst.operands[1].imm =
8937 else if (!inst.operands[1].issingle
8943 inst.operands[1].imm =
8952 if (add_to_lit_pool ((!inst.operands[i].isvec
8953 || inst.operands[i].issingle) ? 4 : 8) == FAIL)
8956 inst.operands[1].reg = REG_PC;
8957 inst.operands[1].isreg = 1;
8958 inst.operands[1].preind = 1;
8959 inst.relocs[0].pc_rel = 1;
8960 inst.relocs[0].type = (thumb_p
8968 /* inst.operands[i] was set up by parse_address. Encode it into an
8979 if (!inst.operands[i].isreg)
8982 if (! inst.operands[0].isvec)
8984 inst.error = _("invalid co-processor operand");
8991 inst.instruction |= inst.operands[i].reg << 16;
8993 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
8995 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
8997 gas_assert (!inst.operands[i].writeback);
9000 inst.error = _("instruction does not support unindexed addressing");
9003 inst.instruction |= inst.operands[i].imm;
9004 inst.instruction |= INDEX_UP;
9008 if (inst.operands[i].preind)
9009 inst.instruction |= PRE_INDEX;
9011 if (inst.operands[i].writeback)
9013 if (inst.operands[i].reg == REG_PC)
9015 inst.error = _("pc may not be used with write-back");
9020 inst.error = _("instruction does not support writeback");
9023 inst.instruction |= WRITE_BACK;
9027 inst.relocs[0].type = (bfd_reloc_code_real_type) reloc_override;
9028 else if ((inst.relocs[0].type < BFD_RELOC_ARM_ALU_PC_G0_NC
9029 || inst.relocs[0].type > BFD_RELOC_ARM_LDC_SB_G2)
9030 && inst.relocs[0].type != BFD_RELOC_ARM_LDR_PC_G0)
9033 inst.relocs[0].type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
9035 inst.relocs[0].type = BFD_RELOC_ARM_CP_OFF_IMM;
9039 if (!inst.operands[i].negative)
9040 inst.instruction |= INDEX_UP;
9057 inst.instruction |= inst.operands[0].reg << 12;
9063 inst.instruction |= inst.operands[0].reg << 16;
9069 inst.instruction |= inst.operands[0].reg << 12;
9070 inst.instruction |= inst.operands[1].reg;
9076 inst.instruction |= inst.operands[0].reg;
9077 inst.instruction |= inst.operands[1].reg << 16;
9083 inst.instruction |= inst.operands[0].reg << 12;
9084 inst.instruction |= inst.operands[1].reg << 16;
9090 inst.instruction |= inst.operands[0].reg << 16;
9091 inst.instruction |= inst.operands[1].reg << 12;
9097 inst.instruction |= inst.operands[0].reg << 8;
9098 inst.instruction |= inst.operands[1].reg << 16;
9121 unsigned Rn = inst.operands[2].reg;
9123 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
9125 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
9137 inst.instruction |= inst.operands[0].reg << 12;
9138 inst.instruction |= inst.operands[1].reg;
9139 inst.instruction |= Rn << 16;
9145 inst.instruction |= inst.operands[0].reg << 12;
9146 inst.instruction |= inst.operands[1].reg << 16;
9147 inst.instruction |= inst.operands[2].reg;
9153 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
9154 constraint (((inst.relocs[0].exp.X_op != O_constant
9155 && inst.relocs[0].exp.X_op != O_illegal)
9156 || inst.relocs[0].exp.X_add_number != 0),
9158 inst.instruction |= inst.operands[0].reg;
9159 inst.instruction |= inst.operands[1].reg << 12;
9160 inst.instruction |= inst.operands[2].reg << 16;
9166 inst.instruction |= inst.operands[0].imm;
9179 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
9183 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
9184 inst.relocs[0].pc_rel = 1;
9185 inst.relocs[0].exp.X_add_number -= 8;
9188 && inst.relocs[0].exp.X_op == O_symbol
9189 && inst.relocs[0].exp.X_add_symbol != NULL
9190 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
9191 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
9192 inst.relocs[0].exp.X_add_number |= 1;
9203 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
9207 inst.relocs[0].type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
9208 inst.relocs[0].pc_rel = 1;
9209 inst.size = INSN_SIZE * 2;
9210 inst.relocs[0].exp.X_add_number -= 8;
9213 && inst.relocs[0].exp.X_op == O_symbol
9214 && inst.relocs[0].exp.X_add_symbol != NULL
9215 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
9216 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
9217 inst.relocs[0].exp.X_add_number |= 1;
9223 constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9224 && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
9226 if (!inst.operands[1].present)
9227 inst.operands[1].reg = inst.operands[0].reg;
9228 inst.instruction |= inst.operands[0].reg << 12;
9229 inst.instruction |= inst.operands[1].reg << 16;
9236 if (inst.operands[0].present)
9237 inst.instruction |= inst.operands[0].imm;
9239 inst.instruction |= 0xf;
9245 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
9249 inst.instruction |= inst.operands[0].reg << 12;
9250 inst.instruction |= inst.operands[1].imm << 7;
9251 inst.instruction |= (msb - 1) << 16;
9261 if (!inst.operands[1].isreg)
9262 inst.operands[1].reg = REG_PC;
9264 msb = inst.operands[2].imm + inst.operands[3].imm;
9268 inst.instruction |= inst.operands[0].reg << 12;
9269 inst.instruction |= inst.operands[1].reg;
9270 inst.instruction |= inst.operands[2].imm << 7;
9271 inst.instruction |= (msb - 1) << 16;
9277 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
9279 inst.instruction |= inst.operands[0].reg << 12;
9280 inst.instruction |= inst.operands[1].reg;
9281 inst.instruction |= inst
9282 inst.instruction |= (inst.operands[3].imm - 1) << 16;
9295 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
9298 inst.instruction |= inst.operands[0].imm & 0xf;
9304 if (inst.operands[0].hasreloc)
9306 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
9307 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
9309 inst.relocs[0].type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
9314 inst.relocs[0].type = (bfd_reloc_code_real_type) default_reloc;
9315 inst.relocs[0].pc_rel = 1;
9335 if (inst.cond == COND_ALWAYS)
9350 into inst.instruction.
9356 if (inst.operands[0].isreg)
9360 if (inst.operands[0].reg == REG_PC)
9363 inst.instruction |= inst.operands[0].reg;
9371 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9372 inst.instruction = 0xfa000000;
9382 if (inst.operands[0].reg == REG_PC)
9385 inst.instruction |= inst.operands[0].reg;
9399 inst.relocs[0].type = BFD_RELOC_ARM_V4BX;
9408 if (inst.operands[0].reg == REG_PC)
9411 inst.instruction |= inst.operands[0].reg;
9420 inst.instruction |= inst.operands[0].reg << 8;
9421 inst.instruction |= inst.operands[1].imm << 20;
9422 inst.instruction |= inst.operands[2].reg << 12;
9423 inst.instruction |= inst.operands[3].reg << 16;
9424 inst.instruction |= inst.operands[4].reg;
9425 inst.instruction |= inst.operands[5].imm << 5;
9431 inst.instruction |= inst.operands[0].reg << 16;
9490 Rd = inst.operands[2].reg;
9493 if (inst.instruction == 0xee000010
9494 || inst.instruction == 0xfe000010)
9504 if (inst.instruction == 0xe000010)
9513 if (inst.operands[0].reg == r->cp
9514 && inst.operands[1].imm == r->opc1
9515 && inst.operands[3].reg == r->crn
9516 && inst.operands[4].reg == r->crm
9517 && inst.operands[5].imm == r->opc2)
9526 inst.instruction |= inst.operands[0].reg << 8;
9527 inst.instruction |= inst.operands[1].imm << 21;
9528 inst.instruction |= Rd << 12;
9529 inst.instruction |= inst.operands[3].reg << 16;
9530 inst.instruction |= inst.operands[4].reg;
9531 inst.instruction |= inst.operands[5].imm << 5;
9552 Rd = inst.operands[2].reg;
9553 Rn = inst.operands[3].reg;
9567 if ((inst.instruction & 0x0FF00000) == 0x0C500000)
9574 inst.instruction |= inst.operands[0].reg << 8;
9575 inst.instruction |= inst.operands[1].imm << 4;
9576 inst.instruction |= Rd << 12;
9577 inst.instruction |= Rn << 16;
9578 inst.instruction |= inst.operands[4].reg;
9584 inst.instruction |= inst.operands[0].imm << 6;
9585 if (inst.operands[1].present)
9587 inst.instruction |= CPSI_MMOD;
9588 inst.instruction |= inst.operands[1].imm;
9595 inst.instruction |= inst.operands[0].imm;
9603 Rd = inst.operands[0].reg;
9604 Rn = (inst.operands[1].present
9605 ? inst.operands[1].reg : Rd);
9606 Rm = inst.operands[2].reg;
9612 inst.instruction |= Rd << 16;
9613 inst.instruction |= Rn << 0;
9614 inst.instruction |= Rm << 8;
9625 inst.size = 0;
9629 now_pred.mask = (inst.instruction & 0xf) | 0x10;
9630 now_pred.cc = inst.operands[0].imm;
9646 int base_reg = inst.operands[0].reg;
9647 int range = inst.operands[1].imm;
9650 inst.instruction |= base_reg << 16;
9651 inst.instruction |= range;
9653 if (inst.operands[1].writeback)
9654 inst.instruction |= LDM_TYPE_2_OR_3;
9656 if (inst.operands[0].writeback)
9658 inst.instruction |= WRITE_BACK;
9660 if (inst.instruction & LOAD_BIT)
9663 if ((inst.instruction & LDM_TYPE_2_OR_3)
9673 if (inst.instruction & LDM_TYPE_2_OR_3)
9686 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
9693 inst.instruction &= A_COND_MASK;
9694 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
9695 inst.instruction |= one_reg << 12;
9714 constraint (inst.operands[0].reg % 2 != 0,
9716 constraint (inst.operands[1].present
9717 && inst.operands[1].reg != inst.operands[0].reg + 1,
9719 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
9720 constraint (!inst.operands[2].isreg, _("'[' expected"));
9722 if (!inst.operands[1].present)
9723 inst.operands[1].reg = inst.operands[0].reg + 1;
9729 if (inst.operands[2].reg == inst.operands[1].reg
9730 && (inst.operands[2].writeback || inst.operands[2].postind))
9734 if (!(inst.instruction & V4_STR_BIT))
9738 if (inst.operands[2].immisreg
9739 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
9740 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
9743 inst.instruction |= inst.operands[0].reg << 12;
9750 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
9751 || inst.operands[1].postind || inst.operands[1].writeback
9752 || inst.operands[1].immisreg || inst.operands[1].shifted
9753 || inst.operands[1].negative
9765 || (inst.operands[1].reg == REG_PC),
9768 constraint (inst.relocs[0].exp.X_op != O_constant
9769 || inst.relocs[0].exp.X_add_number != 0,
9772 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
9774 inst.instruction |= inst.operands[0].reg << 12;
9775 inst.instruction |= inst.operands[1].reg << 16;
9776 inst.relocs[0].type = BFD_RELOC_UNUSED;
9782 constraint (inst.operands[0].reg % 2 != 0,
9784 constraint (inst.operands[1].present
9785 && inst.operands[1].reg != inst.operands[0].reg + 1,
9789 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
9791 inst.instruction |= inst.operands[0].reg << 12;
9792 inst.instruction |= inst.operands[2].reg << 16;
9800 constraint (!(inst.operands[1].immisreg)
9801 && (inst.operands[0].reg == REG_PC
9802 && inst.operands[1].reg == REG_PC
9803 && (inst.relocs[0].exp.X_add_number & 0x3)),
9810 inst.instruction |= inst.operands[0].reg << 12;
9811 if (!inst.operands[1].isreg)
9823 if (inst.operands[1].preind)
9825 constraint (inst.relocs[0].exp.X_op != O_constant
9826 || inst.relocs[0].exp.X_add_number != 0,
9829 inst.operands[1].preind = 0;
9830 inst.operands[1].postind = 1;
9831 inst.operands[1].writeback = 1;
9833 inst.instruction |= inst.operands[0].reg << 12;
9842 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
9843 inst.instruction |= inst.operands[0].reg << 12;
9844 if (!inst.operands[1].isreg)
9855 if (inst.operands[1].preind)
9857 constraint (inst
9858 || inst.relocs[0].exp.X_add_number != 0,
9861 inst.operands[1].preind = 0;
9862 inst.operands[1].postind = 1;
9863 inst.operands[1].writeback = 1;
9865 inst.instruction |= inst.operands[0].reg << 12;
9874 inst.instruction |= inst.operands[0].reg << 8;
9875 inst.instruction |= inst.operands[1].reg << 12;
9883 if (inst.operands[0].reg == inst.operands[1].reg
9885 && !(inst.instruction & 0x00400000))
9888 inst.instruction |= inst.operands[0].reg << 16;
9889 inst.instruction |= inst.operands[1].reg;
9890 inst.instruction |= inst.operands[2].reg << 8;
9891 inst.instruction |= inst.operands[3].reg << 12;
9897 constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9898 && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
9900 inst.instruction |= inst.operands[0].reg << 12;
9911 top = (inst.instruction & 0x00400000) != 0;
9912 constraint (top && inst.relocs[0].type == BFD_RELOC_ARM_MOVW,
9914 constraint (!top && inst.relocs[0].type == BFD_RELOC_ARM_MOVT,
9916 inst.instruction |= inst.operands[0].reg << 12;
9917 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
9919 imm = inst.relocs[0].exp.X_add_number;
9921 inst.instruction |= (imm & 0x00000fff);
9922 inst.instruction |= (imm & 0x0000f000) << 4;
9929 if (inst.operands[0].isvec)
9931 if (inst.operands[1].reg != 1)
9933 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
9934 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
9937 else if (inst.operands[1].isvec)
9948 if (inst.operands[0].isvec)
9959 unsigned Rt = inst.operands[0].reg;
9963 inst.error = BAD_SP;
9967 switch (inst.operands[1].reg)
9995 if (inst.operands[0].reg != 2
10005 if (!inst.operands[0].isvec && Rt == REG_PC)
10007 inst.error = BAD_PC;
10013 inst.instruction |= (inst.operands[1].reg << 16);
10014 inst.instruction |= (Rt << 12);
10020 unsigned Rt = inst.operands[1].reg;
10026 inst.error = BAD_PC;
10030 switch (inst.operands[0].reg)
10058 if (inst.operands[0].reg != 2
10069 inst.instruction |= (inst.operands[0].reg << 16);
10070 inst.instruction |= (Rt << 12);
10081 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10082 inst.instruction |= inst.operands[0].reg << 12;
10084 if (inst.operands[1].isreg)
10086 br = inst.operands[1].reg;
10093 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
10096 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
10099 inst.instruction |= br;
10112 inst.instruction |= inst.operands[0].imm;
10113 if (inst.operands[1].isreg)
10114 inst.instruction |= inst.operands[1].reg;
10117 inst.instruction |= INST_IMMEDIATE;
10118 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
10119 inst.relocs[0].pc_rel = 0;
10126 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
10128 if (!inst.operands[2].present)
10129 inst.operands[2].reg = inst.operands[0].reg;
10130 inst.instruction |= inst.operands[0].reg << 16;
10131 inst.instruction |= inst.operands[1].reg;
10132 inst.instruction |= inst.operands[2].reg << 8;
10134 if (inst.operands[0].reg == inst.operands[1].reg
10148 inst.instruction |= inst.operands[0].reg << 12;
10149 inst.instruction |= inst.operands[1].reg << 16;
10150 inst.instruction |= inst.operands[2].reg;
10151 inst.instruction |= inst.operands[3].reg << 8;
10154 if (inst.operands[0].reg == inst.operands[1].reg)
10158 if ((inst.operands[0].reg == inst.operands[2].reg
10159 || inst.operands[1].reg == inst.operands[2].reg)
10167 if (inst.operands[0].present
10171 inst.instruction &= 0xf0000000;
10172 inst.instruction |= 0x0320f000;
10173 if (inst.operands[0].present)
10174 inst.instruction |= inst.operands[0].imm;
10186 inst.instruction |= inst.operands[0].reg << 12;
10187 inst.instruction |= inst.operands[1].reg << 16;
10188 inst.instruction |= inst.operands[2].reg;
10189 if (inst.operands[3].present)
10198 if (!inst.operands[3].present)
10202 inst.instruction &= 0xfff00010;
10203 inst.instruction |= inst.operands[0].reg << 12;
10204 inst.instruction |= inst.operands[1].reg;
10205 inst.instruction |= inst.operands[2].reg << 16;
10209 inst.instruction |= inst.operands[0].reg << 12;
10210 inst.instruction |= inst.operands[1].reg << 16;
10211 inst.instruction |= inst.operands[2].reg;
10226 constraint (!inst.operands[0].isreg,
10228 constraint (inst.operands[0].postind,
10230 constraint (inst.operands[0].writeback,
10232 constraint (!inst.operands[0].preind,
10241 constraint (!inst.operands[0].isreg,
10243 constraint (inst.operands[0].postind,
10245 constraint (inst.operands[0].writeback,
10247 constraint (!inst.operands[0].preind,
10250 inst.instruction &= ~PRE_INDEX;
10256 constraint (inst.operands[0].writeback,
10258 inst.operands[1] = inst.operands[0];
10259 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
10260 inst.operands[0].isreg = 1;
10261 inst.operands[0].writeback = 1;
10262 inst.operands[0].reg = REG_SP;
10275 inst.instruction |= inst.operands[0].reg << 16;
10276 if (inst.operands[0].writeback)
10277 inst.instruction |= WRITE_BACK;
10285 inst.instruction |= inst.operands[0].reg << 12;
10286 inst.instruction |= (inst.operands[1].imm - 1) << 16;
10287 inst.instruction |= inst.operands[2].reg;
10289 if (inst.operands[3].present)
10298 inst.instruction |= inst.operands[0].reg << 12;
10299 inst.instruction |= inst.operands[1].imm << 16;
10300 inst.instruction |= inst.operands[2].reg;
10302 if (inst.operands[3].present)
10311 inst.instruction |= inst.operands[0].reg << 12;
10312 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
10313 inst.instruction |= inst.operands[2].reg;
10319 inst.instruction |= inst.operands[0].reg << 12;
10320 inst.instruction |= inst.operands[1].imm << 16;
10321 inst.instruction |= inst.operands[2].reg;
10337 if (inst.operands[0].imm)
10338 inst.instruction |= 0x200;
10344 unsigned int Rm = (inst.operands[1].present
10345 ? inst.operands[1].reg
10346 : inst.operands[0].reg);
10348 inst.instruction |= inst.operands[0].reg << 12;
10349 inst.instruction |= Rm;
10350 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
10352 inst.instruction |= inst.operands[2].reg << 8;
10353 inst.instruction |= SHIFT_BY_REG;
10355 constraint (inst.operands[2].shifted,
10359 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
10365 unsigned int value = inst.relocs[0].exp.X_add_number;
10368 inst.relocs[0].type = BFD_RELOC_ARM_SMC;
10369 inst.relocs[0].pc_rel = 0;
10375 inst.relocs[0].type = BFD_RELOC_ARM_HVC;
10376 inst.relocs[0].pc_rel = 0;
10382 inst.relocs[0].type = BFD_RELOC_ARM_SWI;
10383 inst.relocs[0].pc_rel = 0;
10392 inst.instruction |= ((inst.operands[0].imm & 1) << 9);
10401 inst.instruction |= (inst.operands[0].imm << 3);
10412 inst.instruction |= inst.operands[0].reg << 16;
10413 inst.instruction |= inst.operands[1].reg;
10414 inst.instruction |= inst.operands[2].reg << 8;
10415 inst.instruction |= inst.operands[3].reg << 12;
10426 inst.instruction |= inst.operands[0].reg << 12;
10427 inst.instruction |= inst.operands[1].reg << 16;
10428 inst.instruction |= inst.operands[2].reg;
10429 inst.instruction |= inst.operands[3].reg << 8;
10431 if (inst.operands[0].reg == inst.operands[1].reg)
10442 inst.instruction |= inst.operands[0].reg << 16;
10443 inst.instruction |= inst.operands[1].reg;
10444 inst.instruction |= inst.operands[2].reg << 8;
10455 if (inst.operands[0].present)
10457 reg = inst.operands[0].reg;
10463 inst.instruction |= reg << 16;
10464 inst.instruction |= inst.operands[1].imm;
10465 if (inst.operands[0].writeback || inst.operands[1].writeback)
10466 inst.instruction |= WRITE_BACK;
10474 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10475 || inst.operands[2].postind || inst.operands[2].writeback
10476 || inst.operands[2].immisreg || inst.operands[2].shifted
10477 || inst.operands[2].negative
10479 || (inst.operands[2].reg == REG_PC),
10482 constraint (inst.operands[0].reg == inst.operands[1].reg
10483 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10485 constraint (inst.relocs[0].exp.X_op != O_constant
10486 || inst.relocs[0].exp.X_add_number != 0,
10489 inst.instruction |= inst.operands[0].reg << 12;
10490 inst.instruction |= inst.operands[1].reg;
10491 inst.instruction |= inst.operands[2].reg << 16;
10492 inst.relocs[0].type = BFD_RELOC_UNUSED;
10498 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10499 || inst.operands[2].postind || inst.operands[2].writeback
10500 || inst.operands[2].immisreg || inst.operands[2].shifted
10501 || inst.operands[2].negative,
10504 constraint (inst.operands[0].reg == inst.operands[1].reg
10505 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10513 constraint (inst.operands[1].reg % 2 != 0,
10515 constraint (inst.operands[2].present
10516 && inst.operands[2].reg != inst.operands[1].reg + 1,
10520 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
10522 constraint (inst.operands[0].reg == inst.operands[1].reg
10523 || inst.operands[0].reg == inst.operands[1].reg + 1
10524 || inst.operands[0].reg == inst.operands[3].reg,
10527 inst.instruction |= inst.operands[0].reg << 12;
10528 inst.instruction |= inst.operands[1].reg;
10529 inst.instruction |= inst.operands[3].reg << 16;
10536 constraint (inst.operands[0].reg == inst.operands[1].reg
10537 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10545 constraint (inst.operands[0].reg == inst.operands[1].reg
10546 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10562 inst.instruction |= inst.operands[0].reg << 12;
10563 inst.instruction |= inst.operands[1].reg << 16;
10564 inst.instruction |= inst.operands[2].reg;
10565 inst.instruction |= inst.operands[3].imm << 10;
10577 inst.instruction |= inst.operands[0].reg << 12;
10578 inst.instruction |= inst.operands[1].reg;
10579 inst.instruction |= inst.operands[2].imm << 10;
10593 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10594 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
10600 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10601 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
10602 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
10608 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10614 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10615 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
10621 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10622 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
10632 inst.instruction |= inst.operands[0].reg << 12;
10633 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
10639 constraint (inst.operands[2].imm != 2,
10641 inst.instruction |= inst.operands[0].reg << 12;
10642 inst.instruction |= inst.operands[1].reg << 16;
10643 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
10653 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
10654 inst.instruction |= inst.operands[1].reg << 12;
10660 constraint (inst.operands[0].imm != 2,
10662 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
10663 inst.instruction |= inst.operands[1].reg << 12;
10664 inst.instruction |= inst.operands[2].reg << 16;
10670 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10677 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10685 if (inst.operands[0].writeback)
10686 inst.instruction |= WRITE_BACK;
10690 inst.instruction |= inst.operands[0].reg << 16;
10691 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
10692 inst.instruction |= inst.operands[1].imm;
10700 if (inst.operands[0].writeback)
10701 inst.instruction |= WRITE_BACK;
10706 inst.instruction |= inst.operands[0].reg << 16;
10707 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10709 count = inst.operands[1].imm << 1;
10713 inst.instruction |= count;
10759 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10760 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
10766 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
10767 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10773 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10774 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
10784 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10785 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
10786 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
10792 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10802 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
10803 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10804 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
10811 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10812 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
10813 inst.instruction |= (inst.operands[1].imm & 0x0f);
10819 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10820 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
10821 inst.instruction |= (inst.operands[1].imm & 0x0f);
10827 int immbits = srcsize - inst.operands[1].imm;
10831 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10833 inst.error = _("immediate value out of range, expected range [0, 16]");
10838 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10840 inst.error = _("immediate value out of range, expected range [1, 32]");
10844 inst.instruction |= (immbits & 1) << 5;
10845 inst.instruction |= (immbits >> 1);
10851 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10858 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10865 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10872 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10882 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
10888 inst.instruction |= inst.operands[0].reg << 12;
10889 inst.instruction |= inst.operands[1].imm;
10895 inst.instruction |= inst.operands[0].reg << 12;
10896 inst.instruction |= inst.operands[1].reg << 16;
10897 inst.instruction |= inst.operands[2].imm;
10903 inst.instruction |= inst.operands[0].reg << 16;
10904 inst.instruction |= inst.operands[1].reg << 12;
10905 inst.instruction |= inst.operands[2].imm;
10911 inst.instruction |= inst.operands[0].reg << 5;
10912 inst.instruction |= inst.operands[1].reg;
10913 inst.instruction |= inst.operands[2].reg << 12;
10919 inst.instruction |= inst.operands[0].reg << 12;
10920 inst.instruction |= inst.operands[1].reg << 16;
10921 inst.instruction |= inst.operands[2].reg;
10922 inst.instruction |= inst.operands[3].imm << 20;
10928 inst.instruction |= inst.operands[0].reg << 12;
10929 inst.instruction |= inst.operands[1].reg << 16;
10930 inst.instruction |= inst.operands[2].reg;
10931 inst.instruction |= inst.operands[3].imm << 21;
10938 inst.instruction |= inst.operands[0].reg << 12;
10939 inst.instruction |= inst.operands[1].reg << 16;
10940 inst.instruction |= inst.operands[1].reg;
10947 inst.instruction |= inst.operands[0].reg << 12;
10959 if (!inst.operands[0].isreg)
10961 constraint (inst.cond != COND_ALWAYS, BAD_COND);
10962 inst.instruction |= 0xf0000000;
10965 inst.instruction |= inst.operands[0].reg << 12;
10972 inst.instruction |= inst.operands[0].reg << 12;
10974 && inst.operands[1].immisreg)
10976 inst.instruction &= ~0x1a000ff;
10977 inst.instruction |= (0xfU << 28);
10978 if (inst.operands[1].preind)
10979 inst.instruction |= PRE_INDEX;
10980 if (!inst.operands[1].negative)
10981 inst.instruction |= INDEX_UP;
10982 if (inst.operands[1].writeback)
10983 inst.instruction |= WRITE_BACK;
10984 inst.instruction |= inst.operands[1].reg << 16;
10985 inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
10986 inst.instruction |= inst.operands[1].imm;
10995 inst.instruction |= inst.operands[0].reg << 12;
10996 inst.instruction |= inst.operands[1].reg << 16;
10997 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
10998 inst.instruction |= (inst.operands[2].imm & 0x0f);
11005 inst.instruction |= inst.operands[0].reg;
11006 inst.instruction |= inst.operands[0].reg << 12;
11007 inst.instruction |= inst.operands[0].reg << 16;
11013 if (inst.operands[2].isreg)
11019 if (inst.operands[2].imm == 0)
11021 switch ((inst.instruction >> 20) & 0xf)
11028 inst.operands[2].imm = 16;
11029 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
11036 inst.operands[2].imm = 32;
11037 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
11046 wrn = (inst.instruction >> 16) & 0xf;
11047 inst.instruction &= 0xff0fff0f;
11048 inst.instruction |= wrn;
11055 inst.operands[2].imm &= 0x1f;
11056 inst.instruction |= (0xfU << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
11073 inst.instruction |= inst.operands[1].reg;
11074 inst.instruction |= inst.operands[2].reg << 12;
11084 inst.instruction |= inst.operands[1].reg << 12;
11085 inst.instruction |= inst.operands[2].reg << 16;
11095 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
11096 inst.instruction |= inst.operands[0].reg << 12;
11097 inst.instruction |= inst.operands[1].reg << 16;
11103 /* inst.operands[i] is a shifted-register operand; encode
11104 it into inst.instruction in the format used by Thumb32. */
11109 unsigned int value = inst.relocs[0].exp.X_add_number;
11110 unsigned int shift = inst.operands[i].shift_kind;
11112 constraint (inst.operands[i].immisreg,
11114 inst.instruction |= inst.operands[i].reg;
11116 inst.instruction |= SHIFT_ROR << 4;
11119 constraint (inst
11132 inst.instruction |= shift << 4;
11133 inst.instruction |= (value & 0x1c) << 10;
11134 inst.instruction |= (value & 0x03) << 6;
11139 /* inst.operands[i] was set up by parse_address. Encode it into a
11149 const bool is_pc = (inst.operands[i].reg == REG_PC);
11151 constraint (!inst.operands[i].isreg,
11154 inst.instruction |= inst.operands[i].reg << 16;
11155 if (inst.operands[i].immisreg)
11159 constraint (inst.operands[i].negative,
11161 constraint (inst.operands[i].postind,
11163 constraint (inst.operands[i].writeback,
11165 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
11168 inst.instruction |= inst.operands[i].imm;
11169 if (inst.operands[i].shifted)
11171 constraint (inst.relocs[0].exp.X_op != O_constant,
11173 constraint (inst.relocs[0].exp.X_add_number < 0
11174 || inst.relocs[0].exp.X_add_number > 3,
11176 inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
11178 inst.relocs[0].type = BFD_RELOC_UNUSED;
11180 else if (inst.operands[i].preind)
11182 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
11183 constraint (is_t && inst.operands[i].writeback,
11185 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
11190 inst.instruction |= 0x01000000;
11191 if (inst.operands[i].writeback)
11192 inst.instruction |= 0x00200000;
11196 inst.instruction |= 0x00000c00;
11197 if (inst.operands[i].writeback)
11198 inst.instruction |= 0x00000100;
11200 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
11202 else if (inst.operands[i].postind)
11204 gas_assert (inst.operands[i].writeback);
11209 inst.instruction |= 0x00200000;
11211 inst.instruction |= 0x00000900;
11212 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
11215 inst.error = _("instruction does not accept unindexed addressing");
11360 Rd = inst.operands[0].reg;
11361 Rn = inst.operands[1].reg;
11370 inst.instruction |= (Rn << 16) | (Rd << 8);
11371 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
11374 /* Parse an add or subtract instruction. We get here with inst.instruction
11382 Rd = inst.operands[0].reg;
11383 Rs = (inst.operands[1].present
11384 ? inst.operands[1].reg /* Rd, Rs, foo */
11385 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11396 flags = (inst.instruction == T_MNEM_adds
11397 || inst.instruction == T_MNEM_subs);
11402 if (!inst.operands[2].isreg)
11409 add = (inst.instruction == T_MNEM_add
11410 || inst.instruction == T_MNEM_adds);
11412 if (inst.size_req != 4)
11431 inst.instruction = THUMB_OP16(opcode);
11432 inst.instruction |= (Rd << 4) | Rs;
11433 if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11434 || (inst.relocs[0].type
11437 if (inst.size_req == 2)
11438 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11440 inst.relax = opcode;
11444 constraint (inst.size_req == 2, _("cannot honor width suffix"));
11446 if (inst.size_req == 4
11447 || (inst.size_req != 2 && !opcode))
11449 constraint ((inst.relocs[0].type
11451 && (inst.relocs[0].type
11457 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
11459 constraint (inst.relocs[0].exp.X_op != O_constant,
11461 constraint (inst.relocs[0].exp.X_add_number < 0
11462 || inst.relocs[0].exp.X_add_number > 0xff,
11464 inst.instruction = T2_SUBS_PC_LR
11465 | inst.relocs[0].exp.X_add_number;
11466 inst.relocs[0].type = BFD_RELOC_UNUSED;
11472 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
11473 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
11477 inst.instruction = THUMB_OP32 (inst.instruction);
11478 inst.instruction = (inst.instruction & 0xe1ffffff)
11481 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
11483 inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_IMM;
11485 inst.instruction |= Rd << 8;
11486 inst.instruction |= Rs << 16;
11491 unsigned int value = inst.relocs[0].exp.X_add_number;
11492 unsigned int shift = inst.operands[2].shift_kind;
11494 Rn = inst.operands[2].reg;
11496 if (!inst.operands[2].shifted && inst.size_req != 4)
11503 inst.instruction = ((inst.instruction == T_MNEM_adds
11504 || inst.instruction == T_MNEM_add)
11507 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
11511 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
11524 inst.instruction = T_OPCODE_ADD_HI;
11525 inst.instruction |= (Rd & 8) << 4;
11526 inst.instruction |= (Rd & 7);
11527 inst.instruction |= Rn << 3;
11540 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
11542 inst.instruction = THUMB_OP32 (inst.instruction);
11543 inst.instruction |= Rd << 8;
11544 inst.instruction |= Rs << 16;
11554 constraint (inst.instruction == T_MNEM_adds
11555 || inst.instruction == T_MNEM_subs,
11558 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
11564 inst.instruction = (inst.instruction == T_MNEM_add
11566 inst.instruction |= (Rd << 4) | Rs;
11567 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11571 Rn = inst.operands[2].reg;
11572 constraint (inst.operands[2].shifted, _("unshifted register required"));
11578 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
11579 inst.instruction = T_OPCODE_ADD_HI;
11580 inst.instruction |= (Rd & 8) << 4;
11581 inst.instruction |= (Rd & 7);
11583 inst.instruction |= Rn << 3;
11585 inst.instruction |= Rs << 3;
11591 inst.instruction = (inst.instruction == T_MNEM_add
11593 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
11603 Rd = inst.operands[0].reg;
11606 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
11609 inst.relax = inst.instruction;
11610 inst.instruction = THUMB_OP16 (inst.instruction);
11611 inst.instruction |= Rd << 4;
11613 else if (unified_syntax && inst.size_req != 2)
11616 inst.instruction = THUMB_OP32 (inst.instruction);
11617 inst.instruction |= Rd << 8;
11618 inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_PC12;
11619 inst.relocs[0].pc_rel = 1;
11624 inst.instruction = THUMB_OP16 (inst.instruction);
11625 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11626 inst.relocs[0].exp.X_add_number -= 4; /* PC relative adjust. */
11627 inst.relocs[0].pc_rel = 1;
11628 inst.instruction |= Rd << 4;
11631 if (inst.relocs[0].exp.X_op == O_symbol
11632 && inst.relocs[0].exp.X_add_symbol != NULL
11633 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
11634 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
11635 inst.relocs[0].exp.X_add_number += 1;
11649 Rd = inst.operands[0].reg;
11650 Rs = (inst.operands[1].present
11651 ? inst.operands[1].reg /* Rd, Rs, foo */
11652 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11653 Rn = inst.operands[2].reg;
11657 if (inst.operands[2].isreg)
11662 if (!inst.operands[2].isreg)
11666 inst.instruction = THUMB_OP32 (inst.instruction);
11667 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11668 inst.instruction |= Rd << 8;
11669 inst.instruction |= Rs << 16;
11670 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
11677 if (THUMB_SETS_FLAGS (inst.instruction))
11684 if (inst.operands[2].shifted)
11686 if (inst.size_req == 4)
11692 inst.instruction = THUMB_OP16 (inst.instruction);
11693 inst.instruction |= Rd;
11694 inst.instruction |= Rn << 3;
11699 constraint (inst.operands[2].shifted
11700 && inst.operands[2].immisreg,
11702 inst.instruction = THUMB_OP32 (inst.instruction);
11703 inst.instruction |= Rd << 8;
11704 inst.instruction |= Rs << 16;
11713 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11715 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
11721 inst.instruction = THUMB_OP16 (inst.instruction);
11722 inst.instruction |= Rd;
11723 inst.instruction |= Rn << 3;
11737 Rd = inst.operands[0].reg;
11738 Rs = (inst.operands[1].present
11739 ? inst.operands[1].reg /* Rd, Rs, foo */
11740 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11741 Rn = inst.operands[2].reg;
11745 if (inst.operands[2].isreg)
11750 if (!inst.operands[2].isreg)
11754 inst.instruction = THUMB_OP32 (inst.instruction);
11755 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11756 inst.instruction |= Rd << 8;
11757 inst.instruction |= Rs << 16;
11758 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
11765 if (THUMB_SETS_FLAGS (inst.instruction))
11772 if (inst.operands[2].shifted)
11774 if (inst.size_req == 4)
11781 inst.instruction = THUMB_OP16 (inst.instruction);
11782 inst.instruction |= Rd;
11783 inst.instruction |= Rn << 3;
11788 inst.instruction = THUMB_OP16 (inst.instruction);
11789 inst.instruction |= Rd;
11790 inst.instruction |= Rs << 3;
11796 constraint (inst.operands[2].shifted
11797 && inst.operands[2].immisreg,
11799 inst.instruction = THUMB_OP32 (inst.instruction);
11800 inst.instruction |= Rd << 8;
11801 inst.instruction |= Rs << 16;
11810 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11812 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
11816 inst.instruction = THUMB_OP16 (inst.instruction);
11817 inst.instruction |= Rd;
11820 inst.instruction |= Rn << 3;
11822 inst.instruction |= Rs << 3;
11832 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
11836 Rd = inst.operands[0].reg;
11838 inst.instruction |= Rd << 8;
11839 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
11840 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
11841 inst.instruction |= msb - 1;
11850 Rd = inst.operands[0].reg;
11855 if (!inst.operands[1].isreg)
11859 Rn = inst.operands[1].reg;
11863 msb = inst.operands[2].imm + inst.operands[3].imm;
11867 inst.instruction |= Rd << 8;
11868 inst.instruction |= Rn << 16;
11869 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
11870 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
11871 inst.instruction |= msb - 1;
11879 Rd = inst.operands[0].reg;
11880 Rn = inst.operands[1].reg;
11885 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
11887 inst.instruction |= Rd << 8;
11888 inst.instruction |= Rn << 16;
11889 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
11890 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
11891 inst.instruction |= inst.operands[3].imm - 1;
11899 into inst.instruction.
11909 if (inst.operands[0].isreg)
11911 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
11913 inst.instruction |= inst.operands[0].reg << 3;
11918 inst.instruction = 0xf000e800;
11930 cond = inst.cond;
11940 cond = inst.cond;
11945 opcode = inst.instruction;
11948 && (inst.size_req == 4
11949 || (inst.size_req != 2
11950 && (inst.operands[0].hasreloc
11951 || inst.relocs[0].exp.X_op == O_constant))))
11953 inst.instruction = THUMB_OP32(opcode);
11963 inst.instruction |= cond << 22;
11969 inst.instruction = THUMB_OP16(opcode);
11974 inst.instruction |= cond << 8;
11978 if (unified_syntax && inst.size_req != 2)
11979 inst.relax = opcode;
11981 inst.relocs[0].type = reloc;
11982 inst.relocs[0].pc_rel = 1;
11991 constraint (inst.cond != COND_ALWAYS,
11993 if (inst.operands[0].present)
11995 constraint (inst.operands[0].imm > range,
11997 inst.instruction |= inst.operands[0].imm;
12026 if (inst.relocs[0].type == BFD_RELOC_ARM_PLT32)
12027 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH23;
12034 if ( inst.relocs[0].exp.X_op == O_symbol
12035 && inst.relocs[0].exp.X_add_symbol != NULL
12036 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
12037 && ! THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
12038 inst.relocs[0].exp.X_add_symbol
12039 = find_real_start (inst.relocs[0].exp.X_add_symbol);
12047 inst.instruction |= inst.operands[0].reg << 3;
12059 Rm = inst.operands[0].reg;
12061 inst.instruction |= Rm << 16;
12070 Rd = inst.operands[0].reg;
12071 Rm = inst.operands[1].reg;
12076 inst.instruction |= Rd << 8;
12077 inst.instruction |= Rm << 16;
12078 inst.instruction |= Rm;
12088 constraint (inst.cond != COND_ALWAYS, BAD_COND);
12090 Rd = inst.operands[0].reg;
12091 switch (inst.instruction)
12097 Rn = inst.operands[1].reg;
12098 Rm = inst.operands[2].reg;
12099 cond = inst.operands[3].imm;
12107 Rn = inst.operands[1].reg;
12108 cond = inst.operands[2].imm;
12117 cond = inst.operands[1].imm;
12128 inst.instruction = THUMB_OP32 (inst.instruction);
12129 inst.instruction |= Rd << 8;
12130 inst.instruction |= Rn << 16;
12131 inst.instruction |= Rm;
12132 inst.instruction |= cond << 4;
12145 inst.instruction |= inst.operands[0].imm;
12153 && (inst.operands[1].present || inst.size_req == 4)
12156 unsigned int imod = (inst.instruction & 0x0030) >> 4;
12157 inst.instruction = 0xf3af8000;
12158 inst.instruction |= imod << 9;
12159 inst.instruction |= inst.operands[0].imm << 5;
12160 if (inst.operands[1].present)
12161 inst.instruction |= 0x100 | inst.operands[1].imm;
12166 && (inst.operands[0].imm & 4),
12169 constraint (inst.operands[1].present || inst.size_req == 4,
12172 inst.instruction |= inst.operands[0].imm;
12181 if (inst.size_req == 4)
12183 inst.instruction = THUMB_OP32 (T_MNEM_mov);
12184 inst.instruction |= inst.operands[0].reg << 8;
12185 inst.instruction |= inst.operands[1].reg;
12189 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
12190 inst.instruction |= (inst.operands[0].reg & 0x7);
12191 inst.instruction |= inst.operands[1].reg << 3;
12199 constraint (inst.operands[0].reg > 7, BAD_HIREG);
12200 inst.instruction |= inst.operands[0].reg;
12201 inst.relocs[0].pc_rel = 1;
12202 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH7;
12208 inst.instruction |= inst.operands[0].imm;
12216 Rd = inst.operands[0].reg;
12217 Rn = (inst.operands[1].present
12218 ? inst.operands[1].reg : Rd);
12219 Rm = inst.operands[2].reg;
12225 inst.instruction |= Rd << 8;
12226 inst.instruction |= Rn << 16;
12227 inst.instruction |= Rm;
12233 if (unified_syntax && inst.size_req == 4)
12234 inst.instruction = THUMB_OP32 (inst.instruction);
12236 inst.instruction = THUMB_OP16 (inst.instruction);
12242 unsigned int cond = inst.operands[0].imm;
12245 now_pred.mask = (inst.instruction & 0xf) | 0x10;
12253 unsigned int mask = inst.instruction & 0x000f;
12276 inst.instruction &= 0xfff0;
12277 inst.instruction |= mask;
12280 inst.instruction |= cond << 4;
12291 load = do_io && ((inst.instruction & (1 << 20)) != 0);
12295 inst.error = _("SP not allowed in register list");
12299 inst.error = _("having the base register in the register list when "
12307 inst.error = _("LR and PC should not both be in register list");
12315 inst.error = _("PC not allowed in register list");
12323 if (inst.instruction & (1 << 23))
12324 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
12326 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
12330 if (inst.instruction & (1 << 23))
12331 inst.instruction = 0x00800000; /* ia -> [base] */
12333 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
12336 inst.instruction |= 0xf8400000;
12338 inst.instruction |= 0x00100000;
12344 inst.instruction |= WRITE_BACK;
12346 inst.instruction |= mask;
12348 inst.instruction |= base << 16;
12357 constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
12359 constraint (inst.operands[1].writeback,
12370 if (inst.operands[0].reg == REG_SP)
12373 if (inst.operands[0].writeback
12374 && (inst.instruction == T_OPCODE_STMFD /* Push. */
12375 || inst.instruction == T_MNEM_ldmia)) /* Pop. */
12377 inst.instruction = (inst.instruction == T_MNEM_ldmia
12380 inst.operands[0] = inst.operands[1];
12385 if (!inst.operands[0].writeback
12386 && (inst.instruction == T_MNEM_stmia
12387 || inst.instruction == T_MNEM_ldmia)
12388 && (inst.operands[1].imm & (inst.operands[1].imm - 1)) == 0)
12391 if (inst.instruction == T_MNEM_ldmia)
12393 inst.instruction = THUMB_OP16 (opcode);
12394 inst.instruction |= ((ffs (inst.operands[1].imm) - 1) << 8);
12400 else if (inst.size_req != 4
12401 && (inst.instruction == T_MNEM_ldmia
12402 || inst.instruction == T_MNEM_stmia)
12403 && inst.operands[0].reg <= 7
12404 && !(inst.operands[1].imm & ~0xff))
12407 if (!inst.operands[0].writeback
12408 && (inst.operands[1].imm & (inst.operands[1].imm - 1)) == 0)
12411 if (inst.instruction == T_MNEM_stmia)
12414 inst.instruction = THUMB_OP16 (opcode);
12415 inst.instruction |= inst.operands[0].reg << 3;
12416 inst.instruction |= (ffs (inst.operands[1].imm) - 1);
12422 mask = 1 << inst.operands[0].reg;
12427 if (inst.instruction == T_MNEM_stmia
12428 ? inst.operands[0].writeback
12429 : (inst.operands[0].writeback
12430 == !(inst.operands[1].imm & mask)))
12435 if (inst.instruction == T_MNEM_stmia
12436 && (inst.operands[1].imm & mask)
12437 && (inst.operands[1].imm & (mask - 1)))
12439 inst.operands[0].reg);
12441 inst.instruction = THUMB_OP16 (inst.instruction);
12442 inst.instruction |= inst.operands[0].reg << 8;
12443 inst.instruction |= inst.operands[1].imm;
12451 if (inst.instruction < 0xffff)
12452 inst.instruction = THUMB_OP32 (inst.instruction);
12454 encode_thumb2_multi (true /* do_io */, inst.operands[0].reg,
12455 inst.operands[1].imm,
12456 inst.operands[0].writeback);
12461 constraint (inst.operands[0].reg > 7
12462 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
12463 constraint (inst.instruction != T_MNEM_ldmia
12464 && inst.instruction != T_MNEM_stmia,
12466 if (inst.instruction == T_MNEM_stmia)
12468 if (!inst.operands[0].writeback)
12470 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
12471 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
12473 inst.operands[0].reg);
12477 if (!inst.operands[0].writeback
12478 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
12480 else if (inst.operands[0].writeback
12481 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
12485 inst.instruction = THUMB_OP16 (inst.instruction);
12486 inst.instruction |= inst.operands[0].reg << 8;
12487 inst.instruction |= inst.operands[1].imm;
12494 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
12495 || inst.operands[1].postind || inst.operands[1].writeback
12496 || inst.operands[1].immisreg || inst.operands[1].shifted
12497 || inst.operands[1].negative,
12500 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
12502 inst.instruction |= inst.operands[0].reg << 12;
12503 inst.instruction |= inst.operands[1].reg << 16;
12504 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
12510 if (!inst.operands[1].present)
12512 constraint (inst.operands[0].reg == REG_LR,
12515 inst.operands[1].reg = inst.operands[0].reg + 1;
12517 constraint (inst.operands[0].reg == inst.operands[1].reg,
12520 inst.instruction |= inst.operands[0].reg << 12;
12521 inst.instruction |= inst.operands[1].reg << 8;
12522 inst.instruction |= inst.operands[2].reg << 16;
12531 if (inst.operands[0].isreg
12532 && !inst.operands[0].preind
12533 && inst.operands[0].reg == REG_PC)
12536 opcode = inst.instruction;
12539 if (!inst.operands[1].isreg)
12542 inst.instruction = THUMB_OP32 (opcode);
12546 if (inst.operands[1].isreg
12547 && !inst.operands[1].writeback
12548 && !inst.operands[1].shifted && !inst.operands[1].postind
12549 && !inst.operands[1].negative && inst.operands[0].reg <= 7
12551 && inst.size_req != 4)
12554 Rn = inst.operands[1].reg;
12555 if (inst.operands[1].immisreg)
12557 inst.instruction = THUMB_OP16 (opcode);
12559 if (Rn <= 7 && inst.operands[1].imm <= 7)
12562 reject_bad_reg (inst.operands[1].imm);
12574 if (inst.relocs[0].pc_rel)
12586 inst.instruction = inst.operands[0].reg << 8;
12590 inst.instruction = inst.operands[0].reg;
12591 inst.instruction |= inst.operands[1].reg << 3;
12593 inst.instruction |= THUMB_OP16 (opcode);
12594 if (inst.size_req == 2)
12595 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
12597 inst.relax = opcode;
12605 && inst.operands[0].reg == REG_SP
12606 && inst.operands[1].writeback == 1
12607 && !inst.operands[1].immisreg)
12619 if (inst.operands[1].immisreg)
12620 reject_bad_reg (inst.operands[1].imm);
12622 constraint (inst.operands[1].writeback == 1
12623 && inst.operands[0].reg == inst.operands[1].reg,
12626 inst.instruction = THUMB_OP32 (opcode);
12627 inst.instruction |= inst.operands[0].reg << 12;
12633 constraint (inst.operands[0].reg > 7, BAD_HIREG);
12635 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
12638 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
12639 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
12640 || inst.operands[1].postind || inst.operands[1].shifted
12641 || inst.operands[1].negative,
12643 inst.instruction = THUMB_OP16 (inst.instruction);
12647 inst.instruction = THUMB_OP16 (inst.instruction);
12648 if (!inst.operands[1].isreg)
12652 constraint (!inst.operands[1].preind
12653 || inst.operands[1].shifted
12654 || inst.operands[1].writeback,
12656 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
12658 constraint (inst.instruction & 0x0600,
12660 constraint (inst.operands[1].reg == REG_PC
12661 && !(inst.instruction & THUMB_LOAD_BIT),
12663 constraint (inst.operands[1].immisreg,
12666 if (inst.operands[1].reg == REG_PC)
12667 inst.instruction = T_OPCODE_LDR_PC;
12668 else if (inst.instruction & THUMB_LOAD_BIT)
12669 inst.instruction = T_OPCODE_LDR_SP;
12671 inst.instruction = T_OPCODE_STR_SP;
12673 inst.instruction |= inst.operands[0].reg << 8;
12674 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
12678 constraint (inst.operands[1].reg > 7, BAD_HIREG);
12679 if (!inst.operands[1].immisreg)
12682 inst.instruction |= inst.operands[0].reg;
12683 inst.instruction |= inst.operands[1].reg << 3;
12684 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
12689 constraint (inst.operands[1].imm > 7, BAD_HIREG);
12690 constraint (inst.operands[1].negative,
12694 switch (inst.instruction)
12696 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
12697 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
12698 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
12699 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
12700 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
12701 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
12707 inst.instruction |= inst.operands[0].reg;
12708 inst.instruction |= inst.operands[1].reg << 3;
12709 inst.instruction |= inst.operands[1].imm << 6;
12715 if (!inst.operands[1].present)
12717 inst.operands[1].reg = inst.operands[0].reg + 1;
12718 constraint (inst.operands[0].reg == REG_LR,
12720 constraint (inst.operands[0].reg == REG_R12,
12724 if (inst.operands[2].writeback
12725 && (inst.operands[0].reg == inst.operands[2].reg
12726 || inst.operands[1].reg == inst.operands[2].reg))
12730 inst.instruction |= inst.operands[0].reg << 12;
12731 inst.instruction |= inst.operands[1].reg << 8;
12738 inst.instruction |= inst.operands[0].reg << 12;
12747 Rd = inst.operands[0].reg;
12748 Rn = inst.operands[1].reg;
12749 Rm = inst.operands[2].reg;
12750 Ra = inst.operands[3].reg;
12757 inst.instruction |= Rd << 8;
12758 inst.instruction |= Rn << 16;
12759 inst.instruction |= Rm;
12760 inst.instruction |= Ra << 12;
12768 RdLo = inst.operands[0].reg;
12769 RdHi = inst.operands[1].reg;
12770 Rn = inst.operands[2].reg;
12771 Rm = inst.operands[3].reg;
12778 inst.instruction |= RdLo << 12;
12779 inst.instruction |= RdHi << 8;
12780 inst.instruction |= Rn << 16;
12781 inst.instruction |= Rm;
12789 Rn = inst.operands[0].reg;
12790 Rm = inst.operands[1].reg;
12797 int r0off = (inst.instruction == T_MNEM_mov
12798 || inst.instruction == T_MNEM_movs) ? 8 : 16;
12804 opcode = inst.instruction;
12809 if (inst.size_req == 4
12810 || inst.operands[1].shifted)
12814 if (opcode == T_MNEM_movs && inst.operands[1].isreg
12815 && !inst.operands[1].shifted
12819 inst.instruction = T2_SUBS_PC_LR;
12842 if (inst.operands[1].isreg)
12873 if (!inst.operands[1].isreg)
12880 inst.instruction = THUMB_OP16 (opcode);
12881 inst.instruction |= Rn << 8;
12882 if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12883 || inst.relocs[0].type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
12885 if (inst.size_req == 2)
12886 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
12888 inst.relax = opcode;
12893 constraint ((inst.relocs[0].type
12895 && (inst.relocs[0].type
12899 inst.instruction = THUMB_OP32 (inst.instruction);
12900 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12901 inst.instruction |= Rn << r0off;
12902 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
12905 else if (inst.operands[1].shifted && inst.operands[1].immisreg
12906 && (inst.instruction == T_MNEM_mov
12907 || inst.instruction == T_MNEM_movs))
12910 bool flags = (inst.instruction == T_MNEM_movs);
12917 if (inst.size_req == 4)
12920 if (!low_regs || inst.operands[1].imm > 7)
12926 switch (inst.operands[1].shift_kind)
12944 inst.instruction = opcode;
12947 inst.instruction |= Rn;
12948 inst.instruction |= inst.operands[1].imm << 3;
12953 inst.instruction |= CONDS_BIT;
12955 inst.instruction |= Rn << 8;
12956 inst.instruction |= Rm << 16;
12957 inst.instruction |= inst.operands[1].imm;
12964 if (low_regs && inst.operands[1].shifted
12965 && (inst.instruction == T_MNEM_mov
12966 || inst.instruction == T_MNEM_movs))
12969 narrow = (inst.instruction == T_MNEM_mov);
12971 narrow = (inst.instruction == T_MNEM_movs);
12976 switch (inst.operands[1].shift_kind)
12978 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
12979 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
12980 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
12987 inst.instruction |= Rn;
12988 inst.instruction |= Rm << 3;
12989 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
12993 inst.instruction = THUMB_OP32 (inst.instruction);
12994 inst.instruction |= Rn << r0off;
12999 switch (inst.instruction)
13013 inst.instruction = T_OPCODE_MOV_HR;
13014 inst.instruction |= (Rn & 0x8) << 4;
13015 inst.instruction |= (Rn & 0x7);
13016 inst.instruction |= Rm << 3;
13022 inst.instruction = T_OPCODE_LSL_I;
13023 inst.instruction |= Rn;
13024 inst.instruction |= Rm << 3;
13030 inst.instruction = T_OPCODE_CMP_LR;
13031 inst.instruction |= Rn;
13032 inst.instruction |= Rm << 3;
13036 inst.instruction = T_OPCODE_CMP_HR;
13037 inst.instruction |= (Rn & 0x8) << 4;
13038 inst.instruction |= (Rn & 0x7);
13039 inst.instruction |= Rm << 3;
13046 inst.instruction = THUMB_OP16 (inst.instruction);
13049 constraint (inst.operands[1].shifted,
13052 if (inst.operands[1].isreg)
13058 if (inst.instruction == T_OPCODE_MOV_I8)
13059 inst.instruction = T_OPCODE_ADD_I3;
13061 inst.instruction = T_OPCODE_CMP_LR;
13063 inst.instruction |= Rn;
13064 inst.instruction |= Rm << 3;
13068 if (inst.instruction == T_OPCODE_MOV_I8)
13069 inst.instruction = T_OPCODE_MOV_HR;
13071 inst.instruction = T_OPCODE_CMP_HR;
13079 inst.instruction |= Rn << 8;
13080 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
13091 top = (inst.instruction & 0x00800000) != 0;
13092 if (inst.relocs[0].type == BFD_RELOC_ARM_MOVW)
13095 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVW;
13097 else if (inst.relocs[0].type == BFD_RELOC_ARM_MOVT)
13100 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVT;
13103 Rd = inst.operands[0].reg;
13106 inst.instruction |= Rd << 8;
13107 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
13109 imm = inst.relocs[0].exp.X_add_number;
13110 inst.instruction |= (imm & 0xf000) << 4;
13111 inst.instruction |= (imm & 0x0800) << 15;
13112 inst.instruction |= (imm & 0x0700) << 4;
13113 inst.instruction |= (imm & 0x00ff);
13122 Rn = inst.operands[0].reg;
13123 Rm = inst.operands[1].reg;
13125 if (inst.instruction == T_MNEM_cmp
13126 || inst.instruction == T_MNEM_cmn)
13134 int r0off = (inst.instruction == T_MNEM_mvn
13135 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
13138 if (inst.size_req == 4
13139 || inst.instruction > 0xffff
13140 || inst.operands[1].shifted
13143 else if (inst.instruction == T_MNEM_cmn
13144 || inst.instruction == T_MNEM_tst)
13146 else if (THUMB_SETS_FLAGS (inst.instruction))
13151 if (!inst.operands[1].isreg)
13155 if (inst.instruction < 0xffff)
13156 inst.instruction = THUMB_OP32 (inst.instruction);
13157 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
13158 inst.instruction |= Rn << r0off;
13159 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
13166 inst.instruction = THUMB_OP16 (inst.instruction);
13167 inst.instruction |= Rn;
13168 inst.instruction |= Rm << 3;
13172 constraint (inst.operands[1].shifted
13173 && inst.operands[1].immisreg,
13175 if (inst.instruction < 0xffff)
13176 inst.instruction = THUMB_OP32 (inst.instruction);
13177 inst.instruction |= Rn << r0off;
13184 constraint (inst.instruction > 0xffff
13185 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
13186 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
13191 inst.instruction = THUMB_OP16 (inst.instruction);
13192 inst.instruction |= Rn;
13193 inst.instruction |= Rm << 3;
13205 Rd = inst.operands[0].reg;
13207 inst.instruction |= Rd << 8;
13209 if (inst.operands[1].isreg)
13211 unsigned br = inst.operands[1].reg;
13215 inst.instruction |= br & (0xf << 16);
13216 inst.instruction |= (br & 0x300) >> 4;
13217 inst.instruction |= (br & SPSR_BIT) >> 2;
13221 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
13239 inst.instruction |= (flags & SPSR_BIT) >> 2;
13240 inst.instruction |= inst.operands[1].imm & 0xff;
13241 inst.instruction |= 0xf0000;
13254 constraint (!inst.operands[1].isreg,
13257 if (inst.operands[0].isreg)
13258 flags = (int)(inst.operands[0].reg);
13260 flags = inst.operands[0].imm;
13264 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
13282 Rn = inst.operands[1].reg;
13285 inst.instruction |= (flags & SPSR_BIT) >> 2;
13286 inst.instruction |= (flags & 0xf0000) >> 8;
13287 inst.instruction |= (flags & 0x300) >> 4;
13288 inst.instruction |= (flags & 0xff);
13289 inst.instruction |= Rn << 16;
13298 if (!inst.operands[2].present)
13299 inst.operands[2].reg = inst.operands[0].reg;
13301 Rd = inst.operands[0].reg;
13302 Rn = inst.operands[1].reg;
13303 Rm = inst.operands[2].reg;
13307 if (inst.size_req == 4
13313 else if (inst.instruction == T_MNEM_muls)
13320 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
13329 inst.instruction = THUMB_OP16 (inst.instruction);
13330 inst.instruction |= Rd;
13333 inst.instruction |= Rm << 3;
13335 inst.instruction |= Rn << 3;
13341 constraint (inst.instruction != T_MNEM_mul,
13344 inst.instruction = THUMB_OP32 (inst.instruction);
13345 inst.instruction |= Rd << 8;
13346 inst.instruction |= Rn << 16;
13347 inst.instruction |= Rm << 0;
13360 RdLo = inst.operands[0].reg;
13361 RdHi = inst.operands[1].reg;
13362 Rn = inst.operands[2].reg;
13363 Rm = inst.operands[3].reg;
13370 inst.instruction |= RdLo << 12;
13371 inst.instruction |= RdHi << 8;
13372 inst.instruction |= Rn << 16;
13373 inst.instruction |= Rm;
13386 if (inst.size_req == 4 || inst.operands[0].imm > 15)
13388 inst.instruction = THUMB_OP32 (inst.instruction);
13389 inst.instruction |= inst.operands[0].imm;
13397 inst.instruction = THUMB_OP16 (inst.instruction);
13398 inst.instruction |= inst.operands[0].imm << 4;
13401 inst.instruction = 0x46c0;
13406 constraint (inst.operands[0].present,
13408 inst.instruction = 0x46c0;
13419 if (THUMB_SETS_FLAGS (inst.instruction))
13423 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
13425 if (inst.size_req == 4)
13430 inst.instruction = THUMB_OP32 (inst.instruction);
13431 inst.instruction |= inst.operands[0].reg << 8;
13432 inst.instruction |= inst.operands[1].reg << 16;
13436 inst.instruction = THUMB_OP16 (inst.instruction);
13437 inst.instruction |= inst.operands[0].reg;
13438 inst.instruction |= inst.operands[1].reg << 3;
13443 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
13445 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
13447 inst.instruction = THUMB_OP16 (inst.instruction);
13448 inst.instruction |= inst.operands[0].reg;
13449 inst.instruction |= inst.operands[1].reg << 3;
13458 Rd = inst.operands[0].reg;
13459 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
13465 inst.instruction |= Rd << 8;
13466 inst.instruction |= Rn << 16;
13468 if (!inst.operands[2].isreg)
13470 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
13471 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
13477 Rm = inst.operands[2].reg;
13480 constraint (inst.operands[2].shifted
13481 && inst.operands[2].immisreg,
13492 Rd = inst.operands[0].reg;
13493 Rn = inst.operands[1].reg;
13494 Rm = inst.operands[2].reg;
13500 inst.instruction |= Rd << 8;
13501 inst.instruction |= Rn << 16;
13502 inst.instruction |= Rm;
13503 inst.operands[3].present)
13505 unsigned int val = inst.relocs[0].exp.X_add_number;
13506 constraint (inst.relocs[0].exp.X_op != O_constant,
13508 inst.instruction |= (val & 0x1c) << 10;
13509 inst.instruction |= (val & 0x03) << 6;
13516 if (!inst.operands[3].present)
13520 inst.instruction &= ~0x00000020;
13523 Rtmp = inst.operands[1].reg;
13524 inst.operands[1].reg = inst.operands[2].reg;
13525 inst.operands[2].reg = Rtmp;
13533 if (inst.operands[0].immisreg)
13534 reject_bad_reg (inst.operands[0].imm);
13544 constraint (inst.operands[0].writeback,
13546 constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
13549 mask = inst.operands[0].imm;
13550 if (inst.size_req != 4 && (mask & ~0xff) == 0)
13551 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
13552 else if (inst.size_req != 4
13553 && (mask & ~0xff) == (1U << (inst.instruction == T_MNEM_push
13556 inst.instruction = THUMB_OP16 (inst.instruction);
13557 inst.instruction |= THUMB_PP_PC_LR;
13558 inst.instruction |= mask & 0xff;
13562 inst.instruction = THUMB_OP32 (inst.instruction);
13567 inst.error = _("invalid register list to push/pop instruction");
13576 encode_thumb2_multi (false /* do_io */, -1, inst.operands[0].imm, false);
13579 inst.error = _("invalid register list to push/pop instruction");
13587 if (inst.operands[0].issingle)
13589 inst.instruction |= (inst.operands[0].reg & 0x1) << 22;
13590 inst.instruction |= (inst.operands[0].reg & 0x1e) << 11;
13591 inst.instruction |= inst.operands[0].imm;
13595 inst.instruction |= (inst.operands[0].reg & 0x10) << 18;
13596 inst.instruction |= (inst.operands[0].reg & 0xf) << 12;
13597 inst.instruction |= 1 << 8;
13598 inst.instruction |= inst.operands[0].imm << 1;
13607 Rd = inst.operands[0].reg;
13608 Rm = inst.operands[1].reg;
13613 inst.instruction |= Rd << 8;
13614 inst.instruction |= Rm << 16;
13615 inst.instruction |= Rm;
13623 Rd = inst.operands[0].reg;
13624 Rm = inst.operands[1].reg;
13630 && inst.size_req != 4)
13632 inst.instruction = THUMB_OP16 (inst.instruction);
13633 inst.instruction |= Rd;
13634 inst.instruction |= Rm << 3;
13638 inst.instruction = THUMB_OP32 (inst.instruction);
13639 inst.instruction |= Rd << 8;
13640 inst.instruction |= Rm << 16;
13641 inst.instruction |= Rm;
13644 inst.error = BAD_HIREG;
13652 Rd = inst.operands[0].reg;
13653 Rm = inst.operands[1].reg;
13658 inst.instruction |= Rd << 8;
13659 inst.instruction |= Rm;
13667 Rd = inst.operands[0].reg;
13668 Rs = (inst.operands[1].present
13669 ? inst.operands[1].reg /* Rd, Rs, foo */
13670 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
13674 if (inst.operands[2].isreg)
13675 reject_bad_reg (inst.operands[2].reg);
13677 inst.instruction |= Rd << 8;
13678 inst.instruction |= Rs << 16;
13679 if (!inst.operands[2].isreg)
13683 if ((inst.instruction & 0x00100000) != 0)
13691 if (inst.size_req == 4 || !unified_syntax)
13694 if (inst.relocs[0].exp.X_op != O_constant
13695 || inst.relocs[0].exp.X_add_number != 0)
13702 inst.relocs[0].type = BFD_RELOC_UNUSED;
13703 inst.instruction = THUMB_OP16 (T_MNEM_negs);
13704 inst.instruction |= Rs << 3;
13705 inst.instruction |= Rd;
13709 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
13710 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
13725 if (inst.operands[0].imm)
13726 inst.instruction |= 0x8;
13732 if (!inst.operands[1].present)
13733 inst.operands[1].reg = inst.operands[0].reg;
13740 switch (inst.instruction)
13753 if (THUMB_SETS_FLAGS (inst.instruction))
13757 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
13759 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
13761 if (inst.operands[2].isreg
13762 && (inst.operands[1].reg != inst.operands[0].reg
13763 || inst.operands[2].reg > 7))
13765 if (inst.size_req == 4)
13768 reject_bad_reg (inst.operands[0].reg);
13769 reject_bad_reg (inst.operands[1].reg);
13773 if (inst.operands[2].isreg)
13775 reject_bad_reg (inst.operands[2].reg);
13776 inst.instruction = THUMB_OP32 (inst.instruction);
13777 inst.instruction |= inst.operands[0].reg << 8;
13778 inst.instruction |= inst.operands[1].reg << 16;
13779 inst.instruction |= inst.operands[2].reg;
13782 constraint (inst.operands[2].shifted,
13787 inst.operands[1].shifted = 1;
13788 inst.operands[1].shift_kind = shift_kind;
13789 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
13791 inst.instruction |= inst.operands[0].reg << 8;
13794 inst.relocs[0].type = BFD_RELOC_UNUSED;
13799 if (inst.operands[2].isreg)
13803 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
13804 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
13805 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
13806 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
13810 inst.instruction |= inst.operands[0].reg;
13811 inst.instruction |= inst.operands[2].reg << 3;
13814 constraint (inst.operands[2].shifted,
13821 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
13822 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
13823 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
13826 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
13827 inst.instruction |= inst.operands[0].reg;
13828 inst.instruction |= inst.operands[1].reg << 3;
13834 constraint (inst.operands[0].reg > 7
13835 || inst.operands[1].reg > 7, BAD_HIREG);
13836 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
13838 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
13840 constraint (inst.operands[2].reg > 7, BAD_HIREG);
13841 constraint (inst.operands[0].reg != inst.operands[1].reg,
13844 switch (inst.instruction)
13846 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
13847 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
13848 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
13849 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
13853 inst.instruction |= inst.operands[0].reg;
13854 inst.instruction |= inst.operands[2].reg << 3;
13857 constraint (inst.operands[2].shifted,
13862 switch (inst.instruction)
13864 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
13865 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
13866 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
13867 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
13870 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
13871 inst.instruction |= inst.operands[0].reg;
13872 inst.instruction |= inst.operands[1].reg << 3;
13882 Rd = inst.operands[0].reg;
13883 Rn = inst.operands[1].reg;
13884 Rm = inst.operands[2].reg;
13890 inst.instruction |= Rd << 8;
13891 inst.instruction |= Rn << 16;
13892 inst.instruction |= Rm;
13900 Rd = inst.operands[0].reg;
13901 Rm = inst.operands[1].reg;
13902 Rn = inst.operands[2].reg;
13908 inst.instruction |= Rd << 8;
13909 inst.instruction |= Rn << 16;
13910 inst.instruction |= Rm;
13916 unsigned int value = inst.relocs[0].exp.X_add_number;
13919 constraint (inst.relocs[0].exp.X_op != O_constant,
13923 inst.relocs[0].type = BFD_RELOC_UNUSED;
13924 inst.instruction |= (value & 0x000f) << 16;
13933 unsigned int value = inst.relocs[0].exp.X_add_number;
13935 inst.relocs[0].type = BFD_RELOC_UNUSED;
13936 inst.instruction |= (value & 0x0fff);
13937 inst.instruction |= (value & 0xf000) << 4;
13945 Rd = inst.operands[0].reg;
13946 Rn = inst.operands[2].reg;
13951 inst.instruction |= Rd << 8;
13952 inst.instruction |= inst.operands[1].imm - bias;
13953 inst.instruction |= Rn << 16;
13955 if (inst.operands[3].present)
13957 offsetT shift_amount = inst.relocs[0].exp.X_add_number;
13959 inst.relocs[0].type = BFD_RELOC_UNUSED;
13961 constraint (inst.relocs[0].exp.X_op != O_constant,
13969 if (inst.operands[3].shift_kind == SHIFT_ASR)
13970 inst.instruction |= 0x00200000; /* sh bit. */
13972 inst.instruction |= (shift_amount & 0x1c) << 10;
13973 inst.instruction |= (shift_amount & 0x03) << 6;
13989 Rd = inst.operands[0].reg;
13990 Rn = inst.operands[2].reg;
13995 inst.instruction |= Rd << 8;
13996 inst.instruction |= inst.operands[1].imm - 1;
13997 inst.instruction |= Rn << 16;
14003 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
14004 || inst.operands[2].postind || inst.operands[2].writeback
14005 || inst.operands[2].immisreg || inst.operands[2].shifted
14006 || inst.operands[2].negative,
14009 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
14011 inst.instruction |= inst.operands[0].reg << 8;
14012 inst.instruction |= inst.operands[1].reg << 12;
14013 inst.instruction |= inst.operands[2].reg << 16;
14014 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
14020 if (!inst.operands[2].present)
14021 inst.operands[2].reg = inst.operands[1].reg + 1;
14023 constraint (inst.operands[0].reg == inst.operands[1].reg
14024 || inst.operands[0].reg == inst.operands[2].reg
14025 || inst.operands[0].reg == inst.operands[3].reg,
14028 inst.instruction |= inst.operands[0].reg;
14029 inst.instruction |= inst.operands[1].reg << 12;
14030 inst.instruction |= inst.operands[2].reg << 8;
14031 inst.instruction |= inst.operands[3].reg << 16;
14039 Rd = inst.operands[0].reg;
14040 Rn = inst.operands[1].reg;
14041 Rm = inst.operands[2].reg;
14047 inst.instruction |= Rd << 8;
14048 inst.instruction |= Rn << 16;
14049 inst.instruction |= Rm;
14050 inst.instruction |= inst.operands[3].imm << 4;
14058 Rd = inst.operands[0].reg;
14059 Rm = inst.operands[1].reg;
14064 if (inst.instruction <= 0xffff
14065 && inst.size_req != 4
14067 && (!inst.operands[2].present || inst.operands[2].imm == 0))
14069 inst.instruction = THUMB_OP16 (inst.instruction);
14070 inst.instruction |= Rd;
14071 inst.instruction |= Rm << 3;
14075 if (inst.instruction <= 0xffff)
14076 inst.instruction = THUMB_OP32 (inst.instruction);
14077 inst.instruction |= Rd << 8;
14078 inst.instruction |= Rm;
14079 inst.instruction |= inst.operands[2].imm << 4;
14083 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
14092 inst.relocs[0].type = BFD_RELOC_ARM_SWI;
14101 half = (inst.instruction & 0x10) != 0;
14103 constraint (inst.operands[0].immisreg,
14106 Rn = inst.operands[0].reg;
14107 Rm = inst.operands[0].imm;
14113 constraint (!half && inst.operands[0].shifted,
14115 inst.instruction |= (Rn << 16) | Rm;
14121 if (!inst.operands[0].present)
14122 inst.operands[0].imm = 0;
14124 if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4)
14126 constraint (inst.size_req == 2,
14128 inst.instruction = THUMB_OP32 (inst.instruction);
14129 inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4;
14130 inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0;
14134 inst.instruction = THUMB_OP16 (inst.instruction);
14135 inst.instruction |= inst.operands[0].imm;
14153 Rd = inst.operands[0].reg;
14154 Rn = inst.operands[2].reg;
14159 inst.instruction |= Rd << 8;
14160 inst.instruction |= inst.operands[1].imm;
14161 inst.instruction |= Rn << 16;
14188 unsigned long insn = inst.instruction;
14190 inst.instruction = THUMB_OP32 (inst.instruction);
14191 if (inst.operands[0].hasreloc == 0)
14193 if (v8_1_branch_value_check (inst.operands[0].imm, 5, false) == FAIL)
14196 inst.instruction |= ((inst.operands[0].imm & 0x1f) >> 1) << 23;
14200 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH5;
14201 inst.relocs[0].pc_rel = 1;
14207 if (inst.operands[1].hasreloc == 0)
14209 int val = inst.operands[1].imm;
14210 if (v8_1_branch_value_check (inst.operands[1].imm, 17, true) == FAIL)
14216 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14220 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF17;
14221 inst.relocs[1].pc_rel = 1;
14226 if (inst.operands[1].hasreloc == 0)
14228 int val = inst.operands[1].imm;
14229 if (v8_1_branch_value_check (inst.operands[1].imm, 19, true) == FAIL)
14235 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14239 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF19;
14240 inst.relocs[1].pc_rel = 1;
14246 if (inst.operands[1].hasreloc == 0)
14248 int val = inst.operands[1].imm;
14252 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14256 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF13;
14257 inst.relocs[1].pc_rel = 1;
14261 if (inst.operands[2].hasreloc == 0)
14263 constraint ((inst.operands[0].hasreloc != 0), BAD_ARGS);
14264 int val2 = inst.operands[2].imm;
14265 int val0 = inst.operands[0].imm & 0x1f;
14268 inst.instruction |= 1 << 17; /* T bit. */
14274 constraint ((inst.operands[0].hasreloc == 0), BAD_ARGS);
14275 inst.relocs[2].type = BFD_RELOC_THUMB_PCREL_BFCSEL;
14276 inst.relocs[2].pc_rel = 1;
14280 constraint (inst.cond != COND_ALWAYS, BAD_COND);
14281 inst.instruction |= (inst.operands[3].imm & 0xf) << 18;
14286 inst.instruction |= inst.operands[1].reg << 16;
14297 if (inst.relocs[0].exp.X_op == O_constant)
14299 int value = inst.relocs[0].exp.X_add_number;
14310 inst.instruction |= (imml << 11) | (immh << 1);
14314 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_LOOP12;
14315 inst.relocs[0].pc_rel = 1;
14323 unsigned int value = inst.operands[2].imm;
14325 inst.instruction |= inst.operands[0].reg << 16;
14326 inst.instruction |= inst.operands[1].reg << 8;
14329 inst.instruction |= ((value == 64) ? 0: 1) << 7;
14332 constraint (inst.operands[3].reg == inst.operands[0].reg, BAD_OVERLAP);
14333 constraint (inst.operands[3].reg == inst.operands[1].reg, BAD_OVERLAP);
14334 inst.instruction |= inst.operands[3].reg << 12;
14341 if (!inst.operands[2].present)
14343 inst.operands[2] = inst.operands[1];
14344 inst.operands[1].reg = 0xf;
14347 inst.instruction |= inst.operands[0].reg << 16;
14348 inst.instruction |= inst.operands[1].reg << 8;
14350 if (inst.operands[2].isreg)
14353 constraint (inst.operands[2].reg == inst.operands[0].reg, BAD_OVERLAP);
14354 constraint (inst.operands[2].reg == inst.operands[1].reg, BAD_OVERLAP);
14355 inst.instruction |= inst.operands[2].reg << 12;
14360 unsigned int value = inst.operands[2].imm;
14361 inst.instruction |= (value & 0x1c) << 10;
14362 inst.instruction |= (value & 0x03) << 6;
14364 inst.instruction |= 0x2;
14581 #define NEON_ENCODE(type, inst) \
14584 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14585 inst.is_neon = 1; \
14592 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14866 if (!inst.operands[1].present)
14867 inst.operands[1] = inst.operands[0];
14878 if (!inst.operands[j].present)
14891 information is stored in inst.vectype. If the type specifier
14893 in inst.operands[].vectype.
14912 if (!(inst.operands[j].isreg
14913 && inst.operands[j].isvec
14914 && inst.operands[j].issingle
14915 && !inst.operands[j].isquad
14916 && ((inst.vectype.elems == 1
14917 && inst.vectype.el[0].size == 16)
14918 || (inst.vectype.elems > 1
14919 && inst.vectype.el[j].size == 16)
14920 || (inst.vectype.elems == 0
14921 && inst.operands[j].vectype.type != NT_invtype
14922 && inst.operands[j].vectype.size == 16))))
14927 if (!(inst.operands[j].isreg
14928 && inst.operands[j].isvec
14929 && inst.operands[j].issingle
14930 && !inst.operands[j].isquad
14931 && ((inst.vectype.elems == 1 && inst.vectype.el[0].size == 32)
14932 || (inst.vectype.elems > 1 && inst.vectype.el[j].size == 32)
14933 || (inst.vectype.elems == 0
14934 && (inst.operands[j].vectype.size == 32
14935 || inst.operands[j].vectype.type == NT_invtype)))))
14940 if (!(inst.operands[j].isreg
14941 && inst.operands[j].isvec
14942 && !inst.operands[j].isquad
14943 && !inst.operands[j].issingle))
14948 if (!(inst.operands[j].isreg
14949 && !inst.operands[j].isvec))
14954 if (!(inst.operands[j].isreg
14955 && inst.operands[j].isvec
14956 && inst.operands[j].isquad
14957 && !inst.operands[j].issingle))
14962 if (!(!inst.operands[j].isreg
14963 && !inst.operands[j].isscalar))
14968 if (!(!inst.operands[j].isreg
14969 && inst.operands[j].isscalar))
14980 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
15218 if (els > 1 && !inst.operands[1].present)
15219 inst.operands[1] = inst.operands[0];
15237 if (inst.vectype.elems > 0)
15239 if (inst.operands[i].vectype.type != NT_invtype)
15245 /* Duplicate inst.vectype elements here as necessary.
15249 if (inst.vectype.elems == 1 && els > 1)
15252 inst.vectype.elems = els;
15253 inst.vectype.el[key_el] = inst.vectype.el[0];
15256 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
15259 else if (inst.vectype.elems == 0 && els > 0)
15266 if (inst.operands[j].vectype.type != NT_invtype)
15267 inst.vectype.el[j] = inst.operands[j].vectype;
15269 if (inst.operands[key_el].vectype.type != NT_invtype)
15272 if (inst.operands[j].vectype.type == NT_invtype)
15273 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
15282 else if (inst.vectype.elems != els)
15295 enum neon_el_type g_type = inst.vectype.el[i].type;
15296 unsigned g_size = inst.vectype.el[i].size;
15327 inst.error = _(BAD_FP16);
15363 inst.error = _(BAD_FP16);
15400 return inst.vectype.el[key_el];
15410 inst.is_neon = 1;
15413 inst.instruction |= 0xe0000000;
15415 inst.instruction |= inst.cond << 28;
15440 inst.is_neon = 1;
15444 inst.instruction = opcode->tvalue;
15449 inst.instruction = (inst.cond << 28) | opcode->avalue;
15457 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
15511 inst.error = NULL;
15518 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
15543 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
15583 int is_neg = (inst.instruction & 0x80) != 0;
15612 int is_ldm = (inst.instruction & (1 << 20)) != 0;
15675 NEON_ENCODE (SINGLE, inst);
15684 NEON_ENCODE (DOUBLE, inst);
15714 switch (inst.operands[0].imm)
15740 if (inst.operands[0].imm > 1)
15745 return inst.operands[0].imm;
15747 if (inst.operands[0].imm == 0x2)
15749 else if (inst.operands[0].imm == 0x8)
15757 switch (inst.operands[0].imm)
15787 if (inst.cond > COND_ALWAYS)
15788 inst.pred_insn_type = INSIDE_VPT_INSN;
15790 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15793 32 and 64. For instructions with no type, inst.vectype.el[j].type is set
15794 to NT_untyped and size is updated in inst.vectype.el[j].size. */
15795 if ((inst.operands[0].present) && (inst.vectype.el[0].type == NT_untyped))
15796 dt = inst.vectype.el[0].size;
15800 inst.is_neon = 1;
15815 inst.instruction |= size << 20;
15816 inst.instruction |= inst.operands[0].reg << 16;
15823 if (inst.operands[0].present)
15832 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
15842 inst.instruction |= (et.size == 16) << 28;
15843 inst.instruction |= 0x3 << 20;
15849 inst.instruction |= 1 << 28;
15850 inst.instruction |= neon_logbits (et.size) << 20;
15853 if (inst.operands[2].isquad)
15855 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15856 inst.instruction |= LOW4 (inst.operands[2].reg);
15857 inst.instruction |= (fcond & 0x2) >> 1;
15861 if (inst.operands[2].reg == REG_SP)
15863 inst.instruction |= 1 << 6;
15864 inst.instruction |= (fcond & 0x2) << 4;
15865 inst.instruction |= inst.operands[2].reg;
15867 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15868 inst.instruction |= (fcond & 0x4) << 10;
15869 inst.instruction |= (fcond & 0x1) << 7;
15874 now_pred.mask = ((inst.instruction & 0x00400000) >> 19)
15875 | ((inst.instruction & 0xe000) >> 13);
15878 inst.is_neon = 1;
15885 if (!inst.operands[1].isreg || !inst.operands[1].isquad)
15887 if (!inst.operands[2].present)
15889 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
15892 if ((inst.instruction & 0xffffffff) == N_MNEM_vcmpe
15893 && inst.operands[1].isquad)
15895 inst.instruction = N_MNEM_vcmp;
15896 inst.cond = 0x10;
15899 if (inst.cond > COND_ALWAYS)
15900 inst.pred_insn_type = INSIDE_VPT_INSN;
15902 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15909 constraint (rs == NS_IQR && inst.operands[2].reg == REG_PC
15910 && !inst.operands[2].iszr, BAD_PC);
15914 inst.instruction = 0xee010f00;
15915 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15916 inst.instruction |= (fcond & 0x4) << 10;
15917 inst.instruction |= (fcond & 0x1) << 7;
15922 inst.instruction |= (et.size == 16) << 28;
15923 inst.instruction |= 0x3 << 20;
15927 inst.instruction |= 1 << 28;
15928 inst.instruction |= neon_logbits (et.size) << 20;
15930 if (inst.operands[2].isquad)
15932 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15933 inst.instruction |= (fcond & 0x2) >> 1;
15934 inst.instruction |= LOW4 (inst.operands[2].reg);
15938 if (inst.operands[2].reg == REG_SP)
15940 inst.instruction |= 1 << 6;
15941 inst.instruction |= (fcond & 0x2) << 4;
15942 inst.instruction |= inst.operands[2].reg;
15945 inst.is_neon = 1;
15952 if (inst.cond > COND_ALWAYS)
15953 inst.pred_insn_type = INSIDE_VPT_INSN;
15955 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15961 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15962 inst.instruction |= neon_logbits (et.size) << 18;
15963 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15964 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15965 inst.instruction |= LOW4 (inst.operands[1].reg);
15966 inst.is_neon = 1;
15976 if (inst.cond > COND_ALWAYS)
15977 inst.pred_insn_type = INSIDE_VPT_INSN;
15979 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15981 if (inst.operands[2].reg == REG_SP)
15983 else if (inst.operands[2].reg == REG_PC)
15986 inst.instruction |= (et.size == 16) << 28;
15987 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15988 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15989 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15990 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15991 inst.instruction |= inst.operands[2].reg;
15992 inst.is_neon = 1;
15998 if (inst.cond > COND_ALWAYS)
15999 inst.pred_insn_type = INSIDE_VPT_INSN;
16001 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16003 unsigned imm = inst.relocs[0].exp.X_add_number;
16010 if (inst.instruction == M_MNEM_vddup || inst.instruction == M_MNEM_vidup)
16018 constraint ((inst.operands[2].reg % 2) != 1, BAD_EVEN);
16019 if (inst.operands[2].reg == REG_SP)
16021 else if (inst.operands[2].reg == REG_PC)
16026 Rm = inst.operands[2].reg >> 1;
16028 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16029 inst.instruction |= neon_logbits (et.size) << 20;
16030 inst.instruction |= inst.operands[1].reg << 16;
16031 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16032 inst.instruction |= (imm > 2) << 7;
16033 inst.instruction |= Rm << 1;
16034 inst.instruction |= (imm == 2 || imm == 8);
16035 inst.is_neon = 1;
16045 if (inst.operands[2].reg == REG_PC)
16047 else if (inst.operands[2].reg == REG_SP)
16050 if (inst.cond > COND_ALWAYS)
16051 inst.pred_insn_type = INSIDE_VPT_INSN;
16053 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16055 inst.instruction |= (et.type == NT_unsigned) << 28;
16056 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16057 inst.instruction |= neon_logbits (et.size) << 20;
16058 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16059 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16060 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16061 inst.instruction |= inst.operands[2].reg;
16062 inst.is_neon = 1;
16071 if (inst.cond > COND_ALWAYS)
16072 inst.pred_insn_type = INSIDE_VPT_INSN;
16074 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16076 int imm = inst.operands[2].imm;
16082 inst.instruction |= neon_logbits (et.size) << 18;
16083 inst.instruction |= 0x110001;
16087 inst.instruction |= (et.size + imm) << 16;
16088 inst.instruction |= 0x800140;
16091 inst.instruction |= (et.type == NT_unsigned) << 28;
16092 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16093 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16094 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16095 inst.instruction |= LOW4 (inst.operands[1].reg);
16096 inst.is_neon = 1;
16102 if (inst.cond > COND_ALWAYS)
16103 inst.pred_insn_type = INSIDE_VPT_INSN;
16105 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16107 if (inst.operands[1].reg == REG_PC)
16109 else if (inst.operands[1].reg == REG_SP)
16112 int imm = inst.operands[2].imm;
16115 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16116 inst.instruction |= (imm & 0x1f) << 16;
16117 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16118 inst.instruction |= inst.operands[1].reg;
16119 inst.is_neon = 1;
16126 switch (inst.instruction)
16152 if (inst.cond > COND_ALWAYS)
16153 inst.pred_insn_type = INSIDE_VPT_INSN;
16155 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16157 unsigned Qd = inst.operands[0].reg;
16158 unsigned Qm = inst.operands[1].reg;
16159 unsigned imm = inst.operands[2].imm;
16165 inst.instruction |= (et.type == NT_unsigned) << 28;
16166 inst.instruction |= HI1 (Qd) << 22;
16167 inst.instruction |= (et.size - imm) << 16;
16168 inst.instruction |= LOW4 (Qd) << 12;
16169 inst.instruction |= HI1 (Qm) << 5;
16170 inst.instruction |= LOW4 (Qm);
16171 inst.is_neon = 1;
16178 if (inst.instruction == M_MNEM_vqmovnt
16179 || inst.instruction == M_MNEM_vqmovnb)
16185 if (inst.cond > COND_ALWAYS)
16186 inst.pred_insn_type = INSIDE_VPT_INSN;
16188 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16190 inst.instruction |= (et.type == NT_unsigned) << 28;
16191 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16192 inst.instruction |= (et.size == 32) << 18;
16193 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16194 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16195 inst.instruction |= LOW4 (inst.operands[1].reg);
16196 inst.is_neon = 1;
16204 if (inst.cond > COND_ALWAYS)
16205 inst.pred_insn_type = INSIDE_VPT_INSN;
16207 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16209 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16210 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16211 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16212 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16213 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16214 inst.instruction |= LOW4 (inst.operands[2].reg);
16215 inst.is_neon = 1;
16221 if (inst.cond > COND_ALWAYS)
16222 inst.pred_insn_type = INSIDE_VPT_INSN;
16224 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16234 if (inst.cond > COND_ALWAYS)
16235 inst.pred_insn_type = INSIDE_VPT_INSN;
16237 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16239 inst.instruction |= (et.size == 16) << 28;
16240 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16241 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16242 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16243 inst.instruction |= LOW4 (inst.operands[1].reg);
16244 inst.is_neon = 1;
16254 if (inst.cond > COND_ALWAYS)
16255 inst.pred_insn_type = INSIDE_VPT_INSN;
16257 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16259 unsigned rot = inst.relocs[0].exp.X_add_number;
16263 if (et.size == 32 && (inst.operands[0].reg == inst.operands[1].reg
16264 || inst.operands[0].reg == inst.operands[2].reg))
16267 inst.instruction |= (et.size == 32) << 28;
16268 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16269 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16270 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16271 inst.instruction |= (rot > 90) << 12;
16272 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16273 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16274 inst.instruction |= LOW4 (inst.operands[2].reg);
16275 inst.instruction |= (rot == 90 || rot == 270);
16276 inst.is_neon = 1;
16284 unsigned long insn = inst.instruction;
16286 inst.instruction = THUMB_OP32 (inst.instruction);
16297 inst.instruction |= neon_logbits (et.size) << 20;
16298 inst.is_neon = 1;
16304 constraint (!inst.operands[0].present,
16309 if (!inst.operands[0].present)
16310 inst.instruction |= 1 << 21;
16321 constraint (inst.operands[1].isreg != 1, BAD_ARGS);
16324 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
16325 else if (inst.operands[1].reg == REG_PC)
16327 if (inst.operands[1].reg == REG_SP)
16330 inst.instruction |= (inst.operands[1].reg << 16);
16343 if (!inst.operands[0].isreg)
16350 constraint (inst.operands[2].present, BAD_SYNTAX);
16355 if (inst.operands[1].isreg)
16362 NEON_ENCODE (SINGLE, inst);
16367 NEON_ENCODE (DOUBLE, inst);
16376 switch (inst.instruction & 0x0fffffff)
16379 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
16382 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
16390 NEON_ENCODE (SINGLE, inst);
16395 NEON_ENCODE (DOUBLE, inst);
16409 inst.operands[1] = inst.operands[0];
16410 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
16411 inst.operands[0].reg = REG_SP;
16412 inst.operands[0].isreg = 1;
16413 inst.operands[0].writeback = 1;
16414 inst.operands[0].present = 1;
16445 if (inst.operands[2].reg == REG_SP)
16447 else if (inst.operands[2].reg == REG_PC)
16453 if (((unsigned)inst.instruction) == 0xd00)
16454 inst.instruction = 0xee300f40;
16456 else if (((unsigned)inst.instruction) == 0x200d00)
16457 inst.instruction = 0xee301f40;
16459 else if (((unsigned)inst.instruction) == 0x1000d10)
16460 inst.instruction = 0xee310e60;
16463 inst.instruction |= (size == 16) << 28;
16468 if (((unsigned)inst.instruction) == 0x800)
16469 inst.instruction = 0xee010f40;
16471 else if (((unsigned)inst.instruction) == 0x1000800)
16472 inst.instruction = 0xee011f40;
16474 else if (((unsigned)inst.instruction) == 0)
16475 inst.instruction = 0xee000f40;
16477 else if (((unsigned)inst.instruction) == 0x200)
16478 inst.instruction = 0xee001f40;
16480 else if (((unsigned)inst.instruction) == 0x900)
16481 inst.instruction = 0xee010e40;
16483 else if (((unsigned)inst.instruction) == 0x910)
16484 inst.instruction = 0xee011e60;
16486 else if (((unsigned)inst.instruction) == 0x10)
16487 inst.instruction = 0xee000f60;
16489 else if (((unsigned)inst.instruction) == 0x210)
16490 inst.instruction = 0xee001f60;
16492 else if (((unsigned)inst.instruction) == 0x3000b10)
16493 inst.instruction = 0xee000e40;
16495 else if (((unsigned)inst.instruction) == 0x0000b00)
16496 inst.instruction = 0xee010e60;
16498 else if (((unsigned)inst.instruction) == 0x1000b00)
16499 inst.instruction = 0xfe010e60;
16502 inst.instruction |= U << 28;
16505 inst.instruction |= neon_logbits (size) << 20;
16507 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16508 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16509 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16510 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16511 inst.instruction |= inst.operands[2].reg;
16512 inst.is_neon = 1;
16518 inst.instruction |= bit28 << 28;
16519 inst.instruction |= neon_logbits (size) << 20;
16520 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16521 inst.instruction |= inst.operands[0].reg << 12;
16522 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16523 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16524 inst.instruction |= LOW4 (inst.operands[2].reg);
16525 inst.is_neon = 1;
16532 inst.instruction |= (ubit != 0) << 28;
16533 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16534 inst.instruction |= neon_logbits (size) << 20;
16535 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16536 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16537 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16538 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16539 inst.instruction |= LOW4 (inst.operands[2].reg);
16541 inst.is_neon = 1;
16547 inst.instruction |= bit28 << 28;
16548 inst.instruction |= neon_logbits (size) << 18;
16549 inst.instruction |= inst.operands[0].reg << 12;
16550 inst.instruction |= LOW4 (inst.operands[1].reg);
16551 inst.is_neon = 1;
16557 constraint (inst.operands[3].reg > 14, MVE_BAD_QREG);
16559 inst.instruction |= U << 28;
16560 inst.instruction |= (inst.operands[1].reg >> 1) << 20;
16561 inst.instruction |= LOW4 (inst.operands[2].reg) << 16;
16562 inst.instruction |= (size == 32) << 16;
16563 inst.instruction |= inst.operands[0].reg << 12;
16564 inst.instruction |= HI1 (inst.operands[2].reg) << 7;
16565 inst.instruction |= inst.operands[3].reg;
16566 inst.is_neon = 1;
16573 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16574 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16575 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16576 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16577 inst.instruction |= LOW4 (inst.operands[2].reg);
16578 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16579 inst.instruction |= (isquad != 0) << 6;
16580 inst.is_neon = 1;
16595 inst.instruction |= (ubit != 0) << 24;
16597 inst.instruction |= neon_logbits (size) << 20;
16599 neon_dp_fixup (&inst);
16612 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16613 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16614 inst.instruction |= LOW4 (inst.operands[1].reg);
16615 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16616 inst.instruction |= (qbit != 0) << 6;
16617 inst.instruction |= (ubit != 0) << 24;
16620 inst.instruction |= neon_logbits (size) << 18;
16622 neon_dp_fixup (&inst);
16647 changed to inst.uncond_value. This is necessary because instructions shared
16657 if (inst.cond != COND_ALWAYS)
16662 if (inst.uncond_value != -1u)
16663 inst.instruction |= inst.uncond_value << 28;
16687 if (inst.cond > COND_ALWAYS)
16691 inst.error = BAD_FPU;
16694 inst.pred_insn_type = INSIDE_VPT_INSN;
16696 else if (inst.cond < COND_ALWAYS)
16699 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16710 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16767 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16768 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16769 inst.instruction |= LOW4 (inst.operands[1].reg);
16770 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16771 inst.instruction |= (isquad != 0) << 6;
16772 inst.instruction |= immbits << 16;
16773 inst.instruction |= (size >> 3) << 7;
16774 inst.instruction |= (size & 0x7) << 19;
16776 inst.instruction |= (uval != 0) << 24;
16778 neon_dp_fixup (&inst);
16787 if (!inst.operands[2].isreg)
16801 int imm = inst.operands[2].imm;
16805 NEON_ENCODE (IMMED, inst);
16826 constraint (inst.operands[0].reg != inst.operands[1].reg,
16828 if (inst.operands[2].reg == REG_SP)
16830 else if (inst.operands[2].reg == REG_PC)
16833 inst.instruction = 0xee311e60;
16834 inst.instruction |= (et.type == NT_unsigned) << 28;
16835 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16836 inst.instruction |= neon_logbits (et.size) << 18;
16837 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16838 inst.instruction |= inst.operands[2].reg;
16839 inst.is_neon = 1;
16852 tmp = inst.operands[2].reg;
16853 inst.operands[2].reg = inst.operands[1].reg;
16854 inst.operands[1].reg = tmp;
16855 NEON_ENCODE (INTEGER, inst);
16867 if (!inst.operands[2].isreg)
16881 int imm = inst.operands[2].imm;
16885 NEON_ENCODE (IMMED, inst);
16906 constraint (inst.operands[0].reg != inst.operands[1].reg,
16908 if (inst.operands[2].reg == REG_SP)
16910 else if (inst.operands[2].reg == REG_PC)
16913 inst.instruction = 0xee311ee0;
16914 inst.instruction |= (et.type == NT_unsigned) << 28;
16915 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16916 inst.instruction |= neon_logbits (et.size) << 18;
16917 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16918 inst.instruction |= inst.operands[2].reg;
16919 inst.is_neon = 1;
16926 tmp = inst.operands[2].reg;
16927 inst.operands[2].reg = inst.operands[1].reg;
16928 inst.operands[1].reg = tmp;
16929 NEON_ENCODE (INTEGER, inst);
16958 if (inst.operands[2].reg == REG_PC)
16960 else if (inst.operands[2].reg == REG_SP)
16963 constraint (inst.operands[0].reg != inst.operands[1].reg,
16966 if (inst.instruction == 0x0000510)
16968 inst.instruction = 0xee331ee0;
16971 inst.instruction = 0xee331e60;
16973 inst.instruction |= (et.type == NT_unsigned) << 28;
16974 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16975 inst.instruction |= neon_logbits (et.size) << 18;
16976 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16977 inst.instruction |= inst.operands[2].reg;
16978 inst.is_neon = 1;
16982 tmp = inst.operands[2].reg;
16983 inst.operands[2].reg = inst.operands[1].reg;
16984 inst.operands[1].reg = tmp;
17048 if (inst.operands[2].present && inst.operands[2].isreg)
17061 NEON_ENCODE (INTEGER, inst);
17066 const int three_ops_form = (inst.operands[2].present
17067 && !inst.operands[2].isreg);
17091 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
17097 constraint (inst.operands[0].reg != inst.operands[1].reg,
17100 NEON_ENCODE (IMMED, inst);
17102 immbits = inst.operands[immoperand].imm;
17107 if (immbits != (inst.operands[immoperand].regisimm ?
17108 inst.operands[immoperand].reg : 0))
17144 inst.instruction |= neon_quad (rs) << 6;
17145 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17146 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17147 inst.instruction |= cmode << 8;
17150 neon_dp_fixup (&inst);
17171 NEON_ENCODE (FLOAT, inst);
17179 NEON_ENCODE (INTEGER, inst);
17209 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
17210 constraint (!inst.operands[1].preind, BAD_ADDR_MODE);
17211 constraint (load && inst.operands[0].reg == inst.operands[1].reg,
17215 int imm = inst.relocs[0].exp.X_add_number;
17228 inst.instruction |= 0x11 << 24;
17229 inst.instruction |= add << 23;
17230 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17231 inst.instruction |= inst.operands[1].writeback << 21;
17232 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17233 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17234 inst.instruction |= 1 << 12;
17235 inst.instruction |= (size == 64) << 8;
17236 inst.instruction &= 0xffffff00;
17237 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
17238 inst.instruction |= imm >> neon_logbits (size);
17244 unsigned os = inst.operands[1].imm >> 5;
17245 unsigned type = inst.vectype.el[0].type;
17251 if (inst.operands[1].reg == REG_PC)
17269 constraint (inst.operands[1].writeback || !inst.operands[1].preind,
17273 constraint (inst.operands[0].reg == (inst.operands[1].imm & 0x1f),
17279 inst.instruction |= ((size == elsize) || (type == NT_unsigned)) << 28;
17286 inst.instruction |= 1 << 23;
17287 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17288 inst.instruction |= inst.operands[1].reg << 16;
17289 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17290 inst.instruction |= neon_logbits (elsize) << 7;
17291 inst.instruction |= HI1 (inst.operands[1].imm) << 5;
17292 inst.instruction |= LOW4 (inst.operands[1].imm);
17293 inst.instruction |= !!os;
17299 enum neon_el_type type = inst.vectype.el[0].type;
17323 int imm = inst.relocs[0].exp.X_add_number;
17351 constraint (inst.operands[1].reg > 7, BAD_HIREG);
17352 constraint (inst.operands[0].reg > 14,
17354 inst.instruction |= (load && type == NT_unsigned) << 28;
17355 inst.instruction |= (size == 16) << 19;
17356 inst.instruction |= neon_logbits (elsize) << 7;
17360 if (inst.operands[1].reg == REG_PC)
17362 else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
17364 inst.instruction |= 1 << 12;
17365 inst.instruction |= neon_logbits (size) << 7;
17367 inst.instruction |= inst.operands[1].preind << 24;
17368 inst.instruction |= add << 23;
17369 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17370 inst.instruction |= inst.operands[1].writeback << 21;
17371 inst.instruction |= inst.operands[1].reg << 16;
17372 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17373 inst.instruction &= 0xffffff80;
17374 inst.instruction |= imm >> neon_logbits (size);
17384 if (inst.cond > COND_ALWAYS)
17385 inst.pred_insn_type = INSIDE_VPT_INSN;
17387 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17389 switch (inst.instruction)
17419 unsigned elsize = inst.vectype.el[0].size;
17421 if (inst.operands[1].isquad)
17428 if (inst.operands[1].immisreg == 2)
17433 else if (!inst.operands[1].immisreg)
17442 inst.is_neon = 1;
17451 constraint (!inst.operands[1].preind || inst.relocs[0].exp.X_add_symbol != 0
17452 || inst.relocs[0].exp.X_add_number != 0
17453 || inst.operands[1].immisreg != 0,
17455 constraint (inst.vectype.el[0].size > 32, BAD_EL_TYPE);
17456 if (inst.operands[1].reg == REG_PC)
17458 else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
17466 if (inst.cond > COND_ALWAYS)
17470 else if (inst.cond < COND_ALWAYS)
17471 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17473 inst.pred_insn_type = MVE_UNPREDICABLE_INSN;
17475 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17476 inst.instruction |= inst.operands[1].writeback << 21;
17477 inst.instruction |= inst.operands[1].reg << 16;
17478 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17479 inst.instruction |= neon_logbits (inst.vectype.el[0].size) << 7;
17480 inst.is_neon = 1;
17493 if (inst.cond > COND_ALWAYS)
17494 inst.pred_insn_type = INSIDE_VPT_INSN;
17496 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17498 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
17500 inst.instruction |= (et.type == NT_unsigned) << 28;
17501 inst.instruction |= inst.operands[1].reg << 19;
17502 inst.instruction |= inst.operands[0].reg << 12;
17503 inst.instruction |= inst.operands[2].reg;
17504 inst.is_neon = 1;
17514 constraint ((inst.instruction == ((unsigned) N_MNEM_vmax)
17515 || inst.instruction == ((unsigned) N_MNEM_vmin))
17573 if (inst.operands[1].present)
17575 void *scratch = xmalloc (sizeof (inst.operands[0]));
17578 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
17579 inst.operands[1] = inst.operands[2];
17580 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
17585 inst.operands[1] = inst.operands[2];
17586 inst.operands[2] = inst.operands[0];
17593 if (inst.operands[2].isreg)
17605 NEON_ENCODE (IMMED, inst);
17606 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17607 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17608 inst.instruction |= LOW4 (inst.operands[1].reg);
17609 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
17610 inst.instruction |= neon_quad (rs) << 6;
17611 inst.instruction |= (et.type == NT_float) << 10;
17612 inst.instruction |= neon_logbits (et.size) << 18;
17614 neon_dp_fixup (&inst);
17686 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
17687 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17688 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17689 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17690 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
17691 inst.instruction |= LOW4 (scalar);
17692 inst.instruction |= HI1 (scalar) << 5;
17693 inst.instruction |= (et.type == NT_float) << 8;
17694 inst.instruction |= neon_logbits (et.size) << 20;
17695 inst.instruction |= (ubit != 0) << 24;
17697 neon_dp_fixup (&inst);
17709 if (inst.operands[2].isscalar)
17715 NEON_ENCODE (SCALAR, inst);
17718 else if (!inst.operands[2].isvec)
17744 if (inst.instruction != B_MNEM_vfmab)
17747 inst.instruction = B_MNEM_vfmat;
17750 if (inst.operands[2].isscalar)
17755 inst.instruction |= (1 << 25);
17756 int idx = inst.operands[2].reg & 0xf;
17758 inst.operands[2].reg >>= 4;
17759 constraint (!(inst.operands[2].reg < 8),
17762 inst.instruction |= ((idx & 1) << 3);
17763 inst.instruction |= ((idx & 2) << 4);
17793 if (inst.operands[2].reg == REG_SP)
17795 else if (inst.operands[2].reg == REG_PC)
17798 inst.instruction = 0xee310e40;
17799 inst.instruction |= (et.size == 16) << 28;
17800 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17801 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17802 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17803 inst.instruction |= HI1 (inst.operands[1].reg) << 6;
17804 inst.instruction |= inst.operands[2].reg;
17805 inst.is_neon = 1;
17811 constraint (!inst.operands[2].isvec, BAD_FPU);
17821 inst.cond == COND_ALWAYS)
17824 inst.instruction = N_MNEM_vfma;
17825 inst.pred_insn_type = INSIDE_VPT_INSN;
17826 inst.cond = 0xf;
17857 if (inst.operands[2].isscalar)
17877 constraint (!inst.operands[2].isvec, BAD_FPU);
17890 if (inst.operands[2].isscalar)
17896 NEON_ENCODE (SCALAR, inst);
17916 NEON_ENCODE (INTEGER, inst);
17935 if (inst.cond > COND_ALWAYS)
17936 inst.pred_insn_type = INSIDE_VPT_INSN;
17938 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17940 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
17952 if (inst.cond > COND_ALWAYS)
17953 inst.pred_insn_type = INSIDE_VPT_INSN;
17955 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17957 unsigned rot = inst.relocs[0].exp.X_add_number;
17960 if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
17965 inst.instruction |= (rot == 270) << 12;
17966 inst.is_neon = 1;
17977 && (inst.operands[0].reg == inst.operands[1].reg
17978 || (rs == NS_QQQ && inst.operands[0].reg == inst.operands[2].reg)))
17981 if (inst.cond > COND_ALWAYS)
17982 inst.pred_insn_type = INSIDE_VPT_INSN;
17984 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17989 inst.instruction |= 1;
17994 inst.instruction |= 0x3 << 5;
18008 if (inst.cond > COND_ALWAYS)
18009 inst.pred_insn_type = INSIDE_VPT_INSN;
18011 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18023 if (inst.cond > COND_ALWAYS)
18024 inst.pred_insn_type = INSIDE_VPT_INSN;
18026 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18036 if (inst.cond > COND_ALWAYS)
18037 inst.pred_insn_type = INSIDE_VPT_INSN;
18039 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18051 if (inst.cond > COND_ALWAYS)
18052 inst.pred_insn_type = INSIDE_VPT_INSN;
18054 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18066 if (inst.cond > COND_ALWAYS)
18067 inst.pred_insn_type = INSIDE_VPT_INSN;
18069 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18081 if (inst.cond > COND_ALWAYS)
18082 inst.pred_insn_type = INSIDE_VPT_INSN;
18084 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18096 if (inst.cond == COND_ALWAYS
18097 && ((unsigned)inst.instruction) == M_MNEM_vmullt)
18115 && (inst.operands[0].reg == inst.operands[1].reg
18116 || inst.operands[0].reg == inst.operands[2].reg))
18119 if (inst.cond > COND_ALWAYS)
18120 inst.pred_insn_type = INSIDE_VPT_INSN;
18122 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18132 inst.instruction = N_MNEM_vmul;
18133 inst.cond = 0xb;
18135 inst.pred_insn_type = INSIDE_IT_INSN;
18154 if (inst.cond > COND_ALWAYS)
18155 inst.pred_insn_type = INSIDE_VPT_INSN;
18157 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18170 && (inst.instruction == M_MNEM_vmladavx
18171 || inst.instruction == M_MNEM_vmladavax
18172 || inst.instruction == M_MNEM_vmlsdav
18173 || inst.instruction == M_MNEM_vmlsdava
18174 || inst.instruction == M_MNEM_vmlsdavx
18175 || inst.instruction == M_MNEM_vmlsdavax))
18178 constraint (inst.operands[2].reg > 14,
18181 if (inst.cond > COND_ALWAYS)
18182 inst.pred_insn_type = INSIDE_VPT_INSN;
18184 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18186 if (inst.instruction == M_MNEM_vmlsdav
18187 || inst.instruction == M_MNEM_vmlsdava
18188 || inst.instruction == M_MNEM_vmlsdavx
18189 || inst.instruction == M_MNEM_vmlsdavax)
18190 inst.instruction |= (et.size == 8) << 28;
18192 inst.instruction |= (et.size == 8) << 8;
18195 inst.instruction |= (et.size == 32) << 16;
18207 && (inst.instruction == M_MNEM_vmlsldav
18208 || inst.instruction == M_MNEM_vmlsldava
18209 || inst.instruction == M_MNEM_vmlsldavx
18210 || inst.instruction == M_MNEM_vmlsldavax))
18213 if (inst.cond > COND_ALWAYS)
18214 inst.pred_insn_type = INSIDE_VPT_INSN;
18216 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18225 if (inst.instruction == M_MNEM_vrmlsldavh
18226 || inst.instruction == M_MNEM_vrmlsldavha
18227 || inst.instruction == M_MNEM_vrmlsldavhx
18228 || inst.instruction == M_MNEM_vrmlsldavhax)
18231 if (inst.operands[1].reg == REG_SP)
18236 if (inst.instruction == M_MNEM_vrmlaldavhx
18237 || inst.instruction == M_MNEM_vrmlaldavhax)
18246 constraint (inst.operands[1].reg == REG_SP, BAD_SP);
18253 constraint ((inst.operands[1].reg % 2) != 1, BAD_EVEN);
18254 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
18256 if (inst.cond > COND_ALWAYS)
18257 inst.pred_insn_type = INSIDE_VPT_INSN;
18259 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18272 if (inst.cond > COND_ALWAYS)
18273 inst.pred_insn_type = INSIDE_VPT_INSN;
18275 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18277 if (inst.operands[0].reg == REG_SP)
18279 else if (inst.operands[0].reg == REG_PC)
18291 if (inst.instruction == M_MNEM_vmaxv || inst.instruction == M_MNEM_vminv)
18296 if (inst.cond > COND_ALWAYS)
18297 inst.pred_insn_type = INSIDE_VPT_INSN;
18299 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18301 if (inst.operands[0].reg == REG_SP)
18303 else if (inst.operands[0].reg == REG_PC)
18319 inst.error
18326 if (inst.operands[2].isscalar)
18331 NEON_ENCODE (SCALAR, inst);
18339 NEON_ENCODE (INTEGER, inst);
18350 NEON_ENCODE (INTEGER, inst);
18397 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18398 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18399 inst.instruction |= LOW4 (inst.operands[1].reg);
18400 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18401 inst.instruction |= neon_quad (rs) << 6;
18402 inst.instruction |= (et.type == NT_float) << 10;
18403 inst.instruction |= neon_logbits (et.size) << 18;
18405 neon_dp_fixup (&inst);
18428 int imm = inst.operands[2].imm;
18453 int imm = inst.operands[2].imm;
18479 int imm = inst.operands[2].imm;
18485 inst.instruction |= (et.type == NT_unsigned) << 8;
18497 NEON_ENCODE (INTEGER, inst);
18499 inst.instruction |= 0xc0;
18501 inst.instruction |= 0x80;
18511 NEON_ENCODE (INTEGER, inst);
18522 int imm = inst.operands[2].imm;
18531 inst.operands[2].present = 0;
18532 inst.instruction = N_MNEM_vqmovn;
18549 int imm = inst.operands[2].imm;
18558 inst.operands[2].present = 0;
18559 inst.instruction = N_MNEM_vqmovun;
18577 NEON_ENCODE (INTEGER, inst);
18586 int imm = inst.operands[2].imm;
18595 inst.operands[2].present = 0;
18596 inst.instruction = N_MNEM_vmovn;
18612 unsigned imm = inst.operands[2].imm;
18617 NEON_ENCODE (INTEGER, inst);
18618 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18619 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18620 inst.instruction |= LOW4 (inst.operands[1].reg);
18621 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18622 inst.instruction |= neon_logbits (et.size) << 18;
18624 neon_dp_fixup (&inst);
18631 NEON_ENCODE (IMMED, inst);
18696 inst.error = NULL; \
18748 constraint (inst.operands[0].reg != inst.operands[1].reg,
18750 inst.operands[1] = inst.operands[2];
18751 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
18858 NEON_ENCODE (FPV8, inst);
18859 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
18860 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
18861 inst.instruction |= sz << 8;
18867 inst.instruction |= op << 7;
18868 inst.instruction |= rm << 16;
18869 inst.instruction |= 0xf0000000;
18870 inst.is_neon = true;
18953 constraint (inst.operands[2].present && inst.operands[2].imm == 0,
18961 constraint (inst.operands[2].imm > 16,
18968 constraint (inst.operands[2].imm > 32,
18972 inst.error = BAD_FPU;
18979 if (inst.operands[2].present && inst.operands[2].imm == 0)
18981 NEON_ENCODE (IMMED, inst);
18983 inst.instruction |= enctab[flavour];
18984 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18985 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18986 inst.instruction |= LOW4 (inst.operands[1].reg);
18987 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18988 inst.instruction |= neon_quad (rs) << 6;
18989 inst.instruction |= 1 << 21;
18992 inst.instruction |= 1 << 21;
18993 immbits = 32 - inst.operands[2].imm;
18994 inst.instruction |= immbits << 16;
18998 inst.instruction |= 3 << 20;
18999 immbits = 16 - inst.operands[2].imm;
19000 inst.instruction |= immbits << 16;
19001 inst.instruction &= ~(1 << 9);
19004 neon_dp_fixup (&inst);
19039 NEON_ENCODE (FLOAT, inst);
19044 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19045 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19046 inst.instruction |= LOW4 (inst.operands[1].reg);
19047 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19048 inst.instruction |= neon_quad (rs) << 6;
19049 inst.instruction |= (flavour == neon_cvt_flavour_u16_f16
19051 inst.instruction |= mode << 8;
19055 inst.instruction = ((inst.instruction & 0xfff3ffff) | (1 << 18));
19058 inst.instruction |= 0xfc000000;
19060 inst.instruction |= 0xf0000000;
19069 NEON_ENCODE (INTEGER, inst);
19078 inst.instruction |= enctab[flavour];
19080 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19081 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19082 inst.instruction |= LOW4 (inst.operands[1].reg);
19083 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19084 inst.instruction |= neon_quad (rs) << 6;
19088 inst.instruction |= 1 << 18;
19090 inst.instruction |= 2 << 18;
19092 neon_dp_fixup (&inst);
19104 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
19111 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
19125 inst.instruction = 0x11b60640;
19129 inst.instruction = 0x3b60600;
19133 inst.instruction = 0x3b60700;
19135 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19136 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19137 inst.instruction |= LOW4 (inst.operands[1].reg);
19138 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19139 neon_dp_fixup (&inst);
19193 encode_arm_vfp_reg (inst.operands[0].reg,
19195 encode_arm_vfp_reg (inst.operands[1].reg,
19197 inst.instruction |= to ? 0x10000 : 0;
19198 inst.instruction |= t ? 0x80 : 0;
19199 inst.instruction |= is_double ? 0x100 : 0;
19229 inst.cond = 0xf;
19230 inst.instruction = N_MNEM_vcvt;
19243 unsigned op0 = inst.operands[0].reg;
19244 unsigned op1 = inst.operands[1].reg;
19245 /* NS_QQ so both registers are quads but inst.operands has their
19252 inst.instruction = 0xee3f0e01;
19253 inst.instruction |= single_to_half << 28;
19254 inst.instruction |= HI1 (op0) << 22;
19255 inst.instruction |= LOW4 (op0) << 13;
19256 inst.instruction |= t << 12;
19257 inst.instruction |= HI1 (op1) << 5;
19258 inst.instruction |= LOW4 (op1) << 1;
19259 inst.is_neon = 1;
19263 inst.error = NULL;
19268 inst.error = NULL;
19278 inst.error = NULL;
19288 inst.error = NULL;
19294 inst.error = NULL;
19295 inst.instruction |= (1 << 8);
19296 inst.instruction &= ~(1 << 9);
19329 op = (inst.instruction & (1 << 5)) != 0;
19331 immlo = inst.operands[1].imm;
19332 if (inst.operands[1].regisimm)
19333 immhi = inst.operands[1].reg;
19338 float_p = inst.operands[1].immisfloat;
19357 inst.instruction &= ~(1 << 5);
19358 inst.instruction |= op << 5;
19360 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19361 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19362 inst.instruction |= neon_quad (rs) << 6;
19363 inst.instruction |= cmode << 8;
19374 if (inst.operands[1].isreg)
19385 NEON_ENCODE (INTEGER, inst);
19386 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19387 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19388 inst.instruction |= LOW4 (inst.operands[1].reg);
19389 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19390 inst.instruction |= neon_quad (rs) << 6;
19394 NEON_ENCODE (IMMED, inst);
19398 neon_dp_fixup (&inst);
19402 constraint (!inst.operands[1].isreg && !inst.operands[0].isquad, BAD_FPU);
19414 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19415 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19416 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19417 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19418 inst.instruction |= LOW4 (inst.operands[2].reg);
19419 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
19420 inst.instruction |= (et.type == NT_unsigned) << 24;
19421 inst.instruction |= neon_logbits (size) << 20;
19423 neon_dp_fixup (&inst);
19435 NEON_ENCODE (INTEGER, inst);
19442 && (inst.cond == 0xf || inst.cond == 0x10))
19447 if (inst.cond == 0xf)
19448 inst.cond = 0xb;
19449 else if (inst.cond == 0x10)
19450 inst.cond = 0xd;
19452 inst.pred_insn_type = INSIDE_IT_INSN;
19454 if (inst.instruction == N_MNEM_vaddl)
19456 inst.instruction = N_MNEM_vadd;
19459 else if (inst.instruction == N_MNEM_vsubl)
19461 inst.instruction = N_MNEM_vsub;
19464 else if (inst.instruction == N_MNEM_vabdl)
19466 inst.instruction = N_MNEM_vabd;
19485 if (inst.operands[2].isscalar)
19489 NEON_ENCODE (SCALAR, inst);
19496 NEON_ENCODE (INTEGER, inst);
19553 if (inst.operands[2].isscalar)
19565 inst.instruction |= (0x1 << 23);
19570 if (inst.cond != COND_ALWAYS)
19587 inst.instruction &= 0x00ffffff;
19588 inst.instruction |= high8;
19593 if (inst.operands[2].isscalar)
19596 = neon_scalar_for_fmac_fp16_long (inst.operands[2].reg, quad_p);
19597 inst.instruction &= 0xffffffd0;
19598 inst.instruction |= rm;
19603 inst.instruction &= 0xfff0ff7f;
19604 inst.instruction |= HI4 (inst.operands[1].reg) << 16;
19605 inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
19611 inst.instruction &= 0xfff0ff50;
19612 inst.instruction |= HI4 (inst.operands[1].reg) << 16;
19613 inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
19614 inst.instruction |= HI4 (inst.operands[2].reg);
19615 inst.instruction |= LOW1 (inst.operands[2].reg) << 5;
19659 if (inst.operands[2].isscalar)
19667 NEON_ENCODE (POLY, inst);
19669 NEON_ENCODE (INTEGER, inst);
19678 inst.error =
19694 unsigned imm = (inst.operands[3].imm * et.size) / 8;
19698 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19699 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19700 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19701 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19702 inst.instruction |= LOW4 (inst.operands[2].reg);
19703 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
19704 inst.instruction |= neon_quad (rs) << 6;
19705 inst.instruction |= imm << 8;
19707 neon_dp_fixup (&inst);
19725 unsigned op = (inst.instruction >> 7) & 3;
19732 && inst.operands[0].reg == inst.operands[1].reg)
19745 if (inst.operands[1].isscalar)
19753 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
19755 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
19760 NEON_ENCODE (SCALAR, inst);
19761 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19762 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19763 inst.instruction |= LOW4 (dm);
19764 inst.instruction |= HI1 (dm) << 5;
19765 inst.instruction |= neon_quad (rs) << 6;
19766 inst.instruction |= x << 17;
19767 inst.instruction |= sizebits << 16;
19769 neon_dp_fixup (&inst);
19787 if (inst.operands[1].reg == REG_SP)
19789 else if (inst.operands[1].reg == REG_PC)
19794 NEON_ENCODE (ARMREG, inst);
19797 case 8: inst.instruction |= 0x400000; break;
19798 case 16: inst.instruction |= 0x000020; break;
19799 case 32: inst.instruction |= 0x000000; break;
19802 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
19803 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
19804 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
19805 inst.instruction |= neon_quad (rs) << 21;
19817 if (inst.cond > COND_ALWAYS)
19818 inst.pred_insn_type = MVE_UNPREDICABLE_INSN;
19829 constraint (inst.operands[Q0].reg != inst.operands[Q1].reg + 2,
19832 constraint (!toQ && inst.operands[Rt].reg == inst.operands[Rt2].reg,
19834 constraint (inst.operands[Rt].reg == REG_SP
19835 || inst.operands[Rt2].reg == REG_SP,
19837 constraint (inst.operands[Rt].reg == REG_PC
19838 || inst.operands[Rt2].reg == REG_PC,
19841 inst.instruction = 0xec000f00;
19842 inst.instruction |= HI1 (inst.operands[Q1].reg / 32) << 23;
19843 inst.instruction |= !!toQ << 20;
19844 inst.instruction |= inst.operands[Rt2].reg << 16;
19845 inst.instruction |= LOW4 (inst.operands[Q1].reg / 32) << 13;
19846 inst.instruction |= (inst.operands[Q1].reg % 4) << 4;
19847 inst.instruction |= inst.operands[Rt].reg;
19856 if (inst.cond > COND_ALWAYS)
19857 inst.pred_insn_type = INSIDE_VPT_INSN;
19859 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
19864 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19865 inst.instruction |= (neon_logbits (et.size) - 1) << 18;
19866 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19867 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19868 inst.instruction |= LOW4 (inst.operands[1].reg);
19869 inst.is_neon = 1;
19934 inst.error = NULL;
19956 inst.instruction = 0x0200110;
19957 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19958 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19959 inst.instruction |= LOW4 (inst.operands[1].reg);
19960 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19961 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19962 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19963 inst.instruction |= neon_quad (rs) << 6;
19965 neon_dp_fixup (&inst);
19971 inst.error = NULL;
19984 inst.instruction = 0x0800010;
19986 neon_dp_fixup (&inst);
19993 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
19994 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
19997 if (inst.vectype.elems == 0
19998 && inst.operands[0].vectype.type == NT_invtype
19999 && inst.operands[1].vectype.type == NT_invtype)
20001 inst.vectype.el[0].type = NT_untyped;
20002 inst.vectype.el[0].size = 32;
20003 inst.vectype.elems = 1;
20024 if (inst.operands[1].reg == REG_SP)
20026 else if (inst.operands[1].reg == REG_PC)
20029 unsigned size = inst.operands[0].isscalar == 1 ? 64 : 128;
20045 inst.instruction = 0xe000b10;
20047 inst.instruction |= LOW4 (dn) << 16;
20048 inst.instruction |= HI1 (dn) << 7;
20049 inst.instruction |= inst.operands[1].reg << 12;
20050 inst.instruction |= (bcdebits & 3) << 5;
20051 inst.instruction |= ((bcdebits >> 2) & 3) << 21;
20052 inst.instruction |= (x >> (3-logsize)) << 16;
20061 inst.instruction = 0xc400b10;
20063 inst.instruction |= LOW4 (inst.operands[0].reg);
20064 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
20065 inst.instruction |= inst.operands[1].reg << 12;
20066 inst.instruction |= inst.operands[2].reg << 16;
20072 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
20073 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
20077 if (inst.vectype.elems == 0
20078 && inst.operands[0].vectype.type == NT_invtype
20079 && inst.operands[1].vectype.type == NT_invtype)
20081 inst.vectype.el[0].type = NT_untyped;
20082 inst.vectype.el[0].size = 32;
20083 inst.vectype.elems = 1;
20106 if (inst.operands[0].reg == REG_SP)
20108 else if (inst.operands[0].reg == REG_PC)
20112 unsigned size = inst.operands[1].isscalar == 1 ? 64 : 128;
20126 inst.instruction = 0xe100b10;
20128 inst.instruction |= LOW4 (dn) << 16;
20129 inst.instruction |= HI1 (dn) << 7;
20130 inst.instruction |= inst.operands[0].reg << 12;
20131 inst.instruction |= (abcdebits & 3) << 5;
20132 inst.instruction |= (abcdebits >> 2) << 21;
20133 inst.instruction |= (x >> (3-logsize)) << 16;
20142 inst.instruction = 0xc500b10;
20144 inst.instruction |= inst.operands[0].reg << 12;
20145 inst.instruction |= inst.operands[1].reg << 16;
20146 inst.instruction |= LOW4 (inst.operands[2].reg);
20147 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
20158 if (!inst.operands[1].immisfloat)
20162 float imm = (float) inst.operands[1].imm;
20169 if (is_quarter_float (inst.operands[1].imm))
20172 inst.operands[1].imm = new_imm;
20173 inst.operands[1].immisfloat = 1;
20177 if (is_quarter_float (inst.operands[1].imm))
20179 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
20221 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
20223 inst.operands[2].imm = 2;
20224 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
20232 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
20234 inst.operands[1] = inst.operands[2];
20235 inst.operands[2] = inst.operands[3];
20236 inst.operands[0].imm = 2;
20237 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
20254 if (!(inst.operands[0].present && inst.operands[0].isquad
20255 && inst.operands[1].present && inst.operands[1].isquad
20256 && !inst.operands[2].present))
20258 inst.instruction = 0;
20259 inst.cond = 0xb;
20269 if (inst.cond != COND_ALWAYS)
20270 inst.pred_insn_type = INSIDE_VPT_INSN;
20275 inst.instruction |= (et.type == NT_unsigned) << 28;
20276 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20277 inst.instruction |= (neon_logbits (et.size) + 1) << 19;
20278 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20279 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
20280 inst.instruction |= LOW4 (inst.operands[1].reg);
20281 inst.is_neon = 1;
20303 int imm = inst.operands[2].imm;
20308 inst.operands[2].present = 0;
20325 if (inst.cond != COND_ALWAYS)
20334 inst.error = BAD_COND;
20341 inst.is_neon = 1;
20342 inst.instruction |= 0xf0000000;
20351 inst.instruction |= sizebits << 19;
20361 NEON_ENCODE (INTEGER, inst);
20374 inst.instruction = N_MNEM_vtrn;
20403 inst.instruction |= (et.type == NT_unsigned) << 7;
20413 inst.instruction |= (et.type == NT_float) << 8;
20475 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
20481 listlenbits = inst.operands[1].imm - 1;
20482 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20483 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20484 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
20485 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
20486 inst.instruction |= LOW4 (inst.operands[2].reg);
20487 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
20488 inst.instruction |= listlenbits << 8;
20490 neon_dp_fixup (&inst);
20500 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
20501 unsigned offsetbits = inst.operands[1].imm * 2;
20503 if (inst.operands[1].issingle)
20509 constraint (is_dbmode && !inst.operands[0].writeback,
20512 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
20516 inst.instruction |= inst.operands[0].reg << 16;
20517 inst.instruction |= inst.operands[0].writeback << 21;
20518 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
20519 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
20521 inst.instruction |= offsetbits;
20531 if (inst.operands[1].issingle)
20533 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 32,
20538 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
20553 if (inst.operands[1].issingle)
20569 if (inst.operands[1].issingle)
20578 int is_ldr = (inst.instruction & (1 << 20)) != 0;
20583 && inst.operands[1].reg == REG_PC
20587 inst.error = _("Use of PC here is UNPREDICTABLE");
20592 if (inst.operands[0].issingle)
20600 if (inst.vectype.el[0].size == 16)
20616 bool is_vldr = ((inst.instruction & (1 << fp_vldr_bitno)) != 0);
20619 if (inst.operands[1].reg == REG_PC)
20620 inst.error = _("Use of PC here is UNPREDICTABLE");
20622 if (inst.operands[1].immisreg)
20623 inst.error = _("instruction does not accept register index");
20625 if (!inst.operands[1].isreg)
20626 inst.error = _("instruction does not accept PC-relative addressing");
20628 if (abs (inst.operands[1].imm) >= (1 << 7))
20629 inst.error = _("immediate value out of range");
20631 inst.instruction = 0xec000f80;
20633 inst.instruction |= 1 << sysreg_vldr_bitno;
20635 inst.instruction |= (inst.operands[0].imm & 0x7) << 13;
20636 inst.instruction |= (inst.operands[0].imm & 0x8) << 19;
20642 bool sysreg_op = !inst.operands[0].isreg;
20689 if (inst.operands[1].immisalign)
20690 switch (inst.operands[1].imm >> 8)
20694 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
20695 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
20700 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
20710 inst.instruction |= alignbits << 4;
20711 inst.instruction |= neon_logbits (et.size) << 6;
20718 idx = ((inst.operands[0].imm >> 4) & 7)
20719 | (((inst.instruction >> 8) & 3) << 3);
20724 constraint (((inst.instruction >> 8) & 3) && et.size == 64,
20727 inst.instruction &= ~0xf00;
20728 inst.instruction |= typebits << 8;
20742 if (!inst.operands[1].immisalign)
20778 int align = inst.operands[1].imm >> 8;
20779 int n = (inst.instruction >> 8) & 3;
20785 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
20787 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
20789 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
20809 inst.instruction |= alignbits << 4;
20819 inst.instruction |= 1 << 4;
20823 constraint (inst.operands[1].immisalign,
20842 inst.instruction |= alignbits << 4;
20850 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
20851 inst.instruction |= 1 << (4 + logsize);
20853 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
20854 inst.instruction |= logsize << 10;
20868 switch ((inst.instruction >> 8) & 3)
20871 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
20872 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
20876 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
20879 case 2: inst.instruction |= 1 << 5; break;
20882 inst.instruction |= neon_logbits (et.size) << 6;
20886 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
20891 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
20893 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
20894 inst.instruction |= 1 << 5;
20895 inst.instruction |= neon_logbits (et.size) << 6;
20899 constraint (inst.operands[1].immisalign,
20901 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
20903 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
20904 inst.instruction |= 1 << 5;
20905 inst.instruction |= neon_logbits (et.size) << 6;
20910 int align = inst.operands[1].imm >> 8;
20915 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
20917 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
20918 inst.instruction |= 1 << 5;
20920 inst.instruction |= 0x3 << 6;
20922 inst.instruction |= neon_logbits (et.size) << 6;
20929 inst.instruction |= do_alignment << 4;
20938 if (inst.operands[1].isreg)
20939 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
20941 switch (NEON_LANE (inst.operands[0].imm))
20944 NEON_ENCODE (INTERLV, inst);
20949 NEON_ENCODE (DUP, inst);
20950 if (inst.instruction == N_INV)
20959 NEON_ENCODE (LANE, inst);
20964 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20965 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20966 inst.instruction |= inst.operands[1].reg << 16;
20968 if (inst.operands[1].postind)
20970 int postreg = inst.operands[1].imm & 0xf;
20971 constraint (!inst.operands[1].immisreg,
20975 inst.instruction |= postreg;
20979 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
20980 constraint (inst.relocs[0].exp.X_op != O_constant
20981 || inst.relocs[0].exp.X_add_number != 0,
20984 if (inst.operands[1].writeback)
20986 inst.instruction |= 0xd;
20989 inst.instruction |= 0xf;
20993 inst.instruction |= 0xf9000000;
20995 inst.instruction |= 0xf4000000;
21008 NEON_ENCODE (FPV8, inst);
21022 inst.instruction |= 0x100;
21024 inst.instruction |= 0xf0000000;
21075 NEON_ENCODE (FPV8, inst);
21083 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
21084 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
21085 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
21086 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
21087 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
21088 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
21089 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
21093 inst.instruction |= (rs == NS_DD) << 8;
21103 inst.error = NULL;
21113 NEON_ENCODE (FLOAT, inst);
21115 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21116 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21117 inst.instruction |= LOW4 (inst.operands[1].reg);
21118 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
21119 inst.instruction |= neon_quad (rs) << 6;
21121 inst.instruction = ((inst.instruction & 0xfff3ffff)
21126 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
21127 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
21128 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
21129 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
21130 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
21131 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
21132 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
21137 inst.instruction |= 0xfc000000;
21139 inst.instruction |= 0xf0000000;
21206 constraint (inst.relocs[0].exp.X_op != O_constant,
21208 unsigned rot = inst.relocs[0].exp.X_add_number;
21217 if (inst.operands[2].isscalar)
21224 unsigned m = neon_scalar_for_vcmla (inst.operands[2].reg, size);
21225 inst.is_neon = 1;
21226 inst.instruction = 0xfe000800;
21227 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21228 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21229 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
21230 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
21231 inst.instruction |= LOW4 (m);
21232 inst.instruction |= HI1 (m) << 5;
21233 inst.instruction |= neon_quad (rs) << 6;
21234 inst.instruction |= rot << 20;
21235 inst.instruction |= (size == 32) << 23;
21248 && (inst.operands[0].reg == inst.operands[1].reg
21249 || inst.operands[0].reg == inst.operands[2].reg))
21253 inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
21254 inst.instruction |= 0xfc200800;
21255 inst.instruction |= rot << 23;
21256 inst.instruction |= (size == 32) << 20;
21266 constraint (inst.relocs[0].exp.X_op != O_constant,
21269 unsigned rot = inst.relocs[0].exp.X_add_number;
21283 if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
21298 inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
21299 inst.instruction |= 0xfc800800;
21300 inst.instruction |= (rot == 270) << 24;
21301 inst.instruction |= (et.size == 32) << 20;
21306 inst.instruction = 0xfe000f00;
21307 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21308 inst.instruction |= neon_logbits (et.size) << 20;
21309 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
21310 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21311 inst.instruction |= (rot == 270) << 12;
21312 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
21313 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
21314 inst.instruction |= LOW4 (inst.operands[2].reg);
21315 inst.is_neon = 1;
21328 if (inst.cond != COND_ALWAYS)
21337 if (inst.operands[2].isscalar)
21339 scalar_oprd2 = neon_scalar_for_mul (inst.operands[2].reg, 32);
21361 inst.instruction &= 0x00ffffff;
21362 inst.instruction |= high8;
21364 inst.instruction |= (unsigned_p ? 1 : 0) << 4;
21366 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21368 if (inst.operands[2].isscalar)
21370 inst.instruction &= 0xffffffd0;
21371 inst.instruction |= LOW4 (scalar_oprd2);
21372 inst.instruction |= HI1 (scalar_oprd2) << 5;
21397 if (inst.operands[2].isscalar)
21402 inst.instruction |= (1 << 25);
21403 int idx = inst.operands[2].reg & 0xf;
21405 inst.operands[2].reg >>= 4;
21406 constraint (!(inst.operands[2].reg < 16),
21409 inst.instruction |= (idx << 5);
21413 inst.instruction |= (1 << 21);
21425 if (inst.operands[2].isscalar)
21430 inst.instruction |= (1 << 25);
21431 int idx = inst.operands[2].reg & 0xf;
21433 inst.operands[2].reg >>= 4;
21434 constraint (!(inst.operands[2].reg < 16),
21437 inst.instruction |= (idx << 5);
21468 unsigned Rx = inst.operands[idx].reg;
21469 bool isvec = inst.operands[idx].isvec;
21500 unsigned coproc = inst.operands[0].reg;
21503 inst.instruction |= coproc << cde_coproc_pos;
21516 inst.error = BAD_SYNTAX;
21529 Rd = inst.operands[1].reg;
21534 constraint (inst.operands[2].reg != Rd + 1,
21536 imm = inst.operands[3].imm;
21539 imm = inst.operands[2].imm;
21543 inst.instruction |= Rd << 12;
21544 inst.instruction |= (imm & 0x1F80) << 9;
21545 inst.instruction |= (imm & 0x0040) << 1;
21546 inst.instruction |= (imm & 0x003f);
21560 Rd = inst.operands[1].reg;
21564 constraint (inst.operands[2].reg != Rd + 1,
21566 imm = inst.operands[4].imm;
21567 Rn = inst.operands[3].reg;
21571 imm = inst.operands[3].imm;
21572 Rn = inst.operands[2].reg;
21580 inst.instruction |= Rd << 12;
21581 inst.instruction |= Rn << 16;
21583 inst.instruction |= (imm & 0x0380) << 13;
21584 inst.instruction |= (imm & 0x0040) << 1;
21585 inst.instruction |= (imm & 0x003f);
21599 Rd = inst.operands[1].reg;
21603 constraint (inst.operands[2].reg != Rd + 1,
21605 imm = inst.operands[5].imm;
21606 Rn = inst.operands[3].reg;
21607 Rm = inst.operands[4].reg;
21611 imm = inst.operands[4].imm;
21612 Rn = inst.operands[2].reg;
21613 Rm = inst.operands[3].reg;
21622 inst.instruction |= Rd;
21623 inst.instruction |= Rn << 16;
21624 inst.instruction |= Rm << 12;
21626 inst.instruction |= (imm & 0x0038) << 17;
21627 inst.instruction |= (imm & 0x0004) << 5;
21628 inst.instruction |= (imm & 0x0003) << 4;
21709 inst.instruction |= HI4 (regnum) << 12;
21710 inst.instruction |= LOW1 (regnum) << 22;
21716 inst.instruction |= HI4 (regnum);
21717 inst.instruction |= LOW1 (regnum) << 5;
21723 inst.instruction |= HI4 (regnum) << 16;
21724 inst.instruction |= LOW1 (regnum) << 7;
21759 inst.instruction |= 1 << vcx_vec_pos;
21761 inst.instruction |= 1 << vcx_size_pos;
21818 R = inst.operands[i+1].reg;
21836 if (inst.cond > COND_ALWAYS)
21837 inst.pred_insn_type = INSIDE_VPT_INSN;
21839 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
21840 else if (inst.cond == COND_ALWAYS)
21841 inst.pred_insn_type = OUTSIDE_PRED_INSN;
21843 inst.error = BAD_NOT_IT;
21871 unsigned imm = inst.operands[2].imm;
21872 inst.instruction |= (imm & 0x03f);
21873 inst.instruction |= (imm & 0x040) << 1;
21874 inst.instruction |= (imm & 0x780) << 9;
21878 inst.instruction |= (imm & 0x800) << 13;
21887 unsigned imm = inst.operands[3].imm;
21888 inst.instruction |= (imm & 0x01) << 4;
21889 inst.instruction |= (imm & 0x02) << 6;
21890 inst.instruction |= (imm & 0x3c) << 14;
21894 inst.instruction |= (imm & 0x40) << 18;
21903 unsigned imm = inst.operands[4].imm;
21904 inst.instruction |= (imm & 0x1) << 4;
21905 inst.instruction |= (imm & 0x6) << 19;
21909 inst.instruction |= (imm & 0x8) << 21;
21922 inst.error = NULL;
21924 NEON_ENCODE (INTEGER, inst);
21925 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21926 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21927 inst.instruction |= LOW4 (inst.operands[1].reg);
21928 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
21930 inst.instruction |= op << 6;
21933 inst.instruction |= 0xfc000000;
21935 inst.instruction |= 0xf0000000;
21947 inst.error = NULL;
21949 NEON_ENCODE (INTEGER, inst);
22040 unsigned int Rd = inst.operands[0].reg;
22041 unsigned int Rn = inst.operands[1].reg;
22042 unsigned int Rm = inst.operands[2].reg;
22045 inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
22046 inst.instruction |= LOW4 (Rn) << 16;
22047 inst.instruction |= LOW4 (Rm);
22048 inst.instruction |= sz << (thumb_mode ? 4 : 21);
22049 inst.instruction |= poly << (thumb_mode ? 20 : 9);
22107 if (inst.operands[2].isscalar)
22112 inst.instruction |= (1 << 25);
22113 int idx = inst.operands[2].reg & 0xf;
22115 inst.operands[2].reg >>= 4;
22116 constraint (!(inst.operands[2].reg < 16),
22119 inst.instruction |= (idx << 5);
22144 inst.instruction = THUMB_OP32 (inst.instruction);
22153 inst.instruction = THUMB_OP32 (inst.instruction);
22154 inst.instruction |= inst.operands[0].reg << 12;
22155 inst.instruction |= inst.operands[1].reg << 16;
22156 inst.instruction |= inst.operands[2].reg;
22165 inst.instruction = THUMB_OP32 (inst.instruction);
22166 inst.instruction |= inst.operands[0].reg << 8;
22167 inst.instruction |= inst.operands[1].reg << 16;
22168 inst.instruction |= inst.operands[2].reg;
22248 switch (inst.relocs[0].exp.X_op)
22251 sym = inst.relocs[0].exp.X_add_symbol;
22252 offset = inst.relocs[0].exp.X_add_number;
22256 offset = inst.relocs[0].exp.X_add_number;
22259 sym = make_expr_symbol (&inst.relocs[0].exp);
22264 inst.relax, sym, offset, NULL/*offset, opcode*/);
22265 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
22281 if (inst.error)
22283 as_bad ("%s -- `%s'", inst.error, str);
22286 if (inst.relax)
22291 if (inst.size == 0)
22294 to = frag_more (inst.size);
22301 if (thumb_mode && (inst.size > THUMB_SIZE))
22303 gas_assert (inst.size == (2 * THUMB_SIZE));
22304 put_thumb32_insn (to, inst.instruction);
22306 else if (inst.size > INSN_SIZE)
22308 gas_assert (inst.size == (2 * INSN_SIZE));
22309 md_number_to_chars (to, inst.instruction, INSN_SIZE);
22310 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
22313 md_number_to_chars (to, inst.instruction, inst.size);
22318 if (inst.relocs[r].type != BFD_RELOC_UNUSED)
22320 inst.size, & inst.relocs[r].exp, inst.relocs[r].pc_rel,
22321 inst.relocs[r].type);
22324 dwarf2_emit_insn (inst.size);
22422 infix; look it up in the conditions table and set inst.cond
22424 Again set inst.cond accordingly. Return the opcode structure.
22428 Otherwise, set inst.cond from the suffix we already looked up,
22462 inst.size_req = 4;
22464 inst.size_req = 2;
22468 inst.vectype.elems = 0;
22476 if (parse_neon_type (&inst.vectype, str) == FAIL)
22493 inst.cond = COND_ALWAYS;
22503 inst.cond = cond->value;
22569 inst.cond = cond->value;
22575 inst.cond = cond->value;
22579 inst.error = BAD_COND;
22580 inst.cond = COND_ALWAYS;
22618 inst.cond = cond->value;
22691 on the inst.condition.
22711 that determines the insn IT type depending on the inst.cond code.
22715 IT instruction type based on the inst.cond code. Otherwise,
22727 In that case, inst.error is set.
22728 Therefore, inst.error has to be checked after the execution of
22738 if (inst.cond != COND_ALWAYS)
22739 inst.pred_insn_type = INSIDE_IT_INSN;
22741 inst.pred_insn_type = OUTSIDE_PRED_INSN;
22787 switch (inst.pred_insn_type)
22791 if (inst.cond < COND_ALWAYS)
22795 inst.error = BAD_SYNTAX;
22801 if (inst.cond > COND_ALWAYS)
22805 inst.error = BAD_SYNTAX;
22814 inst.error = BAD_OUT_VPT;
22819 if (inst.cond < COND_ALWAYS)
22836 new_automatic_it_block (inst.cond);
22837 if (inst.pred_insn_type == INSIDE_IT_LAST_INSN)
22842 inst.error = BAD_OUT_IT;
22848 else if (inst.cond > COND_ALWAYS)
22852 inst.error = BAD_SYNTAX;
22862 if (inst.cond != COND_ALWAYS)
22885 switch (inst.pred_insn_type)
22904 || !now_pred_compatible (inst.cond))
22907 if (inst.pred_insn_type != IF_INSIDE_IT_LAST_INSN)
22908 new_automatic_it_block (inst.cond);
22913 now_pred_add_mask (inst.cond);
22917 && (inst.pred_insn_type == INSIDE_IT_LAST_INSN
22918 || inst.pred_insn_type == IF_INSIDE_IT_LAST_INSN))
22962 switch (inst.pred_insn_type)
22967 if (inst.cond == COND_ALWAYS)
22971 inst.error = BAD_NOT_IT;
22974 else if (inst.cond > COND_ALWAYS)
22978 inst.error = BAD_SYNTAX;
22989 inst.error = BAD_NOT_IT;
23003 if (inst.cond == COND_ALWAYS)
23010 else if (inst.cond < COND_ALWAYS)
23014 inst.error = BAD_SYNTAX;
23022 if (inst.cond < COND_ALWAYS)
23026 inst.error = BAD_SYNTAX;
23029 else if (inst.cond == COND_ALWAYS)
23033 inst.error = BAD_NOT_VPT;
23045 if (inst.cond > COND_ALWAYS)
23049 inst.error = BAD_SYNTAX;
23055 if (cond != inst.cond)
23057 inst.error = now_pred.type == SCALAR_PRED ? BAD_IT_COND :
23066 inst.error = BAD_OUT_IT;
23076 inst.error = BAD_OUT_VPT;
23080 else if (cond != inst.cond)
23082 inst.error = BAD_VPT_COND;
23088 if (now_pred.type == VECTOR_PRED || inst.cond > COND_ALWAYS)
23092 inst.error = BAD_SYNTAX;
23095 else if (cond != inst.cond)
23097 inst.error = BAD_IT_COND;
23102 inst.error = BAD_BRANCH;
23115 inst.error = BAD_IT_IT;
23120 if (inst.cond == COND_ALWAYS)
23134 inst.error = BAD_SYNTAX;
23183 if (inst.instruction >= 0x10000)
23195 if ((inst.instruction & p->mask) == p->pattern)
23317 memset (&inst, '\0', sizeof (inst));
23320 inst.relocs[r].type = BFD_RELOC_UNUSED;
23339 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1u;
23360 if (inst.cond != COND_ALWAYS && !unified_syntax
23378 if (inst.size_req == 0)
23379 inst.size_req = 2;
23380 else if (inst.size_req == 4)
23392 inst.instruction = opcode->tvalue;
23405 if (!(inst.error || inst.relax))
23407 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
23408 inst.size = (inst.instruction > 0xffff ? 4 : 2);
23409 if (inst.size_req && inst.size_req != inst.size)
23418 gas_assert (inst.size_req == 0 || !inst.relax);
23430 if (inst.size == 4 && !t32_insn_ok (variant, opcode))
23436 if (!inst.error)
23456 if (inst.size_req)
23462 inst.instruction = opcode->avalue;
23464 inst.instruction |= 0xFU << 28;
23466 inst.instruction |= inst.cond << 28;
23467 inst.size = INSN_SIZE;
23484 if (!inst.error)
Indexes created Sat Feb 28 05:31:39 UTC 2026