Cross Reference: /src/external/gpl3/binutils.old/dist/gas/config/tc-microblaze.c

Lines Matching defs:immed
889   unsigned int immed = 0, immed2 = 0, temp;
1029 	  immed = 0;
1034           immed = exp.X_add_number;
1057           inst |= (immed << IMM_LOW) & IMM_MASK;
1066               immed = immed + 4;
1071               inst |= (immed << IMM_LOW) & IMM_MASK;
1076           temp = immed & 0xFFFF8000;
1088               inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
1097 	  inst |= (immed << IMM_LOW) & IMM_MASK;
1132           immed = exp.X_add_number;
1135       if (immed != (immed % 32))
1138           immed = immed % 32;
1142       inst |= (immed << IMM_LOW) & IMM5_MASK;
1178 	  immed = 1;
1181 	immed = exp.X_add_number;
1183       if (opcode->instr == bsefi && immed > 31)
1211       if (immed + immed2 > 32)
1218 	inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */
1220 	inst |= ((immed + immed2 - 1) & IMM5_MASK)
1289         op_end = parse_reg (op_end + 1, &immed);  /* Get rfslN.  */
1293           immed = 0;
1301       inst |= (immed << IMM_LOW) & RFSL_MASK;
1328           immed = exp.X_add_number;
1331       inst |= (immed << IMM_LOW) & IMM15_MASK;
1343         op_end = parse_reg (op_end + 1, &immed);  /* Get rfslN.  */
1347           immed = 0;
1355       inst |= (immed << IMM_LOW) & RFSL_MASK;
1361         op_end = parse_reg (op_end + 1, &immed);  /* Get rfslN.  */
1365           immed = 0;
1367       inst |= (immed << IMM_LOW) & RFSL_MASK;
1423         immed = opcode->immval_mask | REG_MSR_MASK;
1425         immed = opcode->immval_mask | REG_PC_MASK;
1427         immed = opcode->immval_mask | REG_EAR_MASK;
1429         immed = opcode->immval_mask | REG_ESR_MASK;
1431         immed = opcode->immval_mask | REG_FSR_MASK;
1433         immed = opcode->immval_mask | REG_BTR_MASK;
1435         immed = opcode->immval_mask | REG_EDR_MASK;
1437         immed = opcode->immval_mask | REG_PID_MASK;
1439         immed = opcode->immval_mask | REG_ZPR_MASK;
1441         immed = opcode->immval_mask | REG_TLBX_MASK;
1443         immed = opcode->immval_mask | REG_TLBLO_MASK;
1445         immed = opcode->immval_mask | REG_TLBHI_MASK;
1447         immed = opcode->immval_mask | REG_SHR_MASK;
1449         immed = opcode->immval_mask | REG_SLR_MASK;
1451 	immed = opcode->immval_mask | REG_PVR_MASK | reg2;
1455       inst |= (immed << IMM_LOW) & IMM_MASK;
1476         immed = opcode->immval_mask | REG_MSR_MASK;
1478         immed = opcode->immval_mask | REG_PC_MASK;
1480         immed = opcode->immval_mask | REG_EAR_MASK;
1482         immed = opcode->immval_mask | REG_ESR_MASK;
1484         immed = opcode->immval_mask | REG_FSR_MASK;
1486         immed = opcode->immval_mask | REG_BTR_MASK;
1488         immed = opcode->immval_mask | REG_EDR_MASK;
1490         immed = opcode->immval_mask | REG_PID_MASK;
1492         immed = opcode->immval_mask | REG_ZPR_MASK;
1494         immed = opcode->immval_mask | REG_TLBX_MASK;
1496         immed = opcode->immval_mask | REG_TLBLO_MASK;
1498         immed = opcode->immval_mask | REG_TLBHI_MASK;
1500         immed = opcode->immval_mask | REG_TLBSX_MASK;
1502         immed = opcode->immval_mask | REG_SHR_MASK;
1504         immed = opcode->immval_mask | REG_SLR_MASK;
1508       inst |= (immed << IMM_LOW) & IMM_MASK;
1602 	  immed = 0;
1607           immed = exp.X_add_number;
1610       temp = immed & 0xFFFF8000;
1622           inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
1631       inst |= (immed << IMM_LOW) & IMM_MASK;
1668           immed = 0;
1673           immed = exp.X_add_number;
1676       temp = immed & 0xFFFF8000;
1688           inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
1697       inst |= (immed << IMM_LOW) & IMM_MASK;
1740           immed = 0;
1745           immed = exp.X_add_number;
1749       temp = immed & 0xFFFF8000;
1761           inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
1768       inst |= (immed << IMM_LOW) & IMM_MASK;
1784         immed = exp.X_add_number;
1786       if (immed != (immed % 32)) {
1788         immed = immed % 32;
1790       inst |= (immed << IMM_MBAR);
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