Lines Matching defs:BIT
38 /* The enumeration strings associated with each value of a 5-bit SVE
79 /* The enumeration strings associated with each value of a 4-bit SVE
102 /* The enumeration strings associated with each value of a 6-bit RPRFM
225 /* Instruction bit-fields.
231 { 10, 2 }, /* CRm_dsb_nxs: 2-bit imm. encoded in CRm<3:2>. */
254 { 16, 1 }, /* SME_Q: Q class bit, bit 16. */
257 { 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */
258 { 10, 1 }, /* SME_VL_10: VLx2 or VLx4, bit [10]. */
259 { 13, 1 }, /* SME_VL_13: VLx2 or VLx4, bit [13]. */
270 { 4, 1 }, /* SME_ZtT: upper bit of Zt, bit [4]. */
273 { 23, 1 }, /* SME_i1: immediate field, bit 23. */
276 { 23, 1 }, /* SME_sz_23: bit [23]. */
277 { 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */
280 { 4, 1 }, /* SVE_M_4: Merge/zero select, bit 4. */
281 { 14, 1 }, /* SVE_M_14: Merge/zero select, bit 14. */
282 { 16, 1 }, /* SVE_M_16: Merge/zero select, bit 16. */
304 { 5, 1 }, /* SVE_i1: single-bit immediate. */
305 { 23, 1 }, /* SVE_i1_23: single-bit immediate. */
306 { 22, 2 }, /* SVE_i2: 2-bit index, bits [23,22]. */
307 { 20, 1 }, /* SVE_i2h: high bit of 2bit immediate, bits. */
308 { 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
309 { 19, 2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */
310 { 22, 2 }, /* SVE_i3h3: two high bits of 3bit immediate, bits [22,23]. */
311 { 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */
312 { 12, 1 }, /* SVE_i3l2: low bit of 3-bit immediate, bit 12. */
313 { 10, 2 }, /* SVE_i4l2: two low bits of 4bit immediate, bits [11,10]. */
314 { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
315 { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
316 { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
317 { 16, 5 }, /* SVE_imm5b: secondary 5-bit immediate field. */
318 { 16, 6 }, /* SVE_imm6: 6-bit immediate field. */
319 { 14, 7 }, /* SVE_imm7: 7-bit immediate field. */
320 { 5, 8 }, /* SVE_imm8: 8-bit immediate field. */
321 { 5, 9 }, /* SVE_imm9: 9-bit immediate field. */
324 { 10, 2 }, /* SVE_msz: 2-bit shift amount for ADR. */
327 { 16, 1 }, /* SVE_rot1: 1-bit rotation amount. */
328 { 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
329 { 10, 1 }, /* SVE_rot3: 1-bit rotation amount at bit 10. */
330 { 17, 2 }, /* SVE_size: 2-bit element size, bits [18,17]. */
331 { 22, 1 }, /* SVE_sz: 1-bit element size select. */
332 { 30, 1 }, /* SVE_sz2: 1-bit element size select. */
333 { 17, 1 }, /* SVE_sz3: 1-bit element size select. */
334 { 14, 1 }, /* SVE_sz4: 1-bit element size select. */
339 { 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */
340 { 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */
344 { 19, 5 }, /* b40: in the test bit and branch instructions. */
345 { 31, 1 }, /* b5: in the test bit and branch instructions. */
363 { 10, 2 }, /* imm2_10: 2-bit immediate, bits [11:10] */
364 { 12, 2 }, /* imm2_12: 2-bit immediate, bits [13:12] */
365 { 13, 2 }, /* imm2_13: 2-bit immediate, bits [14:13] */
366 { 15, 2 }, /* imm2_15: 2-bit immediate, bits [16:15] */
367 { 16, 2 }, /* imm2_16: 2-bit immediate, bits [17:16] */
368 { 19, 2 }, /* imm2_19: 2-bit immediate, bits [20:19] */
389 { 5, 14 }, /* imm14: in test bit and branch instructions. */
392 { 17, 1 }, /* imm17_1: in 1 bit element index. */
407 { 0, 4 }, /* nzcv: flag bit specifier, encoded in the "nzcv" field. */
423 { 22, 1 }, /* sz: 1-bit element size select. */
430 { 7, 1 }, /* ZAn_1: name of the 1bit encoded ZA tile. */
433 { 6, 2 }, /* ZAn_2: name of the 2bit encoded ZA tile. */
434 { 5, 3 }, /* ZAn_3: name of the 3bit encoded ZA tile. */
435 { 6, 1 }, /* ZAn: name of the bit encoded ZA tile. */
439 { 8, 1 }, /* ZA8_1: name of the 1 bit encoded ZA tile ZA0-ZA1. */
1181 IS32 indicates whether value is a 32-bit immediate or not.
1195 32-bit constant expressions like ~0x80000000 are
1382 /* Replicate to a full 64-bit value. */
1402 /* If 64-bit immediate IMM is in the format of
3070 /* The value is expected to be an 8-bit floating-point constant with
3071 sign, 3-bit exponent and normalized 4 bits of precision, encoded
3102 " 8-bit constants"));
3391 /* In the 64-bit form, the final register operand is written as Wm
3634 /* [0][0] 32-bit integer regs with sp Wn
3635 [0][1] 64-bit integer regs with sp Xn sf=1
3636 [1][0] 32-bit integer regs with #0 Wn
3637 [1][1] 64-bit integer regs with #0 Xn sf=1 */
3711 /* Types for expanding an encoded 8-bit value to a floating-point value. */
3731 /* IMM8 is an 8-bit floating-point constant with sign, 3-bit exponent and
3986 when it is not the special case of 8-bit load/store
5443 #define BIT(INSN,BT) (((INSN) >> (BT)) & 1)
5457 if (BIT (insn, 23))
5464 if (BIT (insn, 22))
Indexes created Mon Jun 08 00:24:58 UTC 2026