Lines Matching refs:opnd
959 dump_match_qualifiers (const struct aarch64_opnd_info *opnd,
967 curr[i] = opnd[i].qualifier;
1582 /* Check that indexed register operand OPND has a register in the range
1587 check_reglane (const aarch64_opnd_info *opnd,
1592 if (!value_in_range_p (opnd->reglane.regno, min_regno, max_regno))
1598 if (!value_in_range_p (opnd->reglane.index, min_index, max_index))
1607 /* Check that register list operand OPND has NUM_REGS registers and a
1611 check_reglist (const aarch64_opnd_info *opnd,
1615 if (opnd->reglist.num_regs != num_regs)
1620 if (opnd->reglist.stride != stride)
1677 /* Check that indexed ZA operand OPND has:
1690 check_za_access (const aarch64_opnd_info *opnd,
1695 if (!value_in_range_p (opnd->indexed_za.index.regno, min_wreg, min_wreg + 3))
1711 if (!value_in_range_p (opnd->indexed_za.index.imm, 0, max_index))
1717 if ((opnd->indexed_za.index.imm % range_size) != 0)
1727 if (opnd->indexed_za.index.countm1 != range_size - 1)
1745 if (opnd->indexed_za.group_size != group_size
1746 && (status_vg || opnd->indexed_za.group_size != 0 ))
1803 const aarch64_opnd_info *opnd = opnds + idx;
1804 aarch64_opnd_qualifier_t qualifier = opnd->qualifier;
1807 assert (opcode->operands[idx] == opnd->type && opnd->type == type);
1867 if (!aarch64_stack_pointer_p (opnd))
1891 if (!check_reglane (opnd, mismatch_detail, idx,
1899 if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31, 0, 1))
1906 if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31, 0, 3))
1911 size = aarch64_get_qualifier_esize (opnd->qualifier);
1912 if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31,
1918 size = aarch64_get_qualifier_esize (opnd->qualifier);
1919 if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31,
1927 if (!check_reglane (opnd, mismatch_detail, idx, "pn", 8, 15,
1948 if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31,
1965 if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 15,
1972 if (opnd->reg.regno > 15)
1980 size = aarch64_get_qualifier_esize (opnd->qualifier);
1982 if (!check_za_access (opnd, mismatch_detail, idx,
2004 if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
2006 if ((opnd->reglist.first_regno % num) != 0)
2019 if (!check_reglist (opnd, mismatch_detail, idx, num, 16 / num))
2021 num = 16 | (opnd->reglist.stride - 1);
2022 if ((opnd->reglist.first_regno & ~num) != 0)
2034 if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
2049 size = aarch64_get_qualifier_esize (opnd->qualifier);
2051 if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value, 1,
2058 if (!check_za_access (opnd, mismatch_detail, idx, 12, 15, 1,
2066 if (!check_za_access (opnd, mismatch_detail, idx, 8, 7, 1,
2073 if (!check_za_access (opnd
2080 if (!check_za_access (opnd, mismatch_detail, idx, 8, 3, 2,
2087 if (!check_za_access (opnd, mismatch_detail, idx, 8, 3, 4,
2094 if (!check_za_access (opnd, mismatch_detail, idx, 8, 7, 2,
2101 if (!check_za_access (opnd, mismatch_detail, idx, 12, 7, 2,
2108 if (!check_za_access (opnd, mismatch_detail, idx, 12, 3, 2,
2115 if (!check_za_access (opnd, mismatch_detail, idx, 12, 1, 2,
2122 if (!check_za_access (opnd, mismatch_detail, idx, 12, 0, 2,
2129 if (!check_za_access (opnd, mismatch_detail, idx, 12, 3, 4,
2136 if (!check_za_access (opnd, mismatch_detail, idx, 12, 1, 4,
2143 if (!check_za_access (opnd, mismatch_detail, idx, 12, 15, 1,
2151 if (!check_za_access (opnd, mismatch_detail, idx, 12, 0, 4,
2159 size = aarch64_get_qualifier_esize (opnd->qualifier);
2164 if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value, num,
2179 if (opnd->reg.regno < 8)
2187 if (opnd->reg.regno >= 8
2215 if (opnd->addr.writeback == 1)
2223 if (opnd->addr.writeback == 1 && opnd->addr.preind != 1)
2234 if (opnd->addr.writeback == 0)
2242 if (opnd->addr.writeback)
2244 && !opnd->addr.preind)
2246 && !opnd->addr.postind))
2255 assert (opnd->addr.writeback == 0);
2265 size = aarch64_get_qualifier_esize (opnd->qualifier);
2266 if (!value_in_range_p (opnd->addr.offset.imm, -64 * size, 63 * size))
2272 if (!value_aligned_p (opnd->addr.offset.imm, size))
2281 if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
2292 if ((value_in_range_p (opnd->addr.offset.imm, 0, 255)
2293 && !value_aligned_p (opnd->addr.offset.imm, size))
2294 || value_in_range_p (opnd->addr.offset.imm, -256, -1))
2302 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4088))
2307 if (!value_aligned_p (opnd->addr.offset.imm, 8))
2316 if (!value_in_range_p (opnd->addr.offset.imm, -1024, 1008))
2322 if (!value_aligned_p (opnd->addr.offset.imm, 16))
2331 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4080))
2337 if (!value_aligned_p (opnd->addr.offset.imm, 16))
2347 if (opnd->addr.offset.is_reg)
2349 if (value_in_range_p (opnd->addr.offset.regno, 0, 30))
2373 if ((int) num_bytes != opnd->addr.offset.imm)
2386 size = aarch64_get_qualifier_esize (opnd->qualifier);
2388 if (opnd->shifter.amount != 0
2389 && opnd->shifter.amount != (int)get_logsz (size))
2397 switch (opnd->shifter.kind)
2411 imm = opnd->addr.offset.imm;
2416 if (!value_in_range_p (opnd->addr.offset.imm, 0, 4095 * size))
2422 if (!value_aligned_p (opnd->addr.offset.imm, size))
2435 imm = opnd->imm.value;
2456 if (!value_in_range_p (opnd->addr.offset.imm, 0, 15))
2470 assert (!opnd->addr.offset.is_reg);
2471 assert (opnd->addr.preind);
2475 if ((opnd->addr.offset.imm != 0 && !opnd->shifter.operator_present)
2476 || (opnd->shifter.operator_present
2477 && opnd->shifter.kind != AARCH64_MOD_MUL_VL))
2483 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
2489 if (!value_aligned_p (opnd->addr.offset.imm, num))
2513 assert (!opnd->addr.offset.is_reg);
2514 assert (opnd->addr.preind);
2518 if (opnd->shifter.operator_present
2519 || opnd->shifter.amount_present)
2525 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
2531 if (!value_aligned_p (opnd->addr.offset.imm, num))
2548 assert (opnd->addr.offset.is_reg);
2549 assert (opnd->addr.preind);
2551 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
2552 assert (opnd->shifter.operator_present == 0);
2576 assert (opnd->addr.offset.is_reg);
2577 assert (opnd->addr.preind);
2579 && opnd->addr.offset.regno == 31)
2585 if (((1 << opnd->shifter.kind) & modifiers) == 0
2586 || (opnd->shifter.amount
2617 assert (opnd->addr.offset.is_reg);
2618 assert (opnd->addr.preind);
2619 if (((1 << opnd->shifter.kind) & modifiers) == 0
2620 || opnd->shifter.amount < 0
2621 || opnd->shifter.amount > 3)
2645 ? opnd->addr.offset.imm * -1
2646 : opnd->addr.offset.imm;
2648 && opnd->addr.offset.imm != 0)
2658 if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
2674 if (!value_in_range_p (opnd->reglist.index, 0, num))
2686 if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
2693 if (num != 1 && !check_reglist (opnd, mismatch_detail, idx, num, 1))
2701 if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
2707 if (opnd->reglist.stride != 1)
2716 imm = opnd->imm.value;
2731 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2737 if (opnd->shifter.amount != 0 && opnd->shifter.amount != 12)
2743 if (!value_fit_unsigned_field_p (opnd->imm.value, 12))
2753 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2760 if (!value_aligned_p (opnd->shifter.amount, 16))
2766 if (!value_in_range_p (opnd->shifter.amount, 0, size * 8 - 16))
2772 if (opnd->imm.value < 0)
2778 if (!value_fit_unsigned_field_p (opnd->imm.value, 16))
2789 imm = opnd->imm.value;
2837 if (!value_fit_unsigned_field_p (opnd->imm.value, size))
2847 if (!value_in_range_p (opnd->imm.value, 0, 1008))
2853 if (!value_aligned_p (opnd->imm.value, 16))
2868 if (!value_fit_signed_field_p (opnd->imm.value, size))
2881 if (opnd->imm.value + opnds[idx-1].imm.value > size)
2894 uint64_t uimm = opnd->imm.value;
2908 if (opnd->imm.value != 0)
2919 if (opnd->imm.value != 0
2920 && opnd->imm.value != 90
2921 && opnd->imm.value != 180
2922 && opnd->imm.value != 270)
2933 if (opnd->imm.value != 90 && opnd->imm.value != 270)
2944 if (opnd->imm.value != size)
2954 if (!value_in_range_p (opnd->imm.value, 0, size * 8 - 1))
2964 if (!value_in_range_p (opnd->imm.value, 1, size * 8))
2977 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2985 if (opnd->shifter.kind != AARCH64_MOD_MSL)
2993 if (opnd->shifter.kind != AARCH64_MOD_NONE)
3009 if (!value_in_range_p (opnd->imm.value, -128, 255))
3015 else if (aarch64_shrink_expanded_imm8 (opnd->imm.value) < 0)
3025 switch (opnd->shifter.kind)
3029 if (!value_in_range_p (opnd->shifter.amount, 0, (size - 1) * 8))
3035 if (!value_aligned_p (opnd->shifter.amount, 8))
3043 if (opnd->shifter.amount != 8 && opnd->shifter.amount != 16)
3051 if (opnd->shifter.kind != AARCH64_MOD_NONE)
3064 if (opnd->imm.is_fp == 0)
3074 if (!value_in_range_p (opnd->imm.value, 0, 255))
3080 if (opnd->shifter.kind != AARCH64_MOD_NONE)
3091 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
3094 uvalue = opnd->imm.value;
3095 shift = opnd->shifter.amount;
3141 assert (opnd->imm.is_fp);
3142 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x3f800000)
3151 assert (opnd->imm.is_fp);
3152 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x40000000)
3161 assert (opnd->imm.is_fp);
3162 if (opnd->imm.value != 0 && opnd->imm.value != 0x3f800000)
3173 uint64_t uimm = ~opnd->imm.value;
3186 uint64_t uimm = opnd->imm.value;
3203 assert (opnd->shifter.kind == AARCH64_MOD_MUL);
3204 if (!value_in_range_p (opnd->shifter.amount, 1, 16))
3215 if (!value_in_range_p (opnd->imm.value, 0, 8 * size - 1))
3225 if (!value_in_range_p (opnd
3238 if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
3246 if (!value_in_range_p (opnd->imm.value, 0, 56))
3251 if (opnd->imm.value % 8 != 0)
3260 if (!value_in_range_p (opnd->imm.value, 0, 3))
3277 if (aarch64_pstatefields[i].value == opnd->pstatefield)
3289 if (opcode->iclass == ldst_regoff && opnd->prfop->value >= 24)
3312 if (!check_reglane (opnd, mismatch_detail, idx, "v", 0, 31,
3323 if (!value_in_range_p (opnd->reglane.index, 0, num))
3339 && !value_in_range_p (opnd->reglane.regno, 0, 15))
3345 && !value_in_range_p (opnd->reglane.regno, 0, 7))
3357 if (!aarch64_extend_operator_p (opnd->shifter.kind)
3358 && opnd->shifter.kind != AARCH64_MOD_LSL)
3371 if (!opnd->shifter.operator_present)
3377 else if (opnd->shifter.kind == AARCH64_MOD_LSL)
3384 assert (opnd->shifter.operator_present /* Default to LSL. */
3385 || opnd->shifter.kind == AARCH64_MOD_LSL);
3386 if (!value_in_range_p (opnd->shifter.amount, 0, 4))
3397 && opnd->shifter.kind != AARCH64_MOD_LSL
3398 && opnd->shifter.kind != AARCH64_MOD_UXTX
3399 && opnd->shifter.kind != AARCH64_MOD_SXTX)
3409 if (!aarch64_shift_operator_p (opnd->shifter.kind))
3415 if (opnd->shifter.kind == AARCH64_MOD_ROR
3423 if (!value_in_range_p (opnd->shifter.amount, 0, num))
3431 /* We expect here that opnd->shifter.kind != AARCH64_MOD_LSL
3434 if (!value_in_range_p (opnd->shifter.amount, 0, 7))
3679 /* Get the name of the integer offset register in OPND, using the shift type
3683 get_offset_int_reg_name (const aarch64_opnd_info *opnd)
3685 switch (opnd->shifter.kind)
3689 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_W, 0);
3693 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_X, 0);
3700 /* Get the name of the SVE vector offset register in OPND, using the operand
3835 /* Produce the string representation of the register list operand *OPND
3839 print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
3843 const int num_regs = opnd->reglist.num_regs;
3844 const int stride = opnd->reglist.stride;
3845 const int first_reg = opnd->reglist.first_regno;
3847 const char *qlf_name = aarch64_get_qualifier_name (opnd->qualifier);
3850 assert (opnd->type != AARCH64_OPND_LEt || opnd->reglist.has_index);
3854 if (opnd->reglist.has_index)
3857 style_imm (styler, "%" PRIi64, (opnd->reglist.index % 100)));
3865 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3912 /* Print the register+immediate address in OPND to BUF, which has SIZE
3917 const aarch64_opnd_info *opnd,
3921 if (opnd->addr.writeback)
3923 if (opnd->addr.preind)
3925 if (opnd->type == AARCH64_OPND_ADDR_SIMM10 && !opnd->addr.offset.imm)
3930 style_imm (styler, "#%d", opnd->addr.offset.imm));
3935 style_imm (styler, "#%d", opnd->addr.offset.imm));
3939 if (opnd->shifter.operator_present)
3941 assert (opnd->shifter.kind == AARCH64_MOD_MUL_VL);
3944 style_imm (styler, "#%d", opnd->addr.offset.imm),
3947 else if (opnd->addr.offset.imm)
3950 style_imm (styler, "#%d", opnd->addr.offset.imm));
3957 *OPND in the buffer pointed by BUF of size SIZE. BASE and OFFSET are
3961 const aarch64_opnd_info *opnd,
3968 const char *shift_name = aarch64_operand_modifiers[opnd->shifter.kind].name;
3972 if (opnd->type == AARCH64_OPND_SVE_ADDR_ZX && offset != NULL
3982 if (!opnd->shifter.amount && (opnd->qualifier != AARCH64_OPND_QLF_S_B
3983 || !opnd->shifter.amount_present))
3991 if (opnd->shifter.kind == AARCH64_MOD_LSL)
4004 (opnd->shifter.amount % 100)));
4080 const aarch64_opnd_info *opnd = opnds + idx;
4096 switch (opnd->type)
4114 the <ic_op>, therefore we use opnd->present to override the
4116 if (opnd->type == AARCH64_OPND_Rt_SYS)
4118 if (!opnd->present)
4121 else if ((opnd->type == AARCH64_OPND_Rt_IN_SYS_ALIASES)
4122 && (opnd->reg.regno
4127 snprintf (comment, comment_size, "unpredictable encoding (Rt!=31): #%u", opnd->reg.regno);
4132 && (opnd->reg.regno
4135 assert (opnd->qualifier == AARCH64_OPND_QLF_W
4136 || opnd->qualifier == AARCH64_OPND_QLF_X);
4138 style_reg (styler, get_int_reg_name (opnd->reg.regno,
4139 opnd->qualifier, 0)));
4147 assert (opnd->qualifier == AARCH64_OPND_QLF_W
4148 || opnd->qualifier == AARCH64_OPND_QLF_WSP
4149 || opnd->qualifier == AARCH64_OPND_QLF_X
4150 || opnd->qualifier == AARCH64_OPND_QLF_SP);
4152 style_reg (styler, get_int_reg_name (opnd->reg.regno,
4153 opnd->qualifier, 1)));
4157 kind = opnd->shifter.kind;
4161 && ((opnd->qualifier == AARCH64_OPND_QLF_W
4164 || (opnd->qualifier == AARCH64_OPND_QLF_X
4169 if (opnd->shifter.amount == 0)
4174 get_int_reg_name (opnd->reg.regno,
4175 opnd->qualifier, 0)));
4179 if (opnd->shifter.amount)
4181 style_reg (styler, get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0)),
4183 style_imm (styler, "#%" PRIi64, opnd->shifter.amount));
4186 style_reg (styler, get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0)),
4191 assert (opnd->qualifier == AARCH64_OPND_QLF_W
4192 || opnd->qualifier == AARCH64_OPND_QLF_X);
4193 if (opnd->shifter.amount == 0 && opnd->shifter.kind == AARCH64_MOD_LSL)
4195 style_reg (styler, get_int_reg_name (opnd->reg.regno,
4196 opnd->qualifier, 0)));
4199 style_reg (styler, get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0)),
4200 style_sub_mnem (styler, aarch64_operand_modifiers[opnd->shifter.kind].name),
4201 style_imm (styler, "#%" PRIi64, opnd->shifter.amount));
4205 assert (opnd->qualifier == AARCH64_OPND_QLF_X);
4206 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
4207 if (opnd->shifter.amount == 0)
4209 style_reg (styler, get_int_reg_name (opnd->reg.regno,
4210 opnd->qualifier, 0)));
4213 style_reg (styler, get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0)),
4214 style_sub_mnem (styler, aarch64_operand_modifiers[opnd->shifter.kind].name),
4215 style_imm (styler, "#%" PRIi64, opnd->shifter.amount));
4233 aarch64_get_qualifier_name (opnd->qualifier),
4234 opnd->reg.regno));
4242 style_reg (styler, "v%d.%s", opnd->reg.regno,
4243 aarch64_get_qualifier_name (opnd->qualifier)));
4253 style_reg (styler, "v%d.%s", opnd->reglane.regno,
4254 aarch64_get_qualifier_name (opnd->qualifier)),
4255 style_imm (styler, "%" PRIi64, opnd->reglane.index));
4262 style_reg (styler, "v%d", opnd->reglane.regno),
4263 style_imm (styler, "%" PRIi64, opnd->reglane.index));
4269 style_reg (styler, "v%d.d", opnd->reg.regno),
4278 print_register_list (buf, size, opnd, "v", styler);
4290 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
4292 style_reg (styler, "p%d", opnd->reg.regno));
4293 else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z
4294 || opnd->qualifier == AARCH64_OPND_QLF_P_M)
4296 style_reg (styler, "p%d/%s", opnd->reg.regno,
4297 aarch64_get_qualifier_name (opnd->qualifier)));
4300 style_reg (styler, "p%d.%s", opnd->reg.regno,
4301 aarch64_get_qualifier_name (opnd->qualifier)));
4311 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
4313 style_reg (styler, "pn%d", opnd->reg.regno));
4314 else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z
4315 || opnd->qualifier == AARCH64_OPND_QLF_P_M)
4317 style_reg (styler, "pn%d/%s", opnd->reg.regno,
4318 aarch64_get_qualifier_name (opnd->qualifier)));
4321 style_reg (styler, "pn%d.%s", opnd->reg.regno,
4322 aarch64_get_qualifier_name (opnd->qualifier)));
4327 print_register_list (buf, size, opnd, "p", styler);
4333 style_reg (styler, "pn%d", opnd->reglane.regno),
4334 style_imm (styler, "%" PRIi64, opnd->reglane.index));
4346 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
4347 snprintf (buf, size, "%s", style_reg (styler, "z%d", opnd->reg.regno));
4350 style_reg (styler, "z%d.%s", opnd->reg.regno,
4351 aarch64_get_qualifier_name (opnd->qualifier)));
4365 print_register_list (buf, size, opnd, "z", styler);
4399 (opnd->qualifier == AARCH64_OPND_QLF_NIL
4400 ? style_reg (styler, "z%d", opnd->reglane.regno)
4401 : style_reg (styler, "z%d.%s", opnd->reglane.regno,
4402 aarch64_get_qualifier_name (opnd->qualifier))),
4403 style_imm (styler, "%" PRIi64, opnd->reglane.index));
4414 if (opnd->reglane.index == 0)
4415 snprintf (buf, size, "%s", style_reg (styler, "z%d", opnd->reg.regno));
4418 style_reg (styler, "z%d", opnd->reglane.regno),
4419 style_imm (styler, "%" PRIi64, opnd->reglane.index));
4426 style_reg (styler, "za%d.%s", opnd->reg.regno,
4427 aarch64_get_qualifier_name (opnd->qualifier)));
4436 opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "{" : "",
4438 opnd->indexed_za.regno,
4439 opnd->indexed_za.v == 1 ? 'v' : 'h',
4440 aarch64_get_qualifier_name (opnd->qualifier)),
4441 style_reg (styler, "w%d", opnd->indexed_za.index.regno),
4442 style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm),
4443 opnd->indexed_za.index.countm1 ? ":" : "",
4444 (opnd->indexed_za.index.countm1
4446 opnd->indexed_za.index.imm
4447 + opnd->indexed_za.index.countm1)
4449 opnd->indexed_za.group_size ? ", " : "",
4450 opnd->indexed_za.group_size == 2
4452 : opnd->indexed_za.group_size == 4
4454 opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "}" : "");
4458 print_sme_za_list (buf, size, opnd->imm.value, styler);
4470 opnd->qualifier == AARCH64_OPND_QLF_NIL ? "" : ".",
4471 (opnd->qualifier == AARCH64_OPND_QLF_NIL
4473 : aarch64_get_qualifier_name (opnd->qualifier))),
4474 style_reg (styler, "w%d", opnd->indexed_za.index.regno),
4475 style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm),
4476 opnd->indexed_za.index.countm1 ? ":" : "",
4477 (opnd->indexed_za.index.countm1
4479 opnd->indexed_za.index.imm
4480 + opnd->indexed_za.index.countm1)
4482 opnd->indexed_za.group_size ? ", " : "",
4483 opnd->indexed_za.group_size == 2
4485 : opnd->indexed_za.group_size == 4
4500 opnd->indexed_za.regno,
4501 opnd->indexed_za.v ? 'v': 'h',
4502 opnd->qualifier == AARCH64_OPND_QLF_NIL ? "" : ".",
4503 (opnd->qualifier == AARCH64_OPND_QLF_NIL
4505 : aarch64_get_qualifier_name (opnd->qualifier))),
4506 style_reg (styler, "w%d", opnd->indexed_za.index.regno),
4507 style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm),
4508 opnd->indexed_za.index.countm1 ? ":" : "",
4509 opnd->indexed_za.index.countm1 ? style_imm (styler, "%d",
4510 opnd->indexed_za.index.imm
4511 + opnd->indexed_za.index.countm1):"");
4516 style_reg (styler, opnd->reg.regno == 's' ? "sm" : "za"));
4521 style_reg (styler, "p%d.%s", opnd->indexed_za.regno,
4522 aarch64_get_qualifier_name (opnd->qualifier)),
4523 style_reg (styler, "w%d", opnd->indexed_za.index.regno),
4524 style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm));
4529 enum_value = opnd->imm.value;
4536 enum_value = opnd->imm.value;
4545 style_reg (styler, "C%" PRIi64, opnd->imm.value));
4592 style_imm (styler, "#%" PRIi64, opnd->imm.value));
4600 c.i = opnd->imm.value;
4607 && opnd->imm.value == get_optional_operand_default_value (opcode))
4609 enum_value = opnd->imm.value;
4616 style_imm (styler, "#%" PRIi64, opnd->imm.value));
4621 && !opnd->shifter.operator_present
4622 && opnd->imm.value == get_optional_operand_default_value (opcode))
4624 enum_value = opnd->imm.value;
4626 if (aarch64_sve_pattern_array[opnd->imm.value])
4629 aarch64_sve_pattern_array[opnd->imm.value]));
4632 style_imm (styler, "#%" PRIi64, opnd->imm.value));
4633 if (opnd->shifter.operator_present)
4637 = aarch64_operand_modifiers[opnd->shifter.kind].name;
4640 style_imm (styler, "#%" PRIi64, opnd->shifter.amount));
4645 enum_value = opnd->imm.value;
4652 style_imm (styler, "#%" PRIi64, opnd->imm.value));
4660 int imm32 = opnd->imm.value;
4668 opnd->imm.value));
4669 snprintf (comment, comment_size, "#%" PRIi64, opnd->imm.value);
4687 if (opnd->shifter.amount)
4689 style_imm (styler, "#0x%" PRIx64, opnd->imm.value),
4691 style_imm (styler, "#%" PRIi64, opnd->shifter.amount));
4694 style_imm (styler, "#0x%" PRIx64, opnd->imm.value));
4699 if ((! opnd->shifter.amount && opnd->shifter.kind == AARCH64_MOD_LSL)
4700 || opnd->shifter.kind == AARCH64_MOD_NONE)
4702 style_imm (styler, "#0x%" PRIx64, opnd->imm.value));
4705 style_imm (styler, "#0x%" PRIx64, opnd->imm.value),
4706 style_sub_mnem (styler, aarch64_operand_modifiers[opnd->shifter.kind].name),
4707 style_imm (styler, "#%" PRIi64, opnd->shifter.amount));
4712 if (opnd->shifter.amount)
4714 style_imm (styler, "#%" PRIi64, opnd->imm.value),
4716 style_imm (styler, "#%" PRIi64, opnd->shifter.amount));
4719 style_imm (styler, "#%" PRIi64, opnd->imm.value));
4730 c.i = expand_fp_imm (2, opnd->imm.value);
4737 c.i = expand_fp_imm (4, opnd->imm.value);
4744 c.i = expand_fp_imm (8, opnd->imm.value);
4762 && (opnd->imm.value ==
4767 style_imm (styler, "#0x%x", (unsigned int) opnd->imm.value));
4773 style_sub_mnem (styler, opnd->cond->names[0]));
4774 num_conds = ARRAY_SIZE (opnd->cond->names);
4775 for (i = 1; i < num_conds && opnd->cond->names[i]; ++i)
4780 opnd->cond->names[0], opnd->cond->names[i]);
4783 opnd->cond->names[i]);
4789 + opnd->imm.value;
4806 addr = pc + AARCH64_PCREL_OFFSET + opnd->imm.value;
4821 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
4822 if (opnd->type == AARCH64_OPND_SIMD_ADDR_POST)
4824 if (opnd->addr.offset.is_reg)
4827 style_reg (styler, "x%d", opnd->addr.offset.regno));
4831 style_imm (styler, "#%d", opnd->addr.offset.imm));
4854 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
4855 get_offset_int_reg_name (opnd), styler);
4860 (buf, size, opnd,
4861 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
4862 get_64bit_int_reg_name (opnd->addr.offset.regno, 0), styler);
4878 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
4879 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier),
4909 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
4918 (buf, size, opnd,
4919 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
4927 (buf, size, opnd,
4928 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
4929 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier),
4934 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
4935 if (opnd->addr.offset.imm)
4938 style_imm (styler, "#%d", opnd->addr.offset.imm));
4951 || (sr->flags & opnd->sysreg.flags) == opnd->sysreg.flags)
4956 if (aarch64_sys_regs[i].value == opnd->sysreg.value
4985 unsigned int value = opnd->sysreg.value;
4996 if (aarch64_pstatefields[i].value == opnd->pstatefield)
5002 && (PSTATE_DECODE_CRM (opnd->sysreg.flags)
5018 snprintf (buf, size, "%s", style_reg (styler, opnd->sysins_op->name));
5024 if (opnd->barrier->name[0] == '#')
5025 snprintf (buf, size, "%s", style_imm (styler, opnd->barrier->name));
5028 style_sub_mnem (styler, opnd->barrier->name));
5035 || (opnd->barrier->value
5038 style_imm (styler, "#0x%x", opnd->barrier->value));
5042 if ((opnd->prfop->name == NULL)
5043 || (opcode->iclass != ldst_pos && opnd->prfop->value == 0x18))
5045 style_imm (styler, "#0x%02x", opnd->prfop->value));
5047 snprintf (buf, size, "%s", style_sub_mnem (styler, opnd->prfop->name));
5051 enum_value = opnd->imm.value;
5058 style_imm (styler, "#%" PRIi64, opnd->imm.value));
5075 style_imm (styler, "%d", (int) opnd->imm.value));
5079 style_imm (styler, "%d", (int) opnd->imm.value),
5092 if ((HINT_FLAG (opnd->hint_option->value) & HINT_OPD_F_NOPRINT) == 0)
5094 style_sub_mnem (styler, opnd->hint_option->name));
5098 snprintf (buf, size, "%s", style_sub_mnem (styler, opnd->hint_option->name));
5105 get_int_reg_name (opnd->reg.regno,
5111 style_reg (styler, get_int_reg_name (opnd->reg.regno,
Indexes created Thu May 07 00:24:58 UTC 2026