Lines Matching defs:prev_insn
2347 unsigned int prev_insn = 0;
2363 prev_insn = bfd_get_16 (abfd, contents + i - 2);
2369 if (dsp && (prev_insn & 0xfc00) == 0xf800)
2372 /* Check if prev_insn is actually the field b of a parallel
2382 prev_op = sh_insn_info (prev_insn);
2385 prev_op = sh_insn_info (prev_insn);
2397 && ! sh_insns_conflict (prev_insn, prev_op, insn, op))
2402 there is a previous instruction; PREV_INSN is not
2403 itself a load/store instruction, and PREV_INSN and
2416 /* If the instruction before PREV_INSN has a delay
2417 slot--that is, PREV_INSN is in a delay slot--we
2423 /* If the instruction before PREV_INSN is a load,
2425 putting INSN immediately after PREV_INSN will
2467 /* If PREV_INSN is a load, and it sets a register
2469 immediately after PREV_INSN will cause a pipeline
2473 && sh_load_use (prev_insn, prev_op, next_insn, next_op))
Indexes created Sun Jul 19 00:25:04 UTC 2026