Lines Matching refs:qualifier
809 to a corresponding operand qualifier. */
863 qualifier for the vector type. The operand qualifiers are regular
926 /* Return the operand qualifier associated with all uses of REG, or
968 entry on success, setting *QUALIFIER to the register qualifier.
975 aarch64_opnd_qualifier_t *qualifier)
992 *qualifier = AARCH64_OPND_QLF_S_S;
995 *qualifier = AARCH64_OPND_QLF_S_D;
1006 *qualifier = inherent_reg_qualifier (reg);
1016 on success, setting *QUALIFIER to the register qualifier. Return null
1022 aarch64_reg_parse_32_64 (char **ccp, aarch64_opnd_qualifier_t *qualifier)
1024 return aarch64_addr_reg_parse (ccp, REG_TYPE_R_ZR_SP, qualifier);
1027 /* Parse the qualifier of a vector register or vector element of type
2720 return (operand->qualifier == AARCH64_OPND_QLF_NIL
2721 || aarch64_get_qualifier_esize (operand->qualifier) == 8);
3822 aarch64_opnd_qualifier_t qualifier;
3826 reg = aarch64_reg_parse_32_64 (str, &qualifier);
3842 operand->qualifier = qualifier;
3868 aarch64_opnd_qualifier_t qualifier;
3869 const reg_entry *reg = aarch64_reg_parse_32_64 (str, &qualifier);
3880 operand->qualifier = qualifier;
4429 operand->qualifier = AARCH64_OPND_QLF_X;
4651 /* Parse STR for reg of REG_TYPE and following '.' and QUALIFIER.
4652 Function returns REG_ENTRY struct and QUALIFIER [bhsdq] or NULL
4655 REG_TYPE.QUALIFIER
4663 aarch64_opnd_qualifier_t *qualifier, unsigned int flags)
4672 *qualifier = AARCH64_OPND_QLF_NIL;
4675 *qualifier = vectype_to_qualifier (&vectype);
4676 if (*qualifier == AARCH64_OPND_QLF_NIL)
4794 qualifier and that is indexed by two values: a 32-bit register,
4799 the operand and setting QUALIFIER to the register qualifier.
4813 aarch64_opnd_qualifier_t *qualifier,
4816 const reg_entry *reg = parse_reg_with_qual (str, reg_type, qualifier, flags);
4832 aarch64_opnd_qualifier_t *qualifier)
4840 if (!parse_dual_indexed_reg (str, REG_TYPE_ZATHV, opnd, qualifier,
4867 aarch64_opnd_qualifier_t qualifier;
4875 &qualifier, ptr_flags);
4881 if (qualifier != AARCH64_OPND_QLF_NIL)
4892 if (qualifier == AARCH64_OPND_QLF_S_B)
4897 else if (qualifier == AARCH64_OPND_QLF_S_H)
4899 qualifier == AARCH64_OPND_QLF_S_S)
4901 else if (qualifier == AARCH64_OPND_QLF_S_D)
4903 else if (qualifier == AARCH64_OPND_QLF_S_Q)
4909 else if (qualifier == AARCH64_OPND_QLF_NIL)
5142 info->qualifier = inherent_reg_qualifier (reg); \
5600 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
5602 Return -1 if there is no qualifier sequence; return the first match
5630 DEBUG_TRACE_IF (i == 0, "empty list of qualifier sequence");
5635 if (*qualifiers == instr->operands[j].qualifier)
5649 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
5660 instr->operands[i].qualifier = *qualifiers;
5915 2) manipulating the IR, e.g. replacing the operand qualifier;
5955 /* Find the most matched qualifier sequence. */
5979 First NIL qualifier indicates the end in the list. */
6500 is32 = inst.base.operands[0].qualifier == AARCH64_OPND_QLF_W ? 1 : 0;
6600 enum aarch64_opnd_qualifier opd0_qlf = inst.base.operands[0].qualifier;
6601 enum aarch64_opnd_qualifier opd1_qlf = inst.base.operands[1].qualifier;
6671 (_("relocation qualifier does not match instruction size"));
6765 aarch64_opnd_qualifier_t qualifier, base_qualifier, offset_qualifier;
6942 contexts. Rely on F_STRICT qualifier checking to catch
6944 info->qualifier = AARCH64_OPND_QLF_NIL;
6947 info->qualifier = vectype_to_qualifier (&vectype);
6948 if (info->qualifier == AARCH64_OPND_QLF_NIL)
6969 info->qualifier = AARCH64_OPND_QLF_S_D;
7036 info->qualifier = AARCH64_OPND_QLF_NIL;
7041 info->qualifier = vectype_to_qualifier (&vectype);
7042 if (info->qualifier == AARCH64_OPND_QLF_NIL)
7062 info->qualifier = AARCH64_OPND_QLF_NIL;
7171 info->qualifier = vectype_to_qualifier (&vectype);
7172 if (info->qualifier == AARCH64_OPND_QLF_NIL)
7204 info->qualifier = AARCH64_OPND_QLF_CR;
7749 /* Qualifier to be deduced by libopcodes. */
7855 /* Leave qualifier to be determined by libopcodes. */
7877 /* No qualifier. */
7892 &info->indexed_za, &qualifier, 0))
7894 info->qualifier = qualifier;
8019 info->qualifier = offset_qualifier;
8037 info->qualifier = base_qualifier;
8062 info->qualifier = base_qualifier;
8076 the qualifier checking routines. */
8086 info->qualifier = base_qualifier;
8345 info->qualifier = AARCH64_OPND_QLF_NIL;
8347 info->qualifier = vectype_to_qualifier (&vectype);
8369 reg = parse_reg_with_qual (&str, REG_TYPE_ZAT, &qualifier, 0);
8373 info->qualifier = qualifier;
8384 &qualifier)
8386 &info->indexed_za, &qualifier, 0))
8388 info->qualifier = qualifier;
8406 &info->indexed_za, &qualifier, 0))
8408 info->qualifier = qualifier;
8421 &info->indexed_za, &qualifier, 0))
8423 info->qualifier = qualifier;
8581 if (operands[0].qualifier == AARCH64_OPND_QLF_W)
8589 operands[0].qualifier = AARCH64_OPND_QLF_X;
8602 int size = aarch64_get_qualifier_esize (operands[0].qualifier);
8633 && operands[1].qualifier == AARCH64_OPND_QLF_W
8634 && operands[0].qualifier == AARCH64_OPND_QLF_X)
8635 operands[0].qualifier = AARCH64_OPND_QLF_W;
8649 if (operands[0].qualifier == AARCH64_OPND_QLF_X
8650 && operands[idx].qualifier == AARCH64_OPND_QLF_X
8654 operands[idx].qualifier = AARCH64_OPND_QLF_W;
9109 like ZA0H, supporting qualifier suffixes and indexing. */
9532 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
9533 qualifier matching may fail because the out-of-date qualifier will
9534 prevent the operand being updated with a new and correct qualifier. */
9538 instr->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
Indexes created Thu May 14 00:25:00 UTC 2026