Lines Matching defs:Rm
2409 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
5530 <Rm>
5531 <Rm>, <shift>
5731 <Rm>
5732 <Rm>, <shift>
5814 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5815 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5823 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5824 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
6750 Case 13: VMOV <Sd>, <Rm> */
6780 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6826 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
9257 the same instruction but with REG_PC in the Rm field. */
9344 BLX{<condition>} <Rm> ie BLX(2)
9598 unsigned Rd, Rn, Rm;
9603 Rm = inst.operands[2].reg;
9607 constraint ((Rm == REG_PC), BAD_PC);
9611 inst.instruction |= Rm << 8;
9752 strex rN, rM, foo
9755 strex rN, rM, rX
9883 as_tsktsk (_("Rd and Rm should be different in mla"));
10100 "{C|S}PSR_<field>, Rm",
10133 as_tsktsk (_("Rd and Rm should be different in mul"));
10137 UMULL RdLo, RdHi, Rm, Rs
10138 SMULL RdLo, RdHi, Rm, Rs
10139 UMLAL RdLo, RdHi, Rm, Rs
10140 SMLAL RdLo, RdHi, Rm, Rs. */
10154 /* rdhi, rdlo and rm must all be different before armv6. */
10158 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10176 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10178 Error if Rd, Rn or Rm are R15. */
10198 into pkhbt rd, rm, rn. */
10341 unsigned int Rm = (inst.operands[1].present
10346 inst.instruction |= Rm;
10347 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
10402 SMLAxy{cond} Rd,Rm,Rs,Rn
10403 SMLAWy{cond} Rd,Rm,Rs,Rn
10416 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10433 SMULxy{cond} Rd,Rm,Rs
10552 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10567 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
11063 MIAcc acc0,Rm,Rs
11064 MIAPHcc acc0,Rm,Rs
11065 MIAxycc acc0,Rm,Rs. */
11851 the same instruction but with REG_PC in the Rm field. */
11893 BLX <Rm> which is BLX(2)
12053 int Rm;
12056 Rm = inst.operands[0].reg;
12057 reject_bad_reg (Rm);
12058 inst.instruction |= Rm << 16;
12065 unsigned Rm;
12068 Rm = inst.operands[1].reg;
12071 reject_bad_reg (Rm);
12074 inst.instruction |= Rm << 16;
12075 inst.instruction |= Rm;
12082 unsigned Rd, Rn, Rm;
12095 Rm = inst.operands[2].reg;
12098 constraint (Rm == REG_SP, BAD_SP);
12109 Rm = Rn;
12118 Rm = REG_PC;
12128 inst.instruction |= Rm;
12211 unsigned Rd, Rn, Rm;
12216 Rm = inst.operands[2].reg;
12220 reject_bad_reg (Rm);
12224 inst.instruction |= Rm;
12634 /* Only [Rn,Rm] is acceptable. */
12742 unsigned Rd, Rn, Rm, Ra;
12746 Rm = inst.operands[2].reg;
12751 reject_bad_reg (Rm);
12756 inst.instruction |= Rm;
12763 unsigned RdLo, RdHi, Rn, Rm;
12768 Rm = inst.operands[3].reg;
12773 reject_bad_reg (Rm);
12778 inst.instruction |= Rm;
12784 unsigned Rn, Rm;
12787 Rm = inst.operands[1].reg;
12800 low_regs = (Rn <= 7 && Rm <= 7);
12814 && Rm == REG_LR)
12825 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12827 warn_deprecated_sp (Rm);
12828 /* R15 was documented as a valid choice for Rm in ARMv6,
12831 constraint (Rm == REG_PC, BAD_PC);
12834 reject_bad_reg (Rm);
12844 reject_bad_reg (Rm);
12850 && (Rm == REG_SP || Rm == REG_PC))
12854 "register."), Rm, Rn);
12861 constraint (Rm == REG_PC, BAD_PC);
12863 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
12920 if (Rn != Rm)
12953 inst.instruction |= Rm << 16;
12985 inst.instruction |= Rm << 3;
13013 inst.instruction |= Rm << 3;
13021 inst.instruction |= Rm << 3;
13029 inst.instruction |= Rm << 3;
13036 inst.instruction |= Rm << 3;
13051 if (Rn < 8 && Rm < 8)
13061 inst.instruction |= Rm << 3;
13117 unsigned Rn, Rm;
13120 Rm = inst.operands[1].reg;
13127 reject_bad_reg (Rm);
13138 || Rn > 7 || Rm > 7)
13165 inst.instruction |= Rm << 3;
13185 constraint (Rn > 7 || Rm > 7,
13190 inst.instruction |= Rm << 3;
13293 unsigned Rd, Rn, Rm;
13300 Rm = inst.operands[2].reg;
13306 && Rd != Rm)
13308 || Rm > 7)
13318 constraint (Rn > 7 || Rm > 7,
13330 inst.instruction |= Rm << 3;
13331 else if (Rd == Rm)
13344 inst.instruction |= Rm << 0;
13348 reject_bad_reg (Rm);
13355 unsigned RdLo, RdHi, Rn, Rm;
13360 Rm = inst.operands[3].reg;
13365 reject_bad_reg (Rm);
13370 inst.instruction |= Rm;
13472 unsigned Rm;
13474 Rm = inst.operands[2].reg;
13475 reject_bad_reg (Rm);
13487 unsigned Rd, Rn, Rm;
13491 Rm = inst.operands[2].reg;
13495 reject_bad_reg (Rm);
13499 inst.instruction |= Rm;
13519 /* PR 10168. Swap the Rm and Rn registers. */
13602 unsigned Rd, Rm;
13605 Rm = inst.operands[1].reg;
13608 reject_bad_reg (Rm);
13611 inst.instruction |= Rm << 16;
13612 inst.instruction |= Rm;
13618 unsigned Rd, Rm;
13621 Rm = inst.operands[1].reg;
13624 reject_bad_reg (Rm);
13626 if (Rd <= 7 && Rm <= 7
13631 inst.instruction |= Rm << 3;
13637 inst.instruction |= Rm << 16;
13638 inst.instruction |= Rm;
13647 unsigned Rd, Rm;
13650 Rm = inst.operands[1].reg;
13653 reject_bad_reg (Rm);
13656 inst.instruction |= Rm;
13877 unsigned Rd, Rn, Rm;
13881 Rm = inst.operands[2].reg;
13885 reject_bad_reg (Rm);
13889 inst.instruction |= Rm;
13895 unsigned Rd, Rn, Rm;
13898 Rm = inst.operands[1].reg;
13903 reject_bad_reg (Rm);
13907 inst.instruction |= Rm;
14034 unsigned Rd, Rn, Rm;
14038 Rm = inst.operands[2].reg;
14042 reject_bad_reg (Rm);
14046 inst.instruction |= Rm;
14053 unsigned Rd, Rm;
14056 Rm = inst.operands[1].reg;
14059 reject_bad_reg (Rm);
14063 && Rd <= 7 && Rm <= 7
14068 inst.instruction |= Rm << 3;
14075 inst.instruction |= Rm;
14095 unsigned Rn, Rm;
14104 Rm = inst.operands[0].imm;
14108 reject_bad_reg (Rm);
14112 inst.instruction |= (Rn << 16) | Rm;
14328 /* Assuming Rm is already checked not to be 11x1. */
14349 /* Assuming Rm is already checked not to be 11x1. */
16006 unsigned Rm;
16011 Rm = 7;
16023 Rm = inst.operands[2].reg >> 1;
16030 inst.instruction |= Rm << 1;
16583 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16602 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
17634 scalars, which are encoded in 5 bits, M : Rm.
17635 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17636 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
18799 int rm;
18848 case neon_cvt_mode_a: rm = 0; break;
18849 case neon_cvt_mode_n: rm = 1; break;
18850 case neon_cvt_mode_p: rm = 2; break;
18851 case neon_cvt_mode_m: rm = 3; break;
18865 inst.instruction |= rm << 16;
19406 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19504 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19592 unsigned rm
19595 inst.instruction |= rm;
19607 /* Redo Rn and Rm. */
19873 (Register operations, which are VORR with Rm = Rn.)
19893 13. VMOV <Sd>, <Rm>
19897 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
21594 unsigned imm, Rd, Rn, Rm;
21604 Rm = inst.operands[4].reg;
21610 Rm = inst.operands[3].reg;
21621 inst.instruction |= Rm << 12;
22039 unsigned int Rm = inst.operands[2].reg;
22044 inst.instruction |= LOW4 (Rm);
22048 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
Indexes created Sun Mar 01 05:31:48 UTC 2026