Lines Matching refs:inst
568 static struct arm_it inst;
1005 return inst.cond != COND_ALWAYS;
1019 inst.pred_insn_type = type; \
1028 inst.pred_insn_type = type; \
1037 if (inst.cond == COND_ALWAYS) \
1155 inst.error = _("immediate expression requires a # prefix");
1182 if (inst.error == NULL)
1183 inst.error = (ep->X_op == O_absent
1198 inst.error = _("invalid constant");
1565 if (!inst.error)
1566 inst.error = err;
2015 inst.error = _("invalid register mask");
2034 if (inst.relocs[0].type != 0)
2036 inst.error = _("expression too complex");
2040 memcpy (&inst.relocs[0].exp, &exp, sizeof (expressionS));
2041 inst.relocs[0].type = BFD_RELOC_ARM_MULTI;
2042 inst.relocs[0].pc_rel = 0;
2092 inst.error = _("expecting {");
2223 inst.error = gettext (reg_expected_msgs[regtype]);
2238 inst.error = _("register range not in ascending order");
2246 inst.error = _("invalid register list");
2277 inst.error = _("non-contiguous register range");
3499 /* Add the literal in the global 'inst'
3515 imm1 = inst.operands[1].imm;
3516 imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg
3517 : inst.relocs[0].exp.X_unsigned ? 0
3518 : (int64_t) inst.operands[1].imm >> 32);
3522 imm2 = inst.operands[1].imm;
3533 if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
3534 && (inst.relocs[0].exp.X_op == O_constant)
3536 == inst.relocs[0].exp.X_add_number)
3539 == inst.relocs[0].exp.X_unsigned))
3542 if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
3543 && (inst.relocs[0].exp.X_op == O_symbol)
3545 == inst.relocs[0].exp.X_add_number)
3547 == inst.relocs[0].exp.X_add_symbol)
3549 == inst.relocs[0].exp.X_op_symbol)
3559 == inst.relocs[0].exp.X_unsigned)
3563 == inst.relocs[0].exp.X_unsigned))
3578 inst.error = _("literal pool overflow");
3595 if (!(inst.relocs[0].exp.X_op == O_constant
3596 || inst.relocs[0].exp.X_op == O_big))
3598 inst.error = _("invalid type for literal pool");
3605 inst.error = _("literal pool overflow");
3609 pool->literals[entry] = inst.relocs[0].exp;
3618 inst.error = _("literal pool overflow");
3622 pool->literals[entry] = inst.relocs[0].exp;
3625 pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
3627 pool->literals[entry] = inst.relocs[0].exp;
3630 pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
3637 pool->literals[entry] = inst.relocs[0].exp;
3653 pool->literals[entry] = inst.relocs[0].exp;
3657 inst.relocs[0].exp.X_op = O_symbol;
3658 inst.relocs[0].exp.X_add_number = pool_size;
3659 inst.relocs[0].exp.X_add_symbol = pool->symbol;
3942 as_bad (_(".inst.n operand too big. "\
3943 "Use .inst.w instead"));
3963 "Use .inst.n/.inst.w instead"));
5125 { "inst.n", s_arm_elf_inst, 2 },
5126 { "inst.w", s_arm_elf_inst, 4 },
5127 { "inst", s_arm_elf_inst, 0 },
5200 inst.error = _("constant expression required");
5206 inst.error = _("immediate value out of range");
5216 instructions. Puts the result directly in inst.operands[i]. */
5230 inst.operands[i].imm = exp_p->X_add_number & 0xffffffff;
5237 inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16)
5239 inst.operands[i].regisimm = 1;
5269 inst.operands[i].imm = 0;
5271 inst.operands[i].imm |= ((unsigned) generic_bignum[idx]
5273 inst.operands[i].reg = 0;
5275 inst.operands[i].reg |= ((unsigned) generic_bignum[idx]
5277 inst.operands[i].regisimm = 1;
5447 inst.error = _("shift expression expected");
5455 inst.error = _("shift expression expected");
5467 inst.error = _("'UXTW' not allowed here");
5475 inst.error = _("'LSL' or 'ASR' required");
5483 inst.error = _("'LSL' required");
5491 inst.error = _("'ASR' required");
5498 inst.error = _("'UXTW' required");
5514 inst.operands[i].imm = reg;
5515 inst.operands[i].immisreg = 1;
5517 else if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
5520 inst.operands[i].shift_kind = shift;
5521 inst.operands[i].shifted = 1;
5545 inst.operands[i].reg = value;
5546 inst.operands[i].isreg = 1;
5549 inst.relocs[0].exp.X_op = O_constant;
5550 inst.relocs[0].exp.X_add_number = 0;
5559 if (my_get_expression (&inst.relocs[0].exp, str, GE_IMM_PREFIX))
5568 if (exp.X_op != O_constant || inst.relocs[0].exp.X_op != O_constant)
5570 inst.error = _("constant expression expected");
5577 inst.error = _("invalid rotation");
5580 if (inst.relocs[0].exp.X_add_number < 0
5581 || inst.relocs[0].exp.X_add_number > 255)
5583 inst.error = _("invalid constant");
5588 inst.operands[i].imm = inst.relocs[0].exp.X_add_number | value << 7;
5592 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
5593 inst.relocs[0].pc_rel = 0;
5759 inst.error = _("unknown group relocation");
5765 if (my_get_expression (&inst.relocs[0].exp, str, GE_NO_PREFIX))
5769 inst.relocs[0].type = (bfd_reloc_code_real_type) entry->alu_code;
5770 gas_assert (inst.relocs[0].type != 0);
5782 inst.operands[i]. We assume the initial ':' has been skipped.
5795 inst.error = _("alignment must be constant");
5799 inst.operands[i].imm = exp.X_add_number << 8;
5800 inst.operands[i].immisalign = 1;
5802 inst.operands[i].preind = 0;
5809 to inst.operands[i] and/or inst.relocs[0].
5838 supported by the instruction, and to set inst.relocs[0].type. */
5854 inst.error = BAD_SYNTAX;
5860 inst.relocs[0].pc_rel = 1;
5861 inst.operands[i].reg = REG_PC;
5862 inst.operands[i].isreg = 1;
5863 inst.operands[i].preind = 1;
5865 if (my_get_expression (&inst.relocs[0].exp, &p, GE_OPT_PREFIX_BIG))
5868 else if (parse_big_immediate (&p, i, &inst.relocs[0].exp,
5885 inst.operands[i].isquad = 1;
5889 inst.error = BAD_ADDR_MODE;
5896 inst.error = BAD_ADDR_MODE;
5898 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5901 inst.operands[i].reg = reg;
5902 inst.operands[i].isreg = 1;
5906 inst.operands[i].preind = 1;
5909 else if (*p == '-') p++, inst.operands[i].negative = 1;
5916 inst.operands[i].immisreg = 2;
5917 inst.operands[i].imm = reg;
5923 inst.operands[i].imm |= inst.relocs[0].exp.X_add_number << 5;
5924 inst.relocs[0].exp.X_add_number = 0;
5932 inst.operands[i].imm = reg;
5933 inst.operands[i].immisreg = 1;
5951 if (inst.operands[i].negative)
5953 inst.operands[i].negative = 0;
5972 inst.error = _("unknown group relocation");
5979 if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
5986 inst.relocs[0].type
5991 inst.relocs[0].type
5996 inst.relocs[0].type
6004 if (inst.relocs[0].type == 0)
6006 inst.error = _("this group relocation is not allowed on this instruction");
6014 if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
6017 if (inst.relocs[0].exp.X_op == O_constant
6018 && inst.relocs[0].exp.X_add_number == 0)
6027 inst.operands[i].negative = 1;
6044 inst.error = _("']' expected");
6049 inst.operands[i].writeback = 1;
6056 if (parse_immediate (&p, &inst.operands[i].imm,
6062 inst.error = _("'}' expected at end of 'option' field");
6065 if (inst.operands[i].preind)
6067 inst.error = _("cannot combine index with option");
6075 inst.operands[i].postind = 1;
6076 inst.operands[i].writeback = 1;
6078 if (inst.operands[i].preind)
6080 inst.error = _("cannot combine pre- and post-indexing");
6085 else if (*p == '-') p++, inst.operands[i].negative = 1;
6092 inst.operands[i].immisreg = 2;
6093 inst.operands[i].imm = reg;
6099 if (inst.operands[i].immisalign)
6100 inst.operands[i].imm |= reg;
6102 inst.operands[i].imm = reg;
6103 inst.operands[i].immisreg = 1;
6113 if (inst.operands[i].negative)
6115 inst.operands[i].negative = 0;
6118 if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
6121 if (inst.relocs[0].exp.X_op == O_constant
6122 && inst.relocs[0].exp.X_add_number == 0)
6131 inst.operands[i].negative = 1;
6139 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
6141 inst.operands[i].preind = 1;
6142 inst.relocs[0].exp.X_op = O_constant;
6143 inst.relocs[0].exp.X_add_number = 0;
6171 inst.relocs[0].type = BFD_RELOC_ARM_MOVW;
6173 inst.relocs[0].type = BFD_RELOC_ARM_MOVT;
6175 if (inst.relocs[0].type != BFD_RELOC_UNUSED)
6181 if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
6184 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
6186 if (inst.relocs[0].exp.X_op != O_constant)
6188 inst.error = _("constant expression expected");
6191 if (inst.relocs[0].exp.X_add_number < 0
6192 || inst.relocs[0].exp.X_add_number > 0xffff)
6194 inst.error = _("immediate value out of range");
6331 inst.error = _("unexpected bit specified after APSR");
6343 inst.error = _("selected processor does not "
6355 inst.error = _("bad bitmask specified after APSR");
6390 inst.error = _("selected processor does not support requested special "
6395 inst.error = _("flag for {c}psr instruction expected");
6455 inst.error = _("unrecognized CPS flag");
6462 inst.error = _("missing CPS flags");
6485 inst.error = _("valid endian specifiers are be or le");
6491 inst.error = _("valid endian specifiers are be or le");
6513 inst.error = _("missing rotation field after comma");
6528 inst.error = _("rotation can only be 0, 8, 16, or 24");
6557 inst.error = _("condition required");
6598 inst.error = _("'[' expected");
6604 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6607 inst.operands[0].reg = reg;
6611 inst.error = _("',' expected");
6617 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6620 inst.operands[0].imm = reg;
6626 if (inst.relocs[0].exp.X_add_number != 1)
6628 inst.error = _("invalid shift");
6631 inst.operands[0].shifted = 1;
6636 inst.error = _("']' expected");
6661 inst.operands[i].reg = val;
6662 inst.operands[i].isvec = 1;
6663 inst.operands[i].isscalar = 2;
6664 inst.operands[i].vectype = optype;
6665 inst.operands[i++].present = 1;
6673 inst.operands[i].reg = val;
6674 inst.operands[i].isreg = 1;
6675 inst.operands[i].present = 1;
6680 inst.operands[i].reg = val;
6681 inst.operands[i].isvec = 1;
6682 inst.operands[i].isscalar = 2;
6683 inst.operands[i].vectype = optype;
6684 inst.operands[i++].present = 1;
6692 inst.operands[i].reg = val;
6693 inst.operands[i].isreg = 1;
6694 inst.operands[i++].present = 1;
6702 inst.operands[i].reg = val;
6703 inst.operands[i].isreg = 1;
6704 inst.operands[i].present = 1;
6715 inst.operands[i].reg = val;
6716 inst.operands[i].isscalar = 1;
6717 inst.operands[i].vectype = optype;
6718 inst.operands[i++].present = 1;
6726 inst.operands[i].reg = val;
6727 inst.operands[i].isreg = 1;
6728 inst.operands[i].present = 1;
6739 inst.operands[i].reg = val;
6740 inst.operands[i].isreg = 1;
6741 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6742 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6743 inst.operands[i].isvec = 1;
6744 inst.operands[i].vectype = optype;
6745 inst.operands[i++].present = 1;
6751 inst.operands[i].reg = val;
6752 inst.operands[i].isreg = 1;
6753 inst.operands[i].present = 1;
6767 inst.operands[i].reg = val;
6768 inst.operands[i].isreg = 1;
6769 inst.operands[i].present = 1;
6782 inst.operands[i].reg = val;
6783 inst.operands[i].isreg = 1;
6784 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6785 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6786 inst.operands[i].isvec = 1;
6787 inst.operands[i].vectype = optype;
6788 inst.operands[i].present = 1;
6798 inst.operands[i].reg = val;
6799 inst.operands[i].isreg = 1;
6800 inst.operands[i++].present = 1;
6808 inst.operands[i].reg = val;
6809 inst.operands[i].isreg = 1;
6810 inst.operands[i].present = 1;
6813 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
6818 inst.operands[i].immisfloat = 1;
6833 inst.operands[i].reg = val;
6834 inst.operands[i].isreg = 1;
6835 inst.operands[i++].present = 1;
6843 inst.operands[i].reg = val;
6844 inst.operands[i].isscalar = 2;
6845 inst.operands[i].present = 1;
6846 inst.operands[i].vectype = optype;
6851 inst.operands[i].reg = val;
6852 inst.operands[i].isscalar = 1;
6853 inst.operands[i].present = 1;
6854 inst.operands[i].vectype = optype;
6858 inst.operands[i].reg = val;
6859 inst.operands[i].isreg = 1;
6860 inst.operands[i++].present = 1;
6870 inst.operands[i].reg = val;
6871 inst.operands[i].isreg = 1;
6872 inst.operands[i].isvec = 1;
6873 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6874 inst.operands[i].vectype = optype;
6875 inst.operands[i].present = 1;
6889 inst.operands[i].reg = val;
6890 inst.operands[i].isreg = 1;
6891 inst.operands[i].isvec = 1;
6892 inst.operands[i].issingle = 1;
6893 inst.operands[i].vectype = optype;
6894 inst.operands[i].present = 1;
6903 inst.operands[i].reg = val;
6904 inst.operands[i].isvec = 1;
6905 inst.operands[i].isscalar = 2;
6906 inst.operands[i].vectype = optype;
6907 inst.operands[i++].present = 1;
6918 inst.operands[i].reg = val;
6919 inst.operands[i].isvec = 1;
6920 inst.operands[i].isscalar = 2;
6921 inst.operands[i].vectype = optype;
6922 inst.operands[i].present = 1;
6936 inst.operands[i].reg = val;
6937 inst.operands[i].isreg = 1;
6938 inst.operands[i].isvec = 1;
6939 inst.operands[i].issingle = 1;
6940 inst.operands[i].vectype = optype;
6941 inst.operands[i].present = 1;
7158 semantic validation; it merely squirrels values away in the inst
7185 & inst.operands[i].vectype); \
7191 inst.operands[i].reg = val; \
7192 inst.operands[i].isreg = 1; \
7193 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7194 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7195 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7198 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7206 & inst.operands[i].vectype); \
7210 inst.operands[i].reg = val; \
7211 inst.operands[i].isreg = 1; \
7212 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7213 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7214 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7217 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7226 inst.operands[i].imm = val; \
7237 inst.error = _("constant expression required"); \
7242 inst.error = _("immediate value 48 or 64 expected"); \
7245 inst.operands[i].imm = exp.X_add_number; \
7252 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7256 inst.operands[i].reg = val; \
7257 inst.operands[i].isscalar = 1; \
7288 || ((inst.instruction & 0xf0) == 0x60 \
7291 inst.error = _("invalid barrier type"); \
7311 backtrack_error = inst.error;
7315 if (i > 0 && (i > 1 || inst.operands[0].present))
7365 inst.operands[i].isreg = 1;
7366 inst.operands[i].reg = 13;
7420 inst.error = 0;
7456 inst.operands[i].imm = 0;
7459 inst.error
7486 inst.error = 0;
7490 inst.error = 0;
7555 inst.error = _("immediate value is out of range");
7588 inst.operands[i].writeback = 1;
7636 inst.operands[i].writeback = 1;
7646 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
7651 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
7656 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
7658 if (inst.relocs[0].exp.X_op == O_symbol)
7663 inst.error = _("unrecognized relocation suffix");
7668 inst.operands[i].imm = val;
7669 inst.operands[i].hasreloc = 1;
7675 po_misc_or_fail (my_get_expression (&inst.relocs[i].exp, &str,
7677 if (inst.relocs[i].exp.X_op == O_symbol)
7679 inst.operands[i].hasreloc = 1;
7681 else if (inst.relocs[i].exp.X_op == O_constant)
7683 inst.operands[i].imm = inst.relocs[i].exp.X_add_number;
7684 inst.operands[i].hasreloc = 0;
7716 inst.error = _("iWMMXt data or control register expected");
7719 inst.operands[i].reg = rege->number;
7720 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
7731 inst.error = _("iWMMXt control register expected");
7734 inst.operands[i].reg = rege->number;
7735 inst.operands[i].isreg = 1;
7757 inst.error = _("Banked registers are not available with this "
7794 inst.operands[i].isvec = 1;
7796 inst.operands[i].reg = REG_PC;
7811 inst.operands[i].writeback = 1;
7821 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S,
7826 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D,
7832 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7836 inst.error = NULL;
7837 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7839 inst.operands[i].issingle = 1;
7844 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7848 inst.error = NULL;
7849 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7851 inst.operands[i].issingle = 1;
7856 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7862 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
7863 1, &inst.operands[i].vectype);
7868 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
7869 0, &inst.operands[i].vectype);
7945 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
7946 inst.error = BAD_PC;
7952 if (inst.operands[i].isreg)
7954 if (inst.operands[i].reg == REG_PC)
7955 inst.error = BAD_PC;
7956 else if (inst.operands[i].reg == REG_SP
7962 inst.error = BAD_SP;
7968 if (inst.operands[i].isreg
7969 && inst.operands[i].reg == REG_PC
7970 && (inst.operands[i].writeback || thumb))
7971 inst.error = BAD_PC;
7976 if (inst.operands[i].isreg)
7999 inst.operands[i].imm = val;
8004 if (inst.operands[i].reg != REG_LR)
8005 inst.error = _("operand must be LR register");
8009 if (inst.operands[i].reg != REG_SP)
8010 inst.error = _("operand must be SP register");
8014 if (inst.operands[i].reg != REG_R12)
8015 inst.error = _("operand must be r12");
8021 if (!inst.operands[i].iszr && inst.operands[i].reg == REG_PC)
8022 inst.error = BAD_PC;
8026 if (inst.operands[i].isreg
8027 && (inst.operands[i].reg & 0x00000001) != 0)
8028 inst.error = BAD_ODD;
8032 if (inst.operands[i].isreg)
8034 if ((inst.operands[i].reg & 0x00000001) != 1)
8035 inst.error = BAD_EVEN;
8036 else if (inst.operands[i].reg == REG_SP)
8038 else if (inst.operands[i].reg == REG_PC)
8039 inst.error = BAD_PC;
8048 inst.operands[i].present = 1;
8052 inst.error = BAD_ARGS;
8057 /* The parse routine should already have set inst.error, but set a
8059 if (!inst.error)
8060 inst.error = BAD_SYNTAX;
8071 if (!inst.error)
8072 inst.error = BAD_SYNTAX;
8078 inst.error = backtrack_error;
8079 inst.operands[backtrack_index].present = 0;
8085 if (*str != '\0' && !inst.error)
8086 inst.error = _("garbage following instruction");
8088 return inst.error ? FAIL : SUCCESS;
8104 inst.error = err; \
8120 inst.error = BAD_PC; \
8126 inst.error = BAD_SP; \
8143 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8153 if (inst.cond < COND_ALWAYS)
8159 inst.instruction = (inst.instruction & 0xfffff0ff) | 0x900;
8210 /* Encode a VFP SP or DP register number into inst.instruction. */
8237 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
8241 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
8245 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
8249 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
8253 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
8257 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
8271 if (inst.operands[i].immisreg)
8279 if (inst.operands[op_index].present && inst.operands[op_index].isreg
8280 && inst.operands[op_index].reg == REG_PC)
8284 if (inst.operands[i].imm == REG_PC)
8288 if (inst.operands[i].shift_kind == SHIFT_RRX)
8289 inst.instruction |= SHIFT_ROR << 5;
8292 inst.instruction |= inst.operands[i].shift_kind << 5;
8293 if (inst.operands[i].immisreg)
8295 inst.instruction |= SHIFT_BY_REG;
8296 inst.instruction |= inst.operands[i].imm << 8;
8299 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
8306 if (inst.operands[i].isreg)
8308 inst.instruction |= inst.operands[i].reg;
8313 inst.instruction |= INST_IMMEDIATE;
8314 if (inst.relocs[0].type != BFD_RELOC_ARM_IMMEDIATE)
8315 inst.instruction |= inst.operands[i].imm;
8325 constraint (!inst.operands[i].isreg,
8328 inst.instruction |= inst.operands[i].reg << 16;
8330 if (inst.operands[i].preind)
8334 inst.error = _("instruction does not accept preindexed addressing");
8337 inst.instruction |= PRE_INDEX;
8338 if (inst.operands[i].writeback)
8339 inst.instruction |= WRITE_BACK;
8342 else if (inst.operands[i].postind)
8344 gas_assert (inst.operands[i].writeback);
8346 inst.instruction |= WRITE_BACK;
8350 inst.error = _("instruction does not accept unindexed addressing");
8354 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
8355 && (((inst.instruction & 0x000f0000) >> 16)
8356 == ((inst.instruction & 0x0000f000) >> 12)))
8357 as_warn ((inst.instruction & LOAD_BIT)
8362 /* inst.operands[i] was set up by parse_address. Encode it into an
8369 const bool is_pc = (inst.operands[i].reg == REG_PC);
8373 if (inst.operands[i].immisreg)
8375 constraint ((inst.operands[i].imm == REG_PC
8376 || (is_pc && inst.operands[i].writeback)),
8378 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
8379 inst.instruction |= inst.operands[i].imm;
8380 if (!inst.operands[i].negative)
8381 inst.instruction |= INDEX_UP;
8382 if (inst.operands[i].shifted)
8384 if (inst.operands[i].shift_kind == SHIFT_RRX)
8385 inst.instruction |= SHIFT_ROR << 5;
8388 inst.instruction |= inst.operands[i].shift_kind << 5;
8389 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
8393 else /* immediate offset in inst.relocs[0] */
8395 if (is_pc && !inst.relocs[0].pc_rel)
8397 const bool is_load = ((inst.instruction & LOAD_BIT) != 0);
8402 constraint ((is_t || inst.operands[i].writeback),
8412 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
8415 if (!inst.operands[i].negative)
8416 inst.instruction |= INDEX_UP;
8417 inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM;
8422 /* inst.operands[i] was set up by parse_address. Encode it into an
8430 if (inst.operands[i].immisreg && inst.operands[i].shifted)
8432 inst.error = _("instruction does not accept scaled register index");
8438 if (inst.operands[i].immisreg)
8440 constraint ((inst.operands[i].imm == REG_PC
8441 || (is_t && inst.operands[i].reg == REG_PC)),
8443 constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback,
8445 inst.instruction |= inst.operands[i].imm;
8446 if (!inst.operands[i].negative)
8447 inst.instruction |= INDEX_UP;
8449 else /* immediate offset in inst.relocs[0] */
8451 constraint ((inst.operands[i].reg == REG_PC && !inst.relocs[0].pc_rel
8452 && inst.operands[i].writeback),
8454 inst.instruction |= HWOFFSET_IMM;
8455 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
8458 if (!inst.operands[i].negative)
8459 inst.instruction |= INDEX_UP;
8461 inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM8;
8476 inst.instruction |= immbits & 0xf;
8477 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
8478 inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24);
8712 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8714 it can, convert inst.instruction to that move instruction and
8715 return true; if it can't, convert inst.instruction to a literal-pool
8717 current context, set inst.error and return TRUE.
8719 inst.operands[i] describes the destination register. */
8729 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
8733 if ((inst.instruction & tbit) == 0)
8735 inst.error = _("invalid pseudo operation");
8739 if (inst.relocs[0].exp.X_op != O_constant
8740 && inst.relocs[0].exp.X_op != O_symbol
8741 && inst.relocs[0].exp.X_op != O_big)
8743 inst.error = _("constant expression expected");
8747 if (inst.relocs[0].exp.X_op == O_constant
8748 || inst.relocs[0].exp.X_op == O_big)
8751 if (inst.relocs[0].exp.X_op == O_big)
8755 if (inst.relocs[0].exp.X_add_number <= 0) /* FP value. */
8777 inst.error = _("constant expression not supported");
8792 v = inst.relocs[0].exp.X_add_number;
8794 if (!inst.operands[i].issingle)
8803 && inst.operands[i].reg != 13
8804 && inst.operands[i].reg != 15)
8823 inst.instruction = (0xf04f0000 /* MOV.W. */
8824 | (inst.operands[i].reg << 8));
8826 inst.instruction |= (isNegated ? 0x200000 : 0);
8827 inst.instruction |= (newimm & 0x800) << 15;
8828 inst.instruction |= (newimm & 0x700) << 4;
8829 inst.instruction |= (newimm & 0x0ff);
8838 inst.instruction = 0xf2400000; /* MOVW. */
8839 inst.instruction |= (inst.operands[i].reg << 8);
8840 inst.instruction |= (imm & 0xf000) << 4;
8841 inst.instruction |= (imm & 0x0800) << 15;
8842 inst.instruction |= (imm & 0x0700) << 4;
8843 inst.instruction |= (imm & 0x00ff);
8848 inst.size_req = 0;
8860 inst.instruction &= LITERAL_MASK;
8861 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
8862 inst.instruction |= value & 0xfff;
8870 inst.instruction &= LITERAL_MASK;
8871 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
8872 inst.instruction |= value & 0xfff;
8880 unsigned immlo = inst.operands[1].imm;
8881 unsigned immhi = inst.operands[1].regisimm
8882 ? inst.operands[1].reg
8883 : inst.relocs[0].exp.X_unsigned
8899 inst.instruction = (inst.instruction & VLDR_VMOV_SAME)
8907 inst.instruction |= (0x7U << 29) | (0xF << 24);
8909 inst.instruction |= (0xFU << 28) | (0x1 << 25);
8919 if (inst.operands[i].issingle
8920 && is_quarter_float (inst.operands[1].imm)
8923 inst.operands[1].imm =
8934 else if (!inst.operands[1].issingle
8940 inst.operands[1].imm =
8949 if (add_to_lit_pool ((!inst.operands[i].isvec
8950 || inst.operands[i].issingle) ? 4 : 8) == FAIL)
8953 inst.operands[1].reg = REG_PC;
8954 inst.operands[1].isreg = 1;
8955 inst.operands[1].preind = 1;
8956 inst.relocs[0].pc_rel = 1;
8957 inst.relocs[0].type = (thumb_p
8965 /* inst.operands[i] was set up by parse_address. Encode it into an
8976 if (!inst.operands[i].isreg)
8979 if (! inst.operands[0].isvec)
8981 inst.error = _("invalid co-processor operand");
8988 inst.instruction |= inst.operands[i].reg << 16;
8990 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
8992 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
8994 gas_assert (!inst.operands[i].writeback);
8997 inst.error = _("instruction does not support unindexed addressing");
9000 inst.instruction |= inst.operands[i].imm;
9001 inst.instruction |= INDEX_UP;
9005 if (inst.operands[i].preind)
9006 inst.instruction |= PRE_INDEX;
9008 if (inst.operands[i].writeback)
9010 if (inst.operands[i].reg == REG_PC)
9012 inst.error = _("pc may not be used with write-back");
9017 inst.error = _("instruction does not support writeback");
9020 inst.instruction |= WRITE_BACK;
9024 inst.relocs[0].type = (bfd_reloc_code_real_type) reloc_override;
9025 else if ((inst.relocs[0].type < BFD_RELOC_ARM_ALU_PC_G0_NC
9026 || inst.relocs[0].type > BFD_RELOC_ARM_LDC_SB_G2)
9027 && inst.relocs[0].type != BFD_RELOC_ARM_LDR_PC_G0)
9030 inst.relocs[0].type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
9032 inst.relocs[0].type = BFD_RELOC_ARM_CP_OFF_IMM;
9036 if (!inst.operands[i].negative)
9037 inst.instruction |= INDEX_UP;
9054 inst.instruction |= inst.operands[0].reg << 12;
9060 inst.instruction |= inst.operands[0].reg << 16;
9066 inst.instruction |= inst.operands[0].reg << 12;
9067 inst.instruction |= inst.operands[1].reg;
9073 inst.instruction |= inst.operands[0].reg;
9074 inst.instruction |= inst.operands[1].reg << 16;
9080 inst.instruction |= inst.operands[0].reg << 12;
9081 inst.instruction |= inst.operands[1].reg << 16;
9087 inst.instruction |= inst.operands[0].reg << 16;
9088 inst.instruction |= inst.operands[1].reg << 12;
9094 inst.instruction |= inst.operands[0].reg << 8;
9095 inst.instruction |= inst.operands[1].reg << 16;
9118 unsigned Rn = inst.operands[2].reg;
9120 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
9122 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
9134 inst.instruction |= inst.operands[0].reg << 12;
9135 inst.instruction |= inst.operands[1].reg;
9136 inst.instruction |= Rn << 16;
9142 inst.instruction |= inst.operands[0].reg << 12;
9143 inst.instruction |= inst.operands[1].reg << 16;
9144 inst.instruction |= inst.operands[2].reg;
9150 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
9151 constraint (((inst.relocs[0].exp.X_op != O_constant
9152 && inst.relocs[0].exp.X_op != O_illegal)
9153 || inst.relocs[0].exp.X_add_number != 0),
9155 inst.instruction |= inst.operands[0].reg;
9156 inst.instruction |= inst.operands[1].reg << 12;
9157 inst.instruction |= inst.operands[2].reg << 16;
9163 inst.instruction |= inst.operands[0].imm;
9176 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
9180 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
9181 inst.relocs[0].pc_rel = 1;
9182 inst.relocs[0].exp.X_add_number -= 8;
9185 && inst.relocs[0].exp.X_op == O_symbol
9186 && inst.relocs[0].exp.X_add_symbol != NULL
9187 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
9188 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
9189 inst.relocs[0].exp.X_add_number |= 1;
9200 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
9204 inst.relocs[0].type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
9205 inst.relocs[0].pc_rel = 1;
9206 inst.size = INSN_SIZE * 2;
9207 inst.relocs[0].exp.X_add_number -= 8;
9210 && inst.relocs[0].exp.X_op == O_symbol
9211 && inst.relocs[0].exp.X_add_symbol != NULL
9212 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
9213 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
9214 inst.relocs[0].exp.X_add_number |= 1;
9220 constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9221 && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
9223 if (!inst.operands[1].present)
9224 inst.operands[1].reg = inst.operands[0].reg;
9225 inst.instruction |= inst.operands[0].reg << 12;
9226 inst.instruction |= inst.operands[1].reg << 16;
9233 if (inst.operands[0].present)
9234 inst.instruction |= inst.operands[0].imm;
9236 inst.instruction |= 0xf;
9242 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
9246 inst.instruction |= inst.operands[0].reg << 12;
9247 inst.instruction |= inst.operands[1].imm << 7;
9248 inst.instruction |= (msb - 1) << 16;
9258 if (!inst.operands[1].isreg)
9259 inst.operands[1].reg = REG_PC;
9261 msb = inst.operands[2].imm + inst.operands[3].imm;
9265 inst.instruction |= inst.operands[0].reg << 12;
9266 inst.instruction |= inst.operands[1].reg;
9267 inst.instruction |= inst.operands[2].imm << 7;
9268 inst.instruction |= (msb - 1) << 16;
9274 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
9276 inst.instruction |= inst.operands[0].reg << 12;
9277 inst.instruction |= inst.operands[1].reg;
9278 inst.instruction |= inst.operands[2].imm << 7;
9279 inst.instruction |= (inst.operands[3].imm - 1) << 16;
9292 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
9295 inst.instruction |= inst.operands[0].imm & 0xf;
9301 if (inst.operands[0].hasreloc)
9303 constraint (inst.operands[0].imm != BFD_RELOC_32_PLT_PCREL
9304 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
9306 inst.relocs[0].type = inst.operands[0].imm == BFD_RELOC_32_PLT_PCREL
9311 inst.relocs[0].type = (bfd_reloc_code_real_type) default_reloc;
9312 inst.relocs[0].pc_rel = 1;
9332 if (inst.cond == COND_ALWAYS)
9347 into inst.instruction.
9353 if (inst.operands[0].isreg)
9357 if (inst.operands[0].reg == REG_PC)
9360 inst.instruction |= inst.operands[0].reg;
9368 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9369 inst.instruction = 0xfa000000;
9379 if (inst.operands[0].reg == REG_PC)
9382 inst.instruction |= inst.operands[0].reg;
9396 inst.relocs[0].type = BFD_RELOC_ARM_V4BX;
9405 if (inst.operands[0].reg == REG_PC)
9408 inst.instruction |= inst.operands[0].reg;
9417 inst.instruction |= inst.operands[0].reg << 8;
9418 inst.instruction |= inst.operands[1].imm << 20;
9419 inst.instruction |= inst.operands[2].reg << 12;
9420 inst.instruction |= inst.operands[3].reg << 16;
9421 inst.instruction |= inst.operands[4].reg;
9422 inst.instruction |= inst.operands[5].imm << 5;
9428 inst.instruction |= inst.operands[0].reg << 16;
9487 Rd = inst.operands[2].reg;
9490 if (inst.instruction == 0xee000010
9491 || inst.instruction == 0xfe000010)
9501 if (inst.instruction == 0xe000010)
9510 if (inst.operands[0].reg == r->cp
9511 && inst.operands[1].imm == r->opc1
9512 && inst.operands[3].reg == r->crn
9513 && inst.operands[4].reg == r->crm
9514 && inst.operands[5].imm == r->opc2)
9523 inst.instruction |= inst.operands[0].reg << 8;
9524 inst.instruction |= inst.operands[1].imm << 21;
9525 inst.instruction |= Rd << 12;
9526 inst.instruction |= inst.operands[3].reg << 16;
9527 inst.instruction |= inst.operands[4].reg;
9528 inst.instruction |= inst.operands[5].imm << 5;
9549 Rd = inst.operands[2].reg;
9550 Rn = inst.operands[3].reg;
9564 if ((inst.instruction & 0x0FF00000) == 0x0C500000)
9571 inst.instruction |= inst.operands[0].reg << 8;
9572 inst.instruction |= inst.operands[1].imm << 4;
9573 inst.instruction |= Rd << 12;
9574 inst.instruction |= Rn << 16;
9575 inst.instruction |= inst.operands[4].reg;
9581 inst.instruction |= inst.operands[0].imm << 6;
9582 if (inst.operands[1].present)
9584 inst.instruction |= CPSI_MMOD;
9585 inst.instruction |= inst.operands[1].imm;
9592 inst.instruction |= inst.operands[0].imm;
9600 Rd = inst.operands[0].reg;
9601 Rn = (inst.operands[1].present
9602 ? inst.operands[1].reg : Rd);
9603 Rm = inst.operands[2].reg;
9609 inst.instruction |= Rd << 16;
9610 inst.instruction |= Rn << 0;
9611 inst.instruction |= Rm << 8;
9622 inst.size = 0;
9626 now_pred.mask = (inst.instruction & 0xf) | 0x10;
9627 now_pred.cc = inst.operands[0].imm;
9643 int base_reg = inst.operands[0].reg;
9644 int range = inst.operands[1].imm;
9647 inst.instruction |= base_reg << 16;
9648 inst.instruction |= range;
9650 if (inst.operands[1].writeback)
9651 inst.instruction |= LDM_TYPE_2_OR_3;
9653 if (inst.operands[0].writeback)
9655 inst.instruction |= WRITE_BACK;
9657 if (inst.instruction & LOAD_BIT)
9660 if ((inst.instruction & LDM_TYPE_2_OR_3)
9670 if (inst.instruction & LDM_TYPE_2_OR_3)
9683 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
9690 inst.instruction &= A_COND_MASK;
9691 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
9692 inst.instruction |= one_reg << 12;
9711 constraint (inst.operands[0].reg % 2 != 0,
9713 constraint (inst.operands[1].present
9714 && inst.operands[1].reg != inst.operands[0].reg + 1,
9716 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
9717 constraint (!inst.operands[2].isreg, _("'[' expected"));
9719 if (!inst.operands[1].present)
9720 inst.operands[1].reg = inst.operands[0].reg + 1;
9726 if (inst.operands[2].reg == inst.operands[1].reg
9727 && (inst.operands[2].writeback || inst.operands[2].postind))
9731 if (!(inst.instruction & V4_STR_BIT))
9735 if (inst.operands[2].immisreg
9736 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
9737 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
9740 inst.instruction |= inst.operands[0].reg << 12;
9747 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
9748 || inst.operands[1].postind || inst.operands[1].writeback
9749 || inst.operands[1].immisreg || inst.operands[1].shifted
9750 || inst.operands[1].negative
9762 || (inst.operands[1].reg == REG_PC),
9765 constraint (inst.relocs[0].exp.X_op != O_constant
9766 || inst.relocs[0].exp.X_add_number != 0,
9769 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
9771 inst.instruction |= inst.operands[0].reg << 12;
9772 inst.instruction |= inst.operands[1].reg << 16;
9773 inst.relocs[0].type = BFD_RELOC_UNUSED;
9779 constraint (inst.operands[0].reg % 2 != 0,
9781 constraint (inst.operands[1].present
9782 && inst.operands[1].reg != inst.operands[0].reg + 1,
9786 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
9788 inst.instruction |= inst.operands[0].reg << 12;
9789 inst.instruction |= inst.operands[2].reg << 16;
9797 constraint (!(inst.operands[1].immisreg)
9798 && (inst.operands[0].reg == REG_PC
9799 && inst.operands[1].reg == REG_PC
9800 && (inst.relocs[0].exp.X_add_number & 0x3)),
9807 inst.instruction |= inst.operands[0].reg << 12;
9808 if (!inst.operands[1].isreg)
9820 if (inst.operands[1].preind)
9822 constraint (inst.relocs[0].exp.X_op != O_constant
9823 || inst.relocs[0].exp.X_add_number != 0,
9826 inst.operands[1].preind = 0;
9827 inst.operands[1].postind = 1;
9828 inst.operands[1].writeback = 1;
9830 inst.instruction |= inst.operands[0].reg << 12;
9839 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
9840 inst.instruction |= inst.operands[0].reg << 12;
9841 if (!inst.operands[1].isreg)
9852 if (inst.operands[1].preind)
9854 constraint (inst.relocs[0].exp.X_op != O_constant
9855 || inst.relocs[0].exp.X_add_number != 0,
9858 inst.operands[1].preind = 0;
9859 inst.operands[1].postind = 1;
9860 inst.operands[1].writeback = 1;
9862 inst.instruction |= inst.operands[0].reg << 12;
9871 inst.instruction |= inst.operands[0].reg << 8;
9872 inst.instruction |= inst.operands[1].reg << 12;
9880 if (inst.operands[0].reg == inst.operands[1].reg
9882 && !(inst.instruction & 0x00400000))
9885 inst.instruction |= inst.operands[0].reg << 16;
9886 inst.instruction |= inst.operands[1].reg;
9887 inst.instruction |= inst.operands[2].reg << 8;
9888 inst.instruction |= inst.operands[3].reg << 12;
9894 constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9895 && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
9897 inst.instruction |= inst.operands[0].reg << 12;
9908 top = (inst.instruction & 0x00400000) != 0;
9909 constraint (top && inst.relocs[0].type == BFD_RELOC_ARM_MOVW,
9911 constraint (!top && inst.relocs[0].type == BFD_RELOC_ARM_MOVT,
9913 inst.instruction |= inst.operands[0].reg << 12;
9914 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
9916 imm = inst.relocs[0].exp.X_add_number;
9918 inst.instruction |= (imm & 0x00000fff);
9919 inst.instruction |= (imm & 0x0000f000) << 4;
9926 if (inst.operands[0].isvec)
9928 if (inst.operands[1].reg != 1)
9930 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
9931 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
9934 else if (inst.operands[1].isvec)
9945 if (inst.operands[0].isvec)
9956 unsigned Rt = inst.operands[0].reg;
9960 inst.error = BAD_SP;
9964 switch (inst.operands[1].reg)
9992 if (inst.operands[0].reg != 2
10002 if (!inst.operands[0].isvec && Rt == REG_PC)
10004 inst.error = BAD_PC;
10010 inst.instruction |= (inst.operands[1].reg << 16);
10011 inst.instruction |= (Rt << 12);
10017 unsigned Rt = inst.operands[1].reg;
10023 inst.error = BAD_PC;
10027 switch (inst.operands[0].reg)
10055 if (inst.operands[0].reg != 2
10066 inst.instruction |= (inst.operands[0].reg << 16);
10067 inst.instruction |= (Rt << 12);
10078 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10079 inst.instruction |= inst.operands[0].reg << 12;
10081 if (inst.operands[1].isreg)
10083 br = inst.operands[1].reg;
10090 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
10093 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
10096 inst.instruction |= br;
10109 inst.instruction |= inst.operands[0].imm;
10110 if (inst.operands[1].isreg)
10111 inst.instruction |= inst.operands[1].reg;
10114 inst.instruction |= INST_IMMEDIATE;
10115 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
10116 inst.relocs[0].pc_rel = 0;
10123 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
10125 if (!inst.operands[2].present)
10126 inst.operands[2].reg = inst.operands[0].reg;
10127 inst.instruction |= inst.operands[0].reg << 16;
10128 inst.instruction |= inst.operands[1].reg;
10129 inst.instruction |= inst.operands[2].reg << 8;
10131 if (inst.operands[0].reg == inst.operands[1].reg
10145 inst.instruction |= inst.operands[0].reg << 12;
10146 inst.instruction |= inst.operands[1].reg << 16;
10147 inst.instruction |= inst.operands[2].reg;
10148 inst.instruction |= inst.operands[3].reg << 8;
10151 if (inst.operands[0].reg == inst.operands[1].reg)
10155 if ((inst.operands[0].reg == inst.operands[2].reg
10156 || inst.operands[1].reg == inst.operands[2].reg)
10164 if (inst.operands[0].present
10168 inst.instruction &= 0xf0000000;
10169 inst.instruction |= 0x0320f000;
10170 if (inst.operands[0].present)
10171 inst.instruction |= inst.operands[0].imm;
10183 inst.instruction |= inst.operands[0].reg << 12;
10184 inst.instruction |= inst.operands[1].reg << 16;
10185 inst.instruction |= inst.operands[2].reg;
10186 if (inst.operands[3].present)
10195 if (!inst.operands[3].present)
10199 inst.instruction &= 0xfff00010;
10200 inst.instruction |= inst.operands[0].reg << 12;
10201 inst.instruction |= inst.operands[1].reg;
10202 inst.instruction |= inst.operands[2].reg << 16;
10206 inst.instruction |= inst.operands[0].reg << 12;
10207 inst.instruction |= inst.operands[1].reg << 16;
10208 inst.instruction |= inst.operands[2].reg;
10223 constraint (!inst.operands[0].isreg,
10225 constraint (inst.operands[0].postind,
10227 constraint (inst.operands[0].writeback,
10229 constraint (!inst.operands[0].preind,
10238 constraint (!inst.operands[0].isreg,
10240 constraint (inst.operands[0].postind,
10242 constraint (inst.operands[0].writeback,
10244 constraint (!inst.operands[0].preind,
10247 inst.instruction &= ~PRE_INDEX;
10253 constraint (inst.operands[0].writeback,
10255 inst.operands[1] = inst.operands[0];
10256 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
10257 inst.operands[0].isreg = 1;
10258 inst.operands[0].writeback = 1;
10259 inst.operands[0].reg = REG_SP;
10272 inst.instruction |= inst.operands[0].reg << 16;
10273 if (inst.operands[0].writeback)
10274 inst.instruction |= WRITE_BACK;
10282 inst.instruction |= inst.operands[0].reg << 12;
10283 inst.instruction |= (inst.operands[1].imm - 1) << 16;
10284 inst.instruction |= inst.operands[2].reg;
10286 if (inst.operands[3].present)
10295 inst.instruction |= inst.operands[0].reg << 12;
10296 inst.instruction |= inst.operands[1].imm << 16;
10297 inst.instruction |= inst.operands[2].reg;
10299 if (inst.operands[3].present)
10308 inst.instruction |= inst.operands[0].reg << 12;
10309 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
10310 inst.instruction |= inst.operands[2].reg;
10316 inst.instruction |= inst.operands[0].reg << 12;
10317 inst.instruction |= inst.operands[1].imm << 16;
10318 inst.instruction |= inst.operands[2].reg;
10334 if (inst.operands[0].imm)
10335 inst.instruction |= 0x200;
10341 unsigned int Rm = (inst.operands[1].present
10342 ? inst.operands[1].reg
10343 : inst.operands[0].reg);
10345 inst.instruction |= inst.operands[0].reg << 12;
10346 inst.instruction |= Rm;
10347 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
10349 inst.instruction |= inst.operands[2].reg << 8;
10350 inst.instruction |= SHIFT_BY_REG;
10352 constraint (inst.operands[2].shifted,
10356 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
10362 unsigned int value = inst.relocs[0].exp.X_add_number;
10365 inst.relocs[0].type = BFD_RELOC_ARM_SMC;
10366 inst.relocs[0].pc_rel = 0;
10372 inst.relocs[0].type = BFD_RELOC_ARM_HVC;
10373 inst.relocs[0].pc_rel = 0;
10379 inst.relocs[0].type = BFD_RELOC_ARM_SWI;
10380 inst.relocs[0].pc_rel = 0;
10389 inst.instruction |= ((inst.operands[0].imm & 1) << 9);
10398 inst.instruction |= (inst.operands[0].imm << 3);
10409 inst.instruction |= inst.operands[0].reg << 16;
10410 inst.instruction |= inst.operands[1].reg;
10411 inst.instruction |= inst.operands[2].reg << 8;
10412 inst.instruction |= inst.operands[3].reg << 12;
10423 inst.instruction |= inst.operands[0].reg << 12;
10424 inst.instruction |= inst.operands[1].reg << 16;
10425 inst.instruction |= inst.operands[2].reg;
10426 inst.instruction |= inst.operands[3].reg << 8;
10428 if (inst.operands[0].reg == inst.operands[1].reg)
10439 inst.instruction |= inst.operands[0].reg << 16;
10440 inst.instruction |= inst.operands[1].reg;
10441 inst.instruction |= inst.operands[2].reg << 8;
10452 if (inst.operands[0].present)
10454 reg = inst.operands[0].reg;
10460 inst.instruction |= reg << 16;
10461 inst.instruction |= inst.operands[1].imm;
10462 if (inst.operands[0].writeback || inst.operands[1].writeback)
10463 inst.instruction |= WRITE_BACK;
10471 constraint (!inst.operands[2].isreg || !inst
10472 || inst.operands[2].postind || inst.operands[2].writeback
10473 || inst.operands[2].immisreg || inst.operands[2].shifted
10474 || inst.operands[2].negative
10476 || (inst.operands[2].reg == REG_PC),
10479 constraint (inst.operands[0].reg == inst.operands[1].reg
10480 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10482 constraint (inst.relocs[0].exp.X_op != O_constant
10483 || inst.relocs[0].exp.X_add_number != 0,
10486 inst.instruction |= inst.operands[0].reg << 12;
10487 inst.instruction |= inst.operands[1].reg;
10488 inst.instruction |= inst.operands[2].reg << 16;
10489 inst.relocs[0].type = BFD_RELOC_UNUSED;
10495 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10496 || inst.operands[2].postind || inst.operands[2].writeback
10497 || inst.operands[2].immisreg || inst.operands[2].shifted
10498 || inst.operands[2].negative,
10501 constraint (inst.operands[0].reg == inst.operands[1].reg
10502 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10510 constraint (inst.operands[1].reg % 2 != 0,
10512 constraint (inst.operands[2].present
10513 && inst.operands[2].reg != inst.operands[1].reg + 1,
10517 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
10519 constraint (inst.operands[0].reg == inst.operands[1].reg
10520 || inst.operands[0].reg == inst.operands[1].reg + 1
10521 || inst.operands[0].reg == inst.operands[3].reg,
10524 inst.instruction |= inst.operands[0].reg << 12;
10525 inst.instruction |= inst.operands[1].reg;
10526 inst.instruction |= inst.operands[3].reg << 16;
10533 constraint (inst.operands[0].reg == inst.operands[1].reg
10534 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10542 constraint (inst.operands[0].reg == inst.operands[1].reg
10543 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10559 inst.instruction |= inst.operands[0].reg << 12;
10560 inst.instruction |= inst.operands[1].reg << 16;
10561 inst.instruction |= inst.operands[2].reg;
10562 inst.instruction |= inst.operands[3].imm << 10;
10574 inst.instruction |= inst.operands[0].reg << 12;
10575 inst.instruction |= inst.operands[1].reg;
10576 inst.instruction |= inst.operands[2].imm << 10;
10590 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10591 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
10597 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10598 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
10599 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
10605 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10611 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10612 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
10618 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10619 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
10629 inst.instruction |= inst.operands[0].reg << 12;
10630 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
10636 constraint (inst.operands[2].imm != 2,
10638 inst.instruction |= inst.operands[0].reg << 12;
10639 inst.instruction |= inst.operands[1].reg << 16;
10640 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
10650 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
10651 inst.instruction |= inst.operands[1].reg << 12;
10657 constraint (inst.operands[0].imm != 2,
10659 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
10660 inst.instruction |= inst.operands[1].reg << 12;
10661 inst.instruction |= inst.operands[2].reg << 16;
10667 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10674 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10682 if (inst.operands[0].writeback)
10683 inst.instruction |= WRITE_BACK;
10687 inst.instruction |= inst.operands[0].reg << 16;
10688 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
10689 inst.instruction |= inst.operands[1].imm;
10697 if (inst.operands[0].writeback)
10698 inst.instruction |= WRITE_BACK;
10703 inst.instruction |= inst.operands[0].reg << 16;
10704 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10706 count = inst.operands[1].imm << 1;
10710 inst.instruction |= count;
10756 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10757 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
10763 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
10764 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10770 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10771 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
10781 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10782 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
10783 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
10789 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10799 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
10800 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10801 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
10808 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10809 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
10810 inst.instruction |= (inst.operands[1].imm & 0x0f);
10816 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10817 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
10818 inst.instruction |= (inst.operands[1].imm & 0x0f);
10824 int immbits = srcsize - inst.operands[1].imm;
10828 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10830 inst.error = _("immediate value out of range, expected range [0, 16]");
10835 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10837 inst.error = _("immediate value out of range, expected range [1, 32]");
10841 inst.instruction |= (immbits & 1) << 5;
10842 inst.instruction |= (immbits >> 1);
10848 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10855 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10862 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10869 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10879 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
10885 inst.instruction |= inst.operands[0].reg << 12;
10886 inst.instruction |= inst.operands[1].imm;
10892 inst.instruction |= inst.operands[0].reg << 12;
10893 inst.instruction |= inst.operands[1].reg << 16;
10894 inst.instruction |= inst.operands[2].imm;
10900 inst.instruction |= inst.operands[0].reg << 16;
10901 inst.instruction |= inst.operands[1].reg << 12;
10902 inst.instruction |= inst.operands[2].imm;
10908 inst.instruction |= inst.operands[0].reg << 5;
10909 inst.instruction |= inst.operands[1].reg;
10910 inst.instruction |= inst.operands[2].reg << 12;
10916 inst.instruction |= inst.operands[0].reg << 12;
10917 inst.instruction |= inst.operands[1].reg << 16;
10918 inst.instruction |= inst.operands[2].reg;
10919 inst.instruction |= inst.operands[3].imm << 20;
10925 inst.instruction |= inst.operands[0].reg << 12;
10926 inst.instruction |= inst.operands[1].reg << 16;
10927 inst.instruction |= inst.operands[2].reg;
10928 inst.instruction |= inst.operands[3].imm << 21;
10935 inst.instruction |= inst.operands[0].reg << 12;
10936 inst.instruction |= inst.operands[1].reg << 16;
10937 inst.instruction |= inst.operands[1].reg;
10944 inst.instruction |= inst.operands[0].reg << 12;
10956 if (!inst.operands[0].isreg)
10958 constraint (inst.cond != COND_ALWAYS, BAD_COND);
10959 inst.instruction |= 0xf0000000;
10962 inst.instruction |= inst.operands[0].reg << 12;
10969 inst.instruction |= inst.operands[0].reg << 12;
10971 && inst.operands[1].immisreg)
10973 inst.instruction &= ~0x1a000ff;
10974 inst.instruction |= (0xfU << 28);
10975 if (inst.operands[1].preind)
10976 inst.instruction |= PRE_INDEX;
10977 if (!inst.operands[1].negative)
10978 inst.instruction |= INDEX_UP;
10979 if (inst.operands[1].writeback)
10980 inst.instruction |= WRITE_BACK;
10981 inst.instruction |= inst.operands[1].reg << 16;
10982 inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
10983 inst.instruction |= inst.operands[1].imm;
10992 inst.instruction |= inst.operands[0].reg << 12;
10993 inst.instruction |= inst.operands[1].reg << 16;
10994 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
10995 inst.instruction |= (inst.operands[2].imm & 0x0f);
11002 inst.instruction |= inst.operands[0].reg;
11003 inst.instruction |= inst.operands[0].reg << 12;
11004 inst.instruction |= inst.operands[0].reg << 16;
11010 if (inst.operands[2].isreg)
11016 if (inst.operands[2].imm == 0)
11018 switch ((inst.instruction >> 20) & 0xf)
11025 inst.operands[2].imm = 16;
11026 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
11033 inst.operands[2].imm = 32;
11034 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
11043 wrn = (inst.instruction >> 16) & 0xf;
11044 inst.instruction &= 0xff0fff0f;
11045 inst.instruction |= wrn;
11052 inst.operands[2].imm &= 0x1f;
11053 inst.instruction |= (0xfU << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
11070 inst.instruction |= inst.operands[1].reg;
11071 inst.instruction |= inst.operands[2].reg << 12;
11081 inst.instruction |= inst.operands[1].reg << 12;
11082 inst.instruction |= inst.operands[2].reg << 16;
11092 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
11093 inst.instruction |= inst.operands[0].reg << 12;
11094 inst.instruction |= inst.operands[1].reg << 16;
11100 /* inst.operands[i] is a shifted-register operand; encode
11101 it into inst.instruction in the format used by Thumb32. */
11106 unsigned int value = inst.relocs[0].exp.X_add_number;
11107 unsigned int shift = inst.operands[i].shift_kind;
11109 constraint (inst.operands[i].immisreg,
11111 inst.instruction |= inst.operands[i].reg;
11113 inst.instruction |= SHIFT_ROR << 4;
11116 constraint (inst.relocs[0].exp.X_op != O_constant,
11129 inst.instruction |= shift << 4;
11130 inst.instruction |= (value & 0x1c) << 10;
11131 inst.instruction |= (value & 0x03) << 6;
11136 /* inst.operands[i] was set up by parse_address. Encode it into a
11146 const bool is_pc = (inst.operands[i].reg == REG_PC);
11148 constraint (!inst.operands[i].isreg,
11151 inst.instruction |= inst.operands[i].reg << 16;
11152 if (inst.operands[i].immisreg)
11156 constraint (inst.operands[i].negative,
11158 constraint (inst.operands[i].postind,
11160 constraint (inst.operands[i].writeback,
11162 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
11165 inst.instruction |= inst.operands[i].imm;
11166 if (inst.operands[i].shifted)
11168 constraint (inst.relocs[0].exp.X_op != O_constant,
11170 constraint (inst.relocs[0].exp.X_add_number < 0
11171 || inst.relocs[0].exp.X_add_number > 3,
11173 inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
11175 inst.relocs[0].type = BFD_RELOC_UNUSED;
11177 else if (inst.operands[i].preind)
11179 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
11180 constraint (is_t && inst.operands[i].writeback,
11182 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
11187 inst.instruction |= 0x01000000;
11188 if (inst.operands[i].writeback)
11189 inst.instruction |= 0x00200000;
11193 inst.instruction |= 0x00000c00;
11194 if (inst.operands[i].writeback)
11195 inst.instruction |= 0x00000100;
11197 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
11199 else if (inst.operands[i].postind)
11201 gas_assert (inst.operands[i].writeback);
11206 inst.instruction |= 0x00200000;
11208 inst.instruction |= 0x00000900;
11209 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
11212 inst.error = _("instruction does not accept unindexed addressing");
11357 Rd = inst.operands[0].reg;
11358 Rn = inst.operands[1].reg;
11367 inst.instruction |= (Rn << 16) | (Rd << 8);
11368 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
11371 /* Parse an add or subtract instruction. We get here with inst.instruction
11379 Rd = inst.operands[0].reg;
11380 Rs = (inst.operands[1].present
11381 ? inst.operands[1].reg /* Rd, Rs, foo */
11382 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11393 flags = (inst.instruction == T_MNEM_adds
11394 || inst.instruction == T_MNEM_subs);
11399 if (!inst.operands[2].isreg)
11406 add = (inst.instruction == T_MNEM_add
11407 || inst.instruction == T_MNEM_adds);
11409 if (inst.size_req != 4)
11428 inst.instruction = THUMB_OP16(opcode);
11429 inst.instruction |= (Rd << 4) | Rs;
11430 if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11431 || (inst.relocs[0].type
11434 if (inst.size_req == 2)
11435 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11437 inst.relax = opcode;
11441 constraint (inst.size_req == 2, _("cannot honor width suffix"));
11443 if (inst.size_req == 4
11444 || (inst.size_req != 2 && !opcode))
11446 constraint ((inst.relocs[0].type
11448 && (inst.relocs[0].type
11454 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
11456 constraint (inst.relocs[0].exp.X_op != O_constant,
11458 constraint (inst.relocs[0].exp.X_add_number < 0
11459 || inst.relocs[0].exp.X_add_number > 0xff,
11461 inst.instruction = T2_SUBS_PC_LR
11462 | inst.relocs[0].exp.X_add_number;
11463 inst.relocs[0].type = BFD_RELOC_UNUSED;
11469 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
11470 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
11474 inst.instruction = THUMB_OP32 (inst.instruction);
11475 inst.instruction = (inst.instruction & 0xe1ffffff)
11478 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
11480 inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_IMM;
11482 inst.instruction |= Rd << 8;
11483 inst.instruction |= Rs << 16;
11488 unsigned int value = inst.relocs[0].exp.X_add_number;
11489 unsigned int shift = inst.operands[2].shift_kind;
11491 Rn = inst.operands[2].reg;
11493 if (!inst.operands[2].shifted && inst.size_req != 4)
11500 inst.instruction = ((inst.instruction == T_MNEM_adds
11501 || inst.instruction == T_MNEM_add)
11504 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
11508 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
11521 inst.instruction = T_OPCODE_ADD_HI;
11522 inst.instruction |= (Rd & 8) << 4;
11523 inst.instruction |= (Rd & 7);
11524 inst.instruction |= Rn << 3;
11537 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
11539 inst.instruction = THUMB_OP32 (inst.instruction);
11540 inst.instruction |= Rd << 8;
11541 inst.instruction |= Rs << 16;
11551 constraint (inst.instruction == T_MNEM_adds
11552 || inst.instruction == T_MNEM_subs,
11555 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
11561 inst.instruction = (inst.instruction == T_MNEM_add
11563 inst.instruction |= (Rd << 4) | Rs;
11564 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11568 Rn = inst.operands[2].reg;
11569 constraint (inst.operands[2].shifted, _("unshifted register required"));
11575 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
11576 inst.instruction = T_OPCODE_ADD_HI;
11577 inst.instruction |= (Rd & 8) << 4;
11578 inst.instruction |= (Rd & 7);
11580 inst.instruction |= Rn << 3;
11582 inst.instruction |= Rs << 3;
11588 inst.instruction = (inst.instruction == T_MNEM_add
11590 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
11600 Rd = inst.operands[0].reg;
11603 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
11606 inst.relax = inst.instruction;
11607 inst.instruction = THUMB_OP16 (inst.instruction);
11608 inst.instruction |= Rd << 4;
11610 else if (unified_syntax && inst.size_req != 2)
11613 inst.instruction = THUMB_OP32 (inst.instruction);
11614 inst.instruction |= Rd << 8;
11615 inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_PC12;
11616 inst.relocs[0].pc_rel = 1;
11621 inst.instruction = THUMB_OP16 (inst.instruction);
11622 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11623 inst.relocs[0].exp.X_add_number -= 4; /* PC relative adjust. */
11624 inst.relocs[0].pc_rel = 1;
11625 inst.instruction |= Rd << 4;
11628 if (inst.relocs[0].exp.X_op == O_symbol
11629 && inst.relocs[0].exp.X_add_symbol != NULL
11630 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
11631 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
11632 inst.relocs[0].exp.X_add_number += 1;
11646 Rd = inst.operands[0].reg;
11647 Rs = (inst.operands[1].present
11648 ? inst.operands[1].reg /* Rd, Rs, foo */
11649 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11650 Rn = inst.operands[2].reg;
11654 if (inst.operands[2].isreg)
11659 if (!inst.operands[2].isreg)
11663 inst.instruction = THUMB_OP32 (inst.instruction);
11664 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11665 inst.instruction |= Rd << 8;
11666 inst.instruction |= Rs << 16;
11667 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
11674 if (THUMB_SETS_FLAGS (inst.instruction))
11681 if (inst.operands[2].shifted)
11683 if (inst.size_req == 4)
11689 inst.instruction = THUMB_OP16 (inst.instruction);
11690 inst.instruction |= Rd;
11691 inst.instruction |= Rn << 3;
11696 constraint (inst.operands[2].shifted
11697 && inst.operands[2].immisreg,
11699 inst.instruction = THUMB_OP32 (inst.instruction);
11700 inst.instruction |= Rd << 8;
11701 inst.instruction |= Rs << 16;
11710 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11712 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
11718 inst.instruction = THUMB_OP16 (inst.instruction);
11719 inst.instruction |= Rd;
11720 inst.instruction |= Rn << 3;
11734 Rd = inst.operands[0].reg;
11735 Rs = (inst.operands[1].present
11736 ? inst.operands[1].reg /* Rd, Rs, foo */
11737 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11738 Rn = inst.operands[2].reg;
11742 if (inst.operands[2].isreg)
11747 if (!inst.operands[2].isreg)
11751 inst.instruction = THUMB_OP32 (inst.instruction);
11752 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11753 inst.instruction |= Rd << 8;
11754 inst.instruction |= Rs << 16;
11755 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
11762 if (THUMB_SETS_FLAGS (inst.instruction))
11769 if (inst.operands[2].shifted)
11771 if (inst.size_req == 4)
11778 inst.instruction = THUMB_OP16 (inst.instruction);
11779 inst.instruction |= Rd;
11780 inst.instruction |= Rn << 3;
11785 inst.instruction = THUMB_OP16 (inst.instruction);
11786 inst.instruction |= Rd;
11787 inst.instruction |= Rs << 3;
11793 constraint (inst.operands[2].shifted
11794 && inst.operands[2].immisreg,
11796 inst.instruction = THUMB_OP32 (inst.instruction);
11797 inst.instruction |= Rd << 8;
11798 inst.instruction |= Rs << 16;
11807 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11809 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
11813 inst.instruction = THUMB_OP16 (inst.instruction);
11814 inst.instruction |= Rd;
11817 inst.instruction |= Rn << 3;
11819 inst.instruction |= Rs << 3;
11829 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
11833 Rd = inst.operands[0].reg;
11835 inst.instruction |= Rd << 8;
11836 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
11837 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
11838 inst.instruction |= msb - 1;
11847 Rd = inst.operands[0].reg;
11852 if (!inst.operands[1].isreg)
11856 Rn = inst.operands[1].reg;
11860 msb = inst.operands[2].imm + inst.operands[3].imm;
11864 inst.instruction |= Rd << 8;
11865 inst.instruction |= Rn << 16;
11866 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
11867 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
11868 inst.instruction |= msb - 1;
11876 Rd = inst.operands[0].reg;
11877 Rn = inst.operands[1].reg;
11882 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
11884 inst.instruction |= Rd << 8;
11885 inst.instruction |= Rn << 16;
11886 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
11887 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
11888 inst.instruction |= inst.operands[3].imm - 1;
11896 into inst.instruction.
11906 if (inst.operands[0].isreg)
11908 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
11910 inst.instruction |= inst.operands[0].reg << 3;
11915 inst.instruction = 0xf000e800;
11927 cond = inst.cond;
11937 cond = inst.cond;
11942 opcode = inst.instruction;
11945 && (inst.size_req == 4
11946 || (inst.size_req != 2
11947 && (inst.operands[0].hasreloc
11948 || inst.relocs[0].exp.X_op == O_constant))))
11950 inst.instruction = THUMB_OP32(opcode);
11960 inst.instruction |= cond << 22;
11966 inst.instruction = THUMB_OP16(opcode);
11971 inst.instruction |= cond << 8;
11975 if (unified_syntax && inst.size_req != 2)
11976 inst.relax = opcode;
11978 inst.relocs[0].type = reloc;
11979 inst.relocs[0].pc_rel = 1;
11988 constraint (inst.cond != COND_ALWAYS,
11990 if (inst.operands[0].present)
11992 constraint (inst.operands[0].imm > range,
11994 inst.instruction |= inst.operands[0].imm;
12023 if (inst.relocs[0].type == BFD_RELOC_32_PLT_PCREL)
12024 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH23;
12031 if ( inst.relocs[0].exp.X_op == O_symbol
12032 && inst.relocs[0].exp.X_add_symbol != NULL
12033 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
12034 && ! THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
12035 inst.relocs[0].exp.X_add_symbol
12036 = find_real_start (inst.relocs[0].exp.X_add_symbol);
12044 inst.instruction |= inst.operands[0].reg << 3;
12056 Rm = inst.operands[0].reg;
12058 inst.instruction |= Rm << 16;
12067 Rd = inst.operands[0].reg;
12068 Rm = inst.operands[1].reg;
12073 inst.instruction |= Rd << 8;
12074 inst.instruction |= Rm << 16;
12075 inst.instruction |= Rm;
12085 constraint (inst.cond != COND_ALWAYS, BAD_COND);
12087 Rd = inst.operands[0].reg;
12088 switch (inst.instruction)
12094 Rn = inst.operands[1].reg;
12095 Rm = inst.operands[2].reg;
12096 cond = inst.operands[3].imm;
12104 Rn = inst.operands[1].reg;
12105 cond = inst.operands[2].imm;
12114 cond = inst.operands[1].imm;
12125 inst.instruction = THUMB_OP32 (inst.instruction);
12126 inst.instruction |= Rd << 8;
12127 inst.instruction |= Rn << 16;
12128 inst.instruction |= Rm;
12129 inst.instruction |= cond << 4;
12142 inst.instruction |= inst.operands[0].imm;
12150 && (inst.operands[1].present || inst.size_req == 4)
12153 unsigned int imod = (inst.instruction & 0x0030) >> 4;
12154 inst.instruction = 0xf3af8000;
12155 inst.instruction |= imod << 9;
12156 inst.instruction |= inst.operands[0].imm << 5;
12157 if (inst.operands[1].present)
12158 inst.instruction |= 0x100 | inst.operands[1].imm;
12163 && (inst.operands[0].imm & 4),
12166 constraint (inst.operands[1].present || inst.size_req == 4,
12169 inst.instruction |= inst.operands[0].imm;
12178 if (inst.size_req == 4)
12180 inst.instruction = THUMB_OP32 (T_MNEM_mov);
12181 inst.instruction |= inst.operands[0].reg << 8;
12182 inst.instruction |= inst.operands[1].reg;
12186 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
12187 inst.instruction |= (inst.operands[0].reg & 0x7);
12188 inst.instruction |= inst.operands[1].reg << 3;
12196 constraint (inst.operands[0].reg > 7, BAD_HIREG);
12197 inst.instruction |= inst.operands[0].reg;
12198 inst.relocs[0].pc_rel = 1;
12199 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH7;
12205 inst.instruction |= inst.operands[0].imm;
12213 Rd = inst.operands[0].reg;
12214 Rn = (inst.operands[1].present
12215 ? inst.operands[1].reg : Rd);
12216 Rm = inst.operands[2].reg;
12222 inst.instruction |= Rd << 8;
12223 inst.instruction |= Rn << 16;
12224 inst.instruction |= Rm;
12230 if (unified_syntax && inst.size_req == 4)
12231 inst.instruction = THUMB_OP32 (inst.instruction);
12233 inst.instruction = THUMB_OP16 (inst.instruction);
12239 unsigned int cond = inst.operands[0].imm;
12242 now_pred.mask = (inst.instruction & 0xf) | 0x10;
12250 unsigned int mask = inst.instruction & 0x000f;
12273 inst.instruction &= 0xfff0;
12274 inst.instruction |= mask;
12277 inst.instruction |= cond << 4;
12288 load = do_io && ((inst.instruction & (1 << 20)) != 0);
12292 inst.error = _("SP not allowed in register list");
12296 inst.error = _("having the base register in the register list when "
12304 inst.error = _("LR and PC should not both be in register list");
12312 inst.error = _("PC not allowed in register list");
12320 if (inst.instruction & (1 << 23))
12321 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
12323 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
12327 if (inst.instruction & (1 << 23))
12328 inst.instruction = 0x00800000; /* ia -> [base] */
12330 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
12333 inst.instruction |= 0xf8400000;
12335 inst.instruction |= 0x00100000;
12341 inst.instruction |= WRITE_BACK;
12343 inst.instruction |= mask;
12345 inst.instruction |= base << 16;
12354 constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
12356 constraint (inst.operands[1].writeback,
12367 if (inst.operands[0].reg == REG_SP)
12370 if (inst.operands[0].writeback
12371 && (inst.instruction == T_OPCODE_STMFD /* Push. */
12372 || inst.instruction == T_MNEM_ldmia)) /* Pop. */
12374 inst.instruction = (inst.instruction == T_MNEM_ldmia
12377 inst.operands[0] = inst.operands[1];
12382 if (!inst.operands[0].writeback
12383 && (inst.instruction == T_MNEM_stmia
12384 || inst.instruction == T_MNEM_ldmia)
12385 && (inst.operands[1].imm & (inst.operands[1].imm - 1)) == 0)
12388 if (inst.instruction == T_MNEM_ldmia)
12390 inst.instruction = THUMB_OP16 (opcode);
12391 inst.instruction |= ((ffs (inst.operands[1].imm) - 1) << 8);
12397 else if (inst.size_req != 4
12398 && (inst.instruction == T_MNEM_ldmia
12399 || inst.instruction == T_MNEM_stmia)
12400 && inst.operands[0].reg <= 7
12401 && !(inst.operands[1].imm & ~0xff))
12404 if (!inst.operands[0].writeback
12405 && (inst.operands[1].imm & (inst.operands[1].imm - 1)) == 0)
12408 if (inst.instruction == T_MNEM_stmia)
12411 inst.instruction = THUMB_OP16 (opcode);
12412 inst.instruction |= inst.operands[0].reg << 3;
12413 inst.instruction |= (ffs (inst.operands[1].imm) - 1);
12419 mask = 1 << inst.operands[0].reg;
12424 if (inst.instruction == T_MNEM_stmia
12425 ? inst.operands[0].writeback
12426 : (inst.operands[0].writeback
12427 == !(inst.operands[1].imm & mask)))
12432 if (inst.instruction == T_MNEM_stmia
12433 && (inst.operands[1].imm & mask)
12434 && (inst.operands[1].imm & (mask - 1)))
12436 inst.operands[0].reg);
12438 inst.instruction = THUMB_OP16 (inst.instruction);
12439 inst.instruction |= inst.operands[0].reg << 8;
12440 inst.instruction |= inst.operands[1].imm;
12448 if (inst.instruction < 0xffff)
12449 inst.instruction = THUMB_OP32 (inst.instruction);
12451 encode_thumb2_multi (true /* do_io */, inst.operands[0].reg,
12452 inst.operands[1].imm,
12453 inst.operands[0].writeback);
12458 constraint (inst.operands[0].reg > 7
12459 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
12460 constraint (inst.instruction != T_MNEM_ldmia
12461 && inst.instruction != T_MNEM_stmia,
12463 if (inst.instruction == T_MNEM_stmia)
12465 if (!inst.operands[0].writeback)
12467 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
12468 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
12470 inst.operands[0].reg);
12474 if (!inst.operands[0].writeback
12475 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
12477 else if (inst.operands[0].writeback
12478 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
12482 inst.instruction = THUMB_OP16 (inst.instruction);
12483 inst.instruction |= inst.operands[0].reg << 8;
12484 inst.instruction |= inst.operands[1].imm;
12491 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
12492 || inst.operands[1].postind || inst.operands[1].writeback
12493 || inst.operands[1].immisreg || inst.operands[1].shifted
12494 || inst.operands[1].negative,
12497 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
12499 inst.instruction |= inst.operands[0].reg << 12;
12500 inst.instruction |= inst.operands[1].reg << 16;
12501 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
12507 if (!inst.operands[1].present)
12509 constraint (inst.operands[0].reg == REG_LR,
12512 inst.operands[1].reg = inst.operands[0].reg + 1;
12514 constraint (inst.operands[0].reg == inst.operands[1].reg,
12517 inst.instruction |= inst.operands[0].reg << 12;
12518 inst.instruction |= inst.operands[1].reg << 8;
12519 inst.instruction |= inst.operands[2].reg << 16;
12528 if (inst.operands[0].isreg
12529 && !inst.operands[0].preind
12530 && inst.operands[0].reg == REG_PC)
12533 opcode = inst.instruction;
12536 if (!inst.operands[1].isreg)
12539 inst.instruction = THUMB_OP32 (opcode);
12543 if (inst.operands[1].isreg
12544 && !inst.operands[1].writeback
12545 && !inst.operands[1].shifted && !inst.operands[1].postind
12546 && !inst.operands[1].negative && inst.operands[0].reg <= 7
12548 && inst.size_req != 4)
12551 Rn = inst.operands[1].reg;
12552 if (inst.operands[1].immisreg)
12554 inst.instruction = THUMB_OP16 (opcode);
12556 if (Rn <= 7 && inst.operands[1].imm <= 7)
12559 reject_bad_reg (inst.operands[1].imm);
12571 if (inst.relocs[0].pc_rel)
12583 inst.instruction = inst.operands[0].reg << 8;
12587 inst.instruction = inst.operands[0].reg;
12588 inst.instruction |= inst.operands[1].reg << 3;
12590 inst.instruction |= THUMB_OP16 (opcode);
12591 if (inst.size_req == 2)
12592 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
12594 inst.relax = opcode;
12602 && inst.operands[0].reg == REG_SP
12603 && inst.operands[1].writeback == 1
12604 && !inst.operands[1].immisreg)
12616 if (inst.operands[1].immisreg)
12617 reject_bad_reg (inst.operands[1].imm);
12619 constraint (inst.operands[1].writeback == 1
12620 && inst.operands[0].reg == inst.operands[1].reg,
12623 inst.instruction = THUMB_OP32 (opcode);
12624 inst.instruction |= inst.operands[0].reg << 12;
12630 constraint (inst.operands[0].reg > 7, BAD_HIREG);
12632 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
12635 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
12636 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
12637 || inst.operands[1].postind || inst.operands[1].shifted
12638 || inst.operands[1].negative,
12640 inst.instruction = THUMB_OP16 (inst.instruction);
12644 inst.instruction = THUMB_OP16 (inst.instruction);
12645 if (!inst.operands[1].isreg)
12649 constraint (!inst.operands[1].preind
12650 || inst.operands[1].shifted
12651 || inst.operands[1].writeback,
12653 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
12655 constraint (inst.instruction & 0x0600,
12657 constraint (inst.operands[1].reg == REG_PC
12658 && !(inst.instruction & THUMB_LOAD_BIT),
12660 constraint (inst.operands[1].immisreg,
12663 if (inst.operands[1].reg == REG_PC)
12664 inst.instruction = T_OPCODE_LDR_PC;
12665 else if (inst.instruction & THUMB_LOAD_BIT)
12666 inst.instruction = T_OPCODE_LDR_SP;
12668 inst.instruction = T_OPCODE_STR_SP;
12670 inst.instruction |= inst.operands[0].reg << 8;
12671 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
12675 constraint (inst.operands[1].reg > 7, BAD_HIREG);
12676 if (!inst.operands[1].immisreg)
12679 inst.instruction |= inst.operands[0].reg;
12680 inst.instruction |= inst.operands[1].reg << 3;
12681 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
12686 constraint (inst.operands[1].imm > 7, BAD_HIREG);
12687 constraint (inst.operands[1].negative,
12691 switch (inst.instruction)
12693 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
12694 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
12695 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
12696 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
12697 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
12698 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
12704 inst.instruction |= inst.operands[0].reg;
12705 inst.instruction |= inst.operands[1].reg << 3;
12706 inst.instruction |= inst.operands[1].imm << 6;
12712 if (!inst.operands[1].present)
12714 inst.operands[1].reg = inst.operands[0].reg + 1;
12715 constraint (inst.operands[0].reg == REG_LR,
12717 constraint (inst.operands[0].reg == REG_R12,
12721 if (inst.operands[2].writeback
12722 && (inst.operands[0].reg == inst.operands[2].reg
12723 || inst.operands[1].reg == inst.operands[2].reg))
12727 inst.instruction |= inst.operands[0].reg << 12;
12728 inst.instruction |= inst.operands[1].reg << 8;
12735 inst.instruction |= inst.operands[0].reg << 12;
12744 Rd = inst.operands[0].reg;
12745 Rn = inst.operands[1].reg;
12746 Rm = inst.operands[2].reg;
12747 Ra = inst.operands[3].reg;
12754 inst.instruction |= Rd << 8;
12755 inst.instruction |= Rn << 16;
12756 inst.instruction |= Rm;
12757 inst.instruction |= Ra << 12;
12765 RdLo = inst.operands[0].reg;
12766 RdHi = inst.operands[1].reg;
12767 Rn = inst.operands[2].reg;
12768 Rm = inst.operands[3].reg;
12775 inst.instruction |= RdLo << 12;
12776 inst.instruction |= RdHi << 8;
12777 inst.instruction |= Rn << 16;
12778 inst.instruction |= Rm;
12786 Rn = inst.operands[0].reg;
12787 Rm = inst.operands[1].reg;
12794 int r0off = (inst.instruction == T_MNEM_mov
12795 || inst.instruction == T_MNEM_movs) ? 8 : 16;
12801 opcode = inst.instruction;
12806 if (inst.size_req == 4
12807 || inst.operands[1].shifted)
12811 if (opcode == T_MNEM_movs && inst.operands[1].isreg
12812 && !inst.operands[1].shifted
12816 inst.instruction = T2_SUBS_PC_LR;
12839 if (inst.operands[1].isreg)
12870 if (!inst.operands[1].isreg)
12877 inst.instruction = THUMB_OP16 (opcode);
12878 inst.instruction |= Rn << 8;
12879 if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12880 || inst.relocs[0].type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
12882 if (inst.size_req == 2)
12883 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
12885 inst.relax = opcode;
12890 constraint ((inst.relocs[0].type
12892 && (inst.relocs[0].type
12896 inst.instruction = THUMB_OP32 (inst.instruction);
12897 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12898 inst.instruction |= Rn << r0off;
12899 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
12902 else if (inst.operands[1].shifted && inst.operands[1].immisreg
12903 && (inst.instruction == T_MNEM_mov
12904 || inst.instruction == T_MNEM_movs))
12907 bool flags = (inst.instruction == T_MNEM_movs);
12914 if (inst.size_req == 4)
12917 if (!low_regs || inst.operands[1].imm > 7)
12923 switch (inst.operands[1].shift_kind)
12941 inst.instruction = opcode;
12944 inst.instruction |= Rn;
12945 inst.instruction |= inst.operands[1].imm << 3;
12950 inst.instruction |= CONDS_BIT;
12952 inst.instruction |= Rn << 8;
12953 inst.instruction |= Rm << 16;
12954 inst.instruction |= inst.operands[1].imm;
12961 if (low_regs && inst.operands[1].shifted
12962 && (inst.instruction == T_MNEM_mov
12963 || inst.instruction == T_MNEM_movs))
12966 narrow = (inst.instruction == T_MNEM_mov);
12968 narrow = (inst.instruction == T_MNEM_movs);
12973 switch (inst.operands[1].shift_kind)
12975 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
12976 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
12977 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
12984 inst.instruction |= Rn;
12985 inst.instruction |= Rm << 3;
12986 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
12990 inst.instruction = THUMB_OP32 (inst.instruction);
12991 inst.instruction |= Rn << r0off;
12996 switch (inst.instruction)
13010 inst.instruction = T_OPCODE_MOV_HR;
13011 inst.instruction |= (Rn & 0x8) << 4;
13012 inst.instruction |= (Rn & 0x7);
13013 inst.instruction |= Rm << 3;
13019 inst.instruction = T_OPCODE_LSL_I;
13020 inst.instruction |= Rn;
13021 inst.instruction |= Rm << 3;
13027 inst.instruction = T_OPCODE_CMP_LR;
13028 inst.instruction |= Rn;
13029 inst.instruction |= Rm << 3;
13033 inst.instruction = T_OPCODE_CMP_HR;
13034 inst.instruction |= (Rn & 0x8) << 4;
13035 inst.instruction |= (Rn & 0x7);
13036 inst.instruction |= Rm << 3;
13043 inst.instruction = THUMB_OP16 (inst.instruction);
13046 constraint (inst.operands[1].shifted,
13049 if (inst.operands[1].isreg)
13055 if (inst.instruction == T_OPCODE_MOV_I8)
13056 inst.instruction = T_OPCODE_ADD_I3;
13058 inst.instruction = T_OPCODE_CMP_LR;
13060 inst.instruction |= Rn;
13061 inst.instruction |= Rm << 3;
13065 if (inst.instruction == T_OPCODE_MOV_I8)
13066 inst.instruction = T_OPCODE_MOV_HR;
13068 inst.instruction = T_OPCODE_CMP_HR;
13076 inst.instruction |= Rn << 8;
13077 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
13088 top = (inst.instruction & 0x00800000) != 0;
13089 if (inst.relocs[0].type == BFD_RELOC_ARM_MOVW)
13092 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVW;
13094 else if (inst.relocs[0].type == BFD_RELOC_ARM_MOVT)
13097 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVT;
13100 Rd = inst.operands[0].reg;
13103 inst.instruction |= Rd << 8;
13104 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
13106 imm = inst.relocs[0].exp.X_add_number;
13107 inst.instruction |= (imm & 0xf000) << 4;
13108 inst.instruction |= (imm & 0x0800) << 15;
13109 inst.instruction |= (imm & 0x0700) << 4;
13110 inst.instruction |= (imm & 0x00ff);
13119 Rn = inst.operands[0].reg;
13120 Rm = inst.operands[1].reg;
13122 if (inst.instruction == T_MNEM_cmp
13123 || inst.instruction == T_MNEM_cmn)
13131 int r0off = (inst.instruction == T_MNEM_mvn
13132 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
13135 if (inst.size_req == 4
13136 || inst.instruction > 0xffff
13137 || inst.operands[1].shifted
13140 else if (inst.instruction == T_MNEM_cmn
13141 || inst.instruction == T_MNEM_tst)
13143 else if (THUMB_SETS_FLAGS (inst.instruction))
13148 if (!inst.operands[1].isreg)
13152 if (inst.instruction < 0xffff)
13153 inst.instruction = THUMB_OP32 (inst.instruction);
13154 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
13155 inst.instruction |= Rn << r0off;
13156 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
13163 inst.instruction = THUMB_OP16 (inst.instruction);
13164 inst.instruction |= Rn;
13165 inst.instruction |= Rm << 3;
13169 constraint (inst.operands[1].shifted
13170 && inst.operands[1].immisreg,
13172 if (inst.instruction < 0xffff)
13173 inst.instruction = THUMB_OP32 (inst.instruction);
13174 inst.instruction |= Rn << r0off;
13181 constraint (inst.instruction > 0xffff
13182 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
13183 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
13188 inst.instruction = THUMB_OP16 (inst.instruction);
13189 inst.instruction |= Rn;
13190 inst.instruction |= Rm << 3;
13202 Rd = inst.operands[0].reg;
13204 inst.instruction |= Rd << 8;
13206 if (inst.operands[1].isreg)
13208 unsigned br = inst.operands[1].reg;
13212 inst.instruction |= br & (0xf << 16);
13213 inst.instruction |= (br & 0x300) >> 4;
13214 inst.instruction |= (br & SPSR_BIT) >> 2;
13218 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
13236 inst.instruction |= (flags & SPSR_BIT) >> 2;
13237 inst.instruction |= inst.operands[1].imm & 0xff;
13238 inst.instruction |= 0xf0000;
13251 constraint (!inst.operands[1].isreg,
13254 if (inst.operands[0].isreg)
13255 flags = (int)(inst.operands[0].reg);
13257 flags = inst.operands[0].imm;
13261 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
13279 Rn = inst.operands[1].reg;
13282 inst.instruction |= (flags & SPSR_BIT) >> 2;
13283 inst.instruction |= (flags & 0xf0000) >> 8;
13284 inst.instruction |= (flags & 0x300) >> 4;
13285 inst.instruction |= (flags & 0xff);
13286 inst.instruction |= Rn << 16;
13295 if (!inst.operands[2].present)
13296 inst.operands[2].reg = inst.operands[0].reg;
13298 Rd = inst.operands[0].reg;
13299 Rn = inst.operands[1].reg;
13300 Rm = inst.operands[2].reg;
13304 if (inst.size_req == 4
13310 else if (inst.instruction == T_MNEM_muls)
13317 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
13326 inst.instruction = THUMB_OP16 (inst.instruction);
13327 inst.instruction |= Rd;
13330 inst.instruction |= Rm << 3;
13332 inst.instruction |= Rn << 3;
13338 constraint (inst.instruction != T_MNEM_mul,
13341 inst.instruction = THUMB_OP32 (inst.instruction);
13342 inst.instruction |= Rd << 8;
13343 inst.instruction |= Rn << 16;
13344 inst.instruction |= Rm << 0;
13357 RdLo = inst.operands[0].reg;
13358 RdHi = inst.operands[1].reg;
13359 Rn = inst.operands[2].reg;
13360 Rm = inst.operands[3].reg;
13367 inst.instruction |= RdLo << 12;
13368 inst.instruction |= RdHi << 8;
13369 inst.instruction |= Rn << 16;
13370 inst.instruction |= Rm;
13383 if (inst.size_req == 4 || inst.operands[0].imm > 15)
13385 inst.instruction = THUMB_OP32 (inst.instruction);
13386 inst.instruction |= inst.operands[0].imm;
13394 inst.instruction = THUMB_OP16 (inst.instruction);
13395 inst.instruction |= inst.operands[0].imm << 4;
13398 inst.instruction = 0x46c0;
13403 constraint (inst.operands[0].present,
13405 inst.instruction = 0x46c0;
13416 if (THUMB_SETS_FLAGS (inst.instruction))
13420 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
13422 if (inst.size_req == 4)
13427 inst.instruction = THUMB_OP32 (inst.instruction);
13428 inst.instruction |= inst.operands[0].reg << 8;
13429 inst.instruction |= inst.operands[1].reg << 16;
13433 inst.instruction = THUMB_OP16 (inst.instruction);
13434 inst.instruction |= inst.operands[0].reg;
13435 inst.instruction |= inst.operands[1].reg << 3;
13440 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
13442 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
13444 inst.instruction = THUMB_OP16 (inst.instruction);
13445 inst.instruction |= inst.operands[0].reg;
13446 inst.instruction |= inst.operands[1].reg << 3;
13455 Rd = inst.operands[0].reg;
13456 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
13462 inst.instruction |= Rd << 8;
13463 inst.instruction |= Rn << 16;
13465 if (!inst.operands[2].isreg)
13467 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
13468 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
13474 Rm = inst.operands[2].reg;
13477 constraint (inst.operands[2].shifted
13478 && inst.operands[2].immisreg,
13489 Rd = inst.operands[0].reg;
13490 Rn = inst.operands[1].reg;
13491 Rm = inst.operands[2].reg;
13497 inst.instruction |= Rd << 8;
13498 inst.instruction |= Rn << 16;
13499 inst.instruction |= Rm;
13500 if (inst.operands[3].present)
13502 inst.relocs[0].exp.X_add_number;
13503 constraint (inst.relocs[0].exp.X_op != O_constant,
13505 inst.instruction |= (val & 0x1c) << 10;
13506 inst.instruction |= (val & 0x03) << 6;
13513 if (!inst.operands[3].present)
13517 inst.instruction &= ~0x00000020;
13520 Rtmp = inst.operands[1].reg;
13521 inst.operands[1].reg = inst.operands[2].reg;
13522 inst.operands[2].reg = Rtmp;
13530 if (inst.operands[0].immisreg)
13531 reject_bad_reg (inst.operands[0].imm);
13541 constraint (inst.operands[0].writeback,
13543 constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
13546 mask = inst.operands[0].imm;
13547 if (inst.size_req != 4 && (mask & ~0xff) == 0)
13548 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
13549 else if (inst.size_req != 4
13550 && (mask & ~0xff) == (1U << (inst.instruction == T_MNEM_push
13553 inst.instruction = THUMB_OP16 (inst.instruction);
13554 inst.instruction |= THUMB_PP_PC_LR;
13555 inst.instruction |= mask & 0xff;
13559 inst.instruction = THUMB_OP32 (inst.instruction);
13564 inst.error = _("invalid register list to push/pop instruction");
13573 encode_thumb2_multi (false /* do_io */, -1, inst.operands[0].imm, false);
13576 inst.error = _("invalid register list to push/pop instruction");
13584 if (inst.operands[0].issingle)
13586 inst.instruction |= (inst.operands[0].reg & 0x1) << 22;
13587 inst.instruction |= (inst.operands[0].reg & 0x1e) << 11;
13588 inst.instruction |= inst.operands[0].imm;
13592 inst.instruction |= (inst.operands[0].reg & 0x10) << 18;
13593 inst.instruction |= (inst.operands[0].reg & 0xf) << 12;
13594 inst.instruction |= 1 << 8;
13595 inst.instruction |= inst.operands[0].imm << 1;
13604 Rd = inst.operands[0].reg;
13605 Rm = inst.operands[1].reg;
13610 inst.instruction |= Rd << 8;
13611 inst.instruction |= Rm << 16;
13612 inst.instruction |= Rm;
13620 Rd = inst.operands[0].reg;
13621 Rm = inst.operands[1].reg;
13627 && inst.size_req != 4)
13629 inst.instruction = THUMB_OP16 (inst.instruction);
13630 inst.instruction |= Rd;
13631 inst.instruction |= Rm << 3;
13635 inst.instruction = THUMB_OP32 (inst.instruction);
13636 inst.instruction |= Rd << 8;
13637 inst.instruction |= Rm << 16;
13638 inst.instruction |= Rm;
13641 inst.error = BAD_HIREG;
13649 Rd = inst.operands[0].reg;
13650 Rm = inst.operands[1].reg;
13655 inst.instruction |= Rd << 8;
13656 inst.instruction |= Rm;
13664 Rd = inst.operands[0].reg;
13665 Rs = (inst.operands[1].present
13666 ? inst.operands[1].reg /* Rd, Rs, foo */
13667 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
13671 if (inst.operands[2].isreg)
13672 reject_bad_reg (inst.operands[2].reg);
13674 inst.instruction |= Rd << 8;
13675 inst.instruction |= Rs << 16;
13676 if (!inst.operands[2].isreg)
13680 if ((inst.instruction & 0x00100000) != 0)
13688 if (inst.size_req == 4 || !unified_syntax)
13691 if (inst.relocs[0].exp.X_op != O_constant
13692 || inst.relocs[0].exp.X_add_number != 0)
13699 inst.relocs[0].type = BFD_RELOC_UNUSED;
13700 inst.instruction = THUMB_OP16 (T_MNEM_negs);
13701 inst.instruction |= Rs << 3;
13702 inst.instruction |= Rd;
13706 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
13707 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
13722 if (inst.operands[0].imm)
13723 inst.instruction |= 0x8;
13729 if (!inst.operands[1].present)
13730 inst.operands[1].reg = inst.operands[0].reg;
13737 switch (inst.instruction)
13750 if (THUMB_SETS_FLAGS (inst.instruction))
13754 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
13756 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
13758 if (inst.operands[2].isreg
13759 && (inst.operands[1].reg != inst.operands[0].reg
13760 || inst.operands[2].reg > 7))
13762 if (inst.size_req == 4)
13765 reject_bad_reg (inst.operands[0].reg);
13766 reject_bad_reg (inst.operands[1].reg);
13770 if (inst.operands[2].isreg)
13772 reject_bad_reg (inst.operands[2].reg);
13773 inst.instruction = THUMB_OP32 (inst.instruction);
13774 inst.instruction |= inst.operands[0].reg << 8;
13775 inst.instruction |= inst.operands[1].reg << 16;
13776 inst.instruction |= inst.operands[2].reg;
13779 constraint (inst.operands[2].shifted,
13784 inst.operands[1].shifted = 1;
13785 inst.operands[1].shift_kind = shift_kind;
13786 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
13788 inst.instruction |= inst.operands[0].reg << 8;
13791 inst.relocs[0].type = BFD_RELOC_UNUSED;
13796 if (inst.operands[2].isreg)
13800 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
13801 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
13802 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
13803 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
13807 inst.instruction |= inst.operands[0].reg;
13808 inst.instruction |= inst.operands[2].reg << 3;
13811 constraint (inst.operands[2].shifted,
13818 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
13819 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
13820 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
13823 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
13824 inst.instruction |= inst.operands[0].reg;
13825 inst.instruction |= inst.operands[1].reg << 3;
13831 constraint (inst.operands[0].reg > 7
13832 || inst.operands[1].reg > 7, BAD_HIREG);
13833 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
13835 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
13837 constraint (inst.operands[2].reg > 7, BAD_HIREG);
13838 constraint (inst.operands[0].reg != inst.operands[1].reg,
13841 switch (inst.instruction)
13843 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
13844 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
13845 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
13846 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
13850 inst.instruction |= inst.operands[0].reg;
13851 inst.instruction |= inst.operands[2].reg << 3;
13854 constraint (inst.operands[2].shifted,
13859 switch (inst.instruction)
13861 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
13862 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
13863 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
13864 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
13867 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
13868 inst.instruction |= inst.operands[0].reg;
13869 inst.instruction |= inst.operands[1].reg << 3;
13879 Rd = inst.operands[0].reg;
13880 Rn = inst.operands[1].reg;
13881 Rm = inst.operands[2].reg;
13887 inst.instruction |= Rd << 8;
13888 inst.instruction |= Rn << 16;
13889 inst.instruction |= Rm;
13897 Rd = inst.operands[0].reg;
13898 Rm = inst.operands[1].reg;
13899 Rn = inst.operands[2].reg;
13905 inst.instruction |= Rd << 8;
13906 inst.instruction |= Rn << 16;
13907 inst.instruction |= Rm;
13913 unsigned int value = inst.relocs[0].exp.X_add_number;
13916 constraint (inst.relocs[0].exp.X_op != O_constant,
13920 inst.relocs[0].type = BFD_RELOC_UNUSED;
13921 inst.instruction |= (value & 0x000f) << 16;
13930 unsigned int value = inst.relocs[0].exp.X_add_number;
13932 inst.relocs[0].type = BFD_RELOC_UNUSED;
13933 inst.instruction |= (value & 0x0fff);
13934 inst.instruction |= (value & 0xf000) << 4;
13942 Rd = inst.operands[0].reg;
13943 Rn = inst.operands[2].reg;
13948 inst.instruction |= Rd << 8;
13949 inst.instruction |= inst.operands[1].imm - bias;
13950 inst.instruction |= Rn << 16;
13952 if (inst.operands[3].present)
13954 offsetT shift_amount = inst.relocs[0].exp.X_add_number;
13956 inst.relocs[0].type = BFD_RELOC_UNUSED;
13958 constraint (inst.relocs[0].exp.X_op != O_constant,
13966 if (inst.operands[3].shift_kind == SHIFT_ASR)
13967 inst.instruction |= 0x00200000; /* sh bit. */
13969 inst.instruction |= (shift_amount & 0x1c) << 10;
13970 inst.instruction |= (shift_amount & 0x03) << 6;
13986 Rd = inst.operands[0].reg;
13987 Rn = inst.operands[2].reg;
13992 inst.instruction |= Rd << 8;
13993 inst.instruction |= inst.operands[1].imm - 1;
13994 inst.instruction |= Rn << 16;
14000 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
14001 || inst.operands[2].postind || inst.operands[2].writeback
14002 || inst.operands[2].immisreg || inst.operands[2].shifted
14003 || inst.operands[2].negative,
14006 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
14008 inst.instruction |= inst.operands[0].reg << 8;
14009 inst.instruction |= inst.operands[1].reg << 12;
14010 inst.instruction |= inst.operands[2].reg << 16;
14011 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
14017 if (!inst.operands[2].present)
14018 inst.operands[2].reg = inst.operands[1].reg + 1;
14020 constraint (inst.operands[0].reg == inst.operands[1].reg
14021 || inst.operands[0].reg == inst.operands[2].reg
14022 || inst.operands[0].reg == inst.operands[3].reg,
14025 inst.instruction |= inst.operands[0].reg;
14026 inst.instruction |= inst.operands[1].reg << 12;
14027 inst.instruction |= inst.operands[2].reg << 8;
14028 inst.instruction |= inst.operands[3].reg << 16;
14036 Rd = inst.operands[0].reg;
14037 Rn = inst.operands[1].reg;
14038 Rm = inst.operands[2].reg;
14044 inst.instruction |= Rd << 8;
14045 inst.instruction |= Rn << 16;
14046 inst.instruction |= Rm;
14047 inst.instruction |= inst.operands[3].imm << 4;
14055 Rd = inst.operands[0].reg;
14056 Rm = inst.operands[1].reg;
14061 if (inst.instruction <= 0xffff
14062 && inst.size_req != 4
14064 && (!inst.operands[2].present || inst.operands[2].imm == 0))
14066 inst.instruction = THUMB_OP16 (inst.instruction);
14067 inst.instruction |= Rd;
14068 inst.instruction |= Rm << 3;
14072 if (inst.instruction <= 0xffff)
14073 inst.instruction = THUMB_OP32 (inst.instruction);
14074 inst.instruction |= Rd << 8;
14075 inst.instruction |= Rm;
14076 inst.instruction |= inst.operands[2].imm << 4;
14080 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
14089 inst.relocs[0].type = BFD_RELOC_ARM_SWI;
14098 half = (inst.instruction & 0x10) != 0;
14100 constraint (inst.operands[0].immisreg,
14103 Rn = inst.operands[0].reg;
14104 Rm = inst.operands[0].imm;
14110 constraint (!half && inst.operands[0].shifted,
14112 inst.instruction |= (Rn << 16) | Rm;
14118 if (!inst.operands[0].present)
14119 inst.operands[0].imm = 0;
14121 if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4)
14123 constraint (inst.size_req == 2,
14125 inst.instruction = THUMB_OP32 (inst.instruction);
14126 inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4;
14127 inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0;
14131 inst.instruction = THUMB_OP16 (inst.instruction);
14132 inst.instruction |= inst.operands[0].imm;
14150 Rd = inst.operands[0].reg;
14151 Rn = inst.operands[2].reg;
14156 inst.instruction |= Rd << 8;
14157 inst.instruction |= inst.operands[1].imm;
14158 inst.instruction |= Rn << 16;
14185 unsigned long insn = inst.instruction;
14187 inst.instruction = THUMB_OP32 (inst.instruction);
14188 if (inst.operands[0].hasreloc == 0)
14190 if (v8_1_branch_value_check (inst.operands[0].imm, 5, false) == FAIL)
14193 inst.instruction |= ((inst.operands[0].imm & 0x1f) >> 1) << 23;
14197 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH5;
14198 inst.relocs[0].pc_rel = 1;
14204 if (inst.operands[1].hasreloc == 0)
14206 int val = inst.operands[1].imm;
14207 if (v8_1_branch_value_check (inst.operands[1].imm, 17, true) == FAIL)
14213 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14217 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF17;
14218 inst.relocs[1].pc_rel = 1;
14223 if (inst.operands[1].hasreloc == 0)
14225 int val = inst.operands[1].imm;
14226 if (v8_1_branch_value_check (inst.operands[1].imm, 19, true) == FAIL)
14232 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14236 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF19;
14237 inst.relocs[1].pc_rel = 1;
14243 if (inst.operands[1].hasreloc == 0)
14245 int val = inst.operands[1].imm;
14249 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14253 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF13;
14254 inst.relocs[1].pc_rel = 1;
14258 if (inst.operands[2].hasreloc == 0)
14260 constraint ((inst.operands[0].hasreloc != 0), BAD_ARGS);
14261 int val2 = inst.operands[2].imm;
14262 int val0 = inst.operands[0].imm & 0x1f;
14265 inst.instruction |= 1 << 17; /* T bit. */
14271 constraint ((inst.operands[0].hasreloc == 0), BAD_ARGS);
14272 inst.relocs[2].type = BFD_RELOC_THUMB_PCREL_BFCSEL;
14273 inst.relocs[2].pc_rel = 1;
14277 constraint (inst.cond != COND_ALWAYS, BAD_COND);
14278 inst.instruction |= (inst.operands[3].imm & 0xf) << 18;
14283 inst.instruction |= inst.operands[1].reg << 16;
14294 if (inst.relocs[0].exp.X_op == O_constant)
14296 int value = inst.relocs[0].exp.X_add_number;
14307 inst.instruction |= (imml << 11) | (immh << 1);
14311 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_LOOP12;
14312 inst.relocs[0].pc_rel = 1;
14320 unsigned int value = inst.operands[2].imm;
14322 inst.instruction |= inst.operands[0].reg << 16;
14323 inst.instruction |= inst.operands[1].reg << 8;
14326 inst.instruction |= ((value == 64) ? 0: 1) << 7;
14329 constraint (inst.operands[3].reg == inst.operands[0].reg, BAD_OVERLAP);
14330 constraint (inst.operands[3].reg == inst.operands[1].reg, BAD_OVERLAP);
14331 inst.instruction |= inst.operands[3].reg << 12;
14338 if (!inst.operands[2].present)
14340 inst.operands[2] = inst.operands[1];
14341 inst.operands[1].reg = 0xf;
14344 inst.instruction |= inst.operands[0].reg << 16;
14345 inst.instruction |= inst.operands[1].reg << 8;
14347 if (inst.operands[2].isreg)
14350 constraint (inst.operands[2].reg == inst.operands[0].reg, BAD_OVERLAP);
14351 constraint (inst.operands[2].reg == inst.operands[1].reg, BAD_OVERLAP);
14352 inst.instruction |= inst.operands[2].reg << 12;
14357 unsigned int value = inst.operands[2].imm;
14358 inst.instruction |= (value & 0x1c) << 10;
14359 inst.instruction |= (value & 0x03) << 6;
14361 inst.instruction |= 0x2;
14578 #define NEON_ENCODE(type, inst) \
14581 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14582 inst.is_neon = 1; \
14589 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14863 if (!inst.operands[1].present)
14864 inst.operands[1] = inst.operands[0];
14875 if (!inst.operands[j].present)
14888 information is stored in inst.vectype. If the type specifier
14890 in inst.operands[].vectype.
14909 if (!(inst.operands[j].isreg
14910 && inst.operands[j].isvec
14911 && inst.operands[j].issingle
14912 && !inst.operands[j].isquad
14913 && ((inst.vectype.elems == 1
14914 && inst.vectype.el[0].size == 16)
14915 || (inst.vectype.elems > 1
14916 && inst.vectype.el[j].size == 16)
14917 || (inst.vectype.elems == 0
14918 && inst.operands[j].vectype.type != NT_invtype
14919 && inst.operands[j].vectype.size == 16))))
14924 if (!(inst.operands[j].isreg
14925 && inst.operands[j].isvec
14926 && inst.operands[j].issingle
14927 && !inst.operands[j].isquad
14928 && ((inst.vectype.elems == 1 && inst.vectype.el[0].size == 32)
14929 || (inst.vectype.elems > 1 && inst.vectype.el[j].size == 32)
14930 || (inst.vectype.elems == 0
14931 && (inst.operands[j].vectype.size == 32
14932 || inst.operands[j].vectype.type == NT_invtype)))))
14937 if (!(inst.operands[j].isreg
14938 && inst.operands[j].isvec
14939 && !inst.operands[j].isquad
14940 && !inst.operands[j].issingle))
14945 if (!(inst.operands[j].isreg
14946 && !inst.operands[j].isvec))
14951 if (!(inst.operands[j].isreg
14952 && inst.operands[j].isvec
14953 && inst.operands[j].isquad
14954 && !inst.operands[j].issingle))
14959 if (!(!inst.operands[j].isreg
14960 && !inst.operands[j].isscalar))
14965 if (!(!inst.operands[j].isreg
14966 && inst.operands[j].isscalar))
14977 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
15215 if (els > 1 && !inst.operands[1].present)
15216 inst.operands[1] = inst.operands[0];
15234 if (inst.vectype.elems > 0)
15236 if (inst.operands[i].vectype.type != NT_invtype)
15242 /* Duplicate inst.vectype elements here as necessary.
15246 if (inst.vectype.elems == 1 && els > 1)
15249 inst.vectype.elems = els;
15250 inst.vectype.el[key_el] = inst.vectype.el[0];
15253 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
15256 else if (inst.vectype.elems == 0 && els > 0)
15263 if (inst.operands[j].vectype.type != NT_invtype)
15264 inst.vectype.el[j] = inst.operands[j].vectype;
15266 if (inst.operands[key_el].vectype.type != NT_invtype)
15269 if (inst.operands[j].vectype.type == NT_invtype)
15270 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
15279 else if (inst.vectype.elems != els)
15292 enum neon_el_type g_type = inst.vectype.el[i].type;
15293 unsigned g_size = inst.vectype.el[i].size;
15324 inst.error = _(BAD_FP16);
15360 inst.error = _(BAD_FP16);
15397 return inst.vectype.el[key_el];
15407 inst.is_neon = 1;
15410 inst.instruction |= 0xe0000000;
15412 inst.instruction |= inst.cond << 28;
15437 inst.is_neon = 1;
15441 inst.instruction = opcode->tvalue;
15446 inst.instruction = (inst.cond << 28) | opcode->avalue;
15454 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
15508 inst.error = NULL;
15515 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
15540 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
15580 int is_neg = (inst.instruction & 0x80) != 0;
15609 int is_ldm = (inst.instruction & (1 << 20)) != 0;
15672 NEON_ENCODE (SINGLE, inst);
15681 NEON_ENCODE (DOUBLE, inst);
15711 switch (inst.operands[0].imm)
15737 if (inst.operands[0].imm > 1)
15742 return inst.operands[0].imm;
15744 if (inst.operands[0].imm == 0x2)
15746 else if (inst.operands[0].imm == 0x8)
15754 switch (inst.operands[0].imm)
15784 if (inst.cond > COND_ALWAYS)
15785 inst.pred_insn_type = INSIDE_VPT_INSN;
15787 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15790 32 and 64. For instructions with no type, inst.vectype.el[j].type is set
15791 to NT_untyped and size is updated in inst.vectype.el[j].size. */
15792 if ((inst.operands[0].present) && (inst.vectype.el[0].type == NT_untyped))
15793 dt = inst.vectype.el[0].size;
15797 inst.is_neon = 1;
15812 inst.instruction |= size << 20;
15813 inst.instruction |= inst.operands[0].reg << 16;
15820 if (inst.operands[0].present)
15829 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
15839 inst.instruction |= (et.size == 16) << 28;
15840 inst.instruction |= 0x3 << 20;
15846 inst.instruction |= 1 << 28;
15847 inst.instruction |= neon_logbits (et.size) << 20;
15850 if (inst.operands[2].isquad)
15852 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15853 inst.instruction |= LOW4 (inst.operands[2].reg);
15854 inst.instruction |= (fcond & 0x2) >> 1;
15858 if (inst.operands[2].reg == REG_SP)
15860 inst.instruction |= 1 << 6;
15861 inst.instruction |= (fcond & 0x2) << 4;
15862 inst.instruction |= inst.operands[2].reg;
15864 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15865 inst.instruction |= (fcond & 0x4) << 10;
15866 inst.instruction |= (fcond & 0x1) << 7;
15871 now_pred.mask = ((inst.instruction & 0x00400000) >> 19)
15872 | ((inst.instruction & 0xe000) >> 13);
15875 inst.is_neon = 1;
15882 if (!inst.operands[1].isreg || !inst.operands[1].isquad)
15884 if (!inst.operands[2].present)
15886 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
15889 if ((inst.instruction & 0xffffffff) == N_MNEM_vcmpe
15890 && inst.operands[1].isquad)
15892 inst.instruction = N_MNEM_vcmp;
15893 inst.cond = 0x10;
15896 if (inst.cond > COND_ALWAYS)
15897 inst.pred_insn_type = INSIDE_VPT_INSN;
15899 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15906 constraint (rs == NS_IQR && inst.operands[2].reg == REG_PC
15907 && !inst.operands[2].iszr, BAD_PC);
15911 inst.instruction = 0xee010f00;
15912 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15913 inst.instruction |= (fcond & 0x4) << 10;
15914 inst.instruction |= (fcond & 0x1) << 7;
15919 inst.instruction |= (et.size == 16) << 28;
15920 inst.instruction |= 0x3 << 20;
15924 inst.instruction |= 1 << 28;
15925 inst.instruction |= neon_logbits (et.size) << 20;
15927 if (inst.operands[2].isquad)
15929 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15930 inst.instruction |= (fcond & 0x2) >> 1;
15931 inst.instruction |= LOW4 (inst.operands[2].reg);
15935 if (inst.operands[2].reg == REG_SP)
15937 inst.instruction |= 1 << 6;
15938 inst.instruction |= (fcond & 0x2) << 4;
15939 inst.instruction |= inst.operands[2].reg;
15942 inst.is_neon = 1;
15949 if (inst.cond > COND_ALWAYS)
15950 inst.pred_insn_type = INSIDE_VPT_INSN;
15952 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15958 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15959 inst.instruction |= neon_logbits (et.size) << 18;
15960 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15961 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15962 inst.instruction |= LOW4 (inst.operands[1].reg);
15963 inst.is_neon = 1;
15973 if (inst.cond > COND_ALWAYS)
15974 inst.pred_insn_type = INSIDE_VPT_INSN;
15976 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15978 if (inst.operands[2].reg == REG_SP)
15980 else if (inst.operands[2].reg == REG_PC)
15983 inst.instruction |= (et.size == 16) << 28;
15984 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15985 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15986 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15987 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15988 inst.instruction |= inst.operands[2].reg;
15989 inst.is_neon = 1;
15995 if (inst.cond > COND_ALWAYS)
15996 inst.pred_insn_type = INSIDE_VPT_INSN;
15998 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16000 unsigned imm = inst.relocs[0].exp.X_add_number;
16007 if (inst.instruction == M_MNEM_vddup || inst.instruction == M_MNEM_vidup)
16015 constraint ((inst.operands[2].reg % 2) != 1, BAD_EVEN);
16016 if (inst.operands[2].reg == REG_SP)
16018 else if (inst.operands[2].reg == REG_PC)
16023 Rm = inst.operands[2].reg >> 1;
16025 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16026 inst.instruction |= neon_logbits (et.size) << 20;
16027 inst.instruction |= inst.operands[1].reg << 16;
16028 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16029 inst.instruction |= (imm > 2) << 7;
16030 inst.instruction |= Rm << 1;
16031 inst.instruction |= (imm == 2 || imm == 8);
16032 inst.is_neon = 1;
16042 if (inst.operands[2].reg == REG_PC)
16044 else if (inst.operands[2].reg == REG_SP)
16047 if (inst.cond > COND_ALWAYS)
16048 inst.pred_insn_type = INSIDE_VPT_INSN;
16050 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16052 inst.instruction |= (et.type == NT_untyped) << 28;
16053 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16054 inst.instruction |= neon_logbits (et.size) << 20;
16055 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16056 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16057 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16058 inst.instruction |= inst.operands[2].reg;
16059 inst.is_neon = 1;
16068 if (inst.cond > COND_ALWAYS)
16069 inst.pred_insn_type = INSIDE_VPT_INSN;
16071 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16073 int imm = inst.operands[2].imm;
16079 inst.instruction |= neon_logbits (et.size) << 18;
16080 inst.instruction |= 0x110001;
16084 inst.instruction |= (et.size + imm) << 16;
16085 inst.instruction |= 0x800140;
16088 inst.instruction |= (et.type == NT_unsigned) << 28;
16089 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16090 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16091 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16092 inst.instruction |= LOW4 (inst.operands[1].reg);
16093 inst.is_neon = 1;
16099 if (inst.cond > COND_ALWAYS)
16100 inst.pred_insn_type = INSIDE_VPT_INSN;
16102 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16104 if (inst.operands[1].reg == REG_PC)
16106 else if (inst.operands[1].reg == REG_SP)
16109 int imm = inst.operands[2].imm;
16112 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16113 inst.instruction |= (imm & 0x1f) << 16;
16114 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16115 inst.instruction |= inst.operands[1].reg;
16116 inst.is_neon = 1;
16123 switch (inst.instruction)
16149 if (inst.cond > COND_ALWAYS)
16150 inst.pred_insn_type = INSIDE_VPT_INSN;
16152 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16154 unsigned Qd = inst.operands[0].reg;
16155 unsigned Qm = inst.operands[1].reg;
16156 unsigned imm = inst.operands[2].imm;
16162 inst.instruction |= (et.type == NT_unsigned) << 28;
16163 inst.instruction |= HI1 (Qd) << 22;
16164 inst.instruction |= (et.size - imm) << 16;
16165 inst.instruction |= LOW4 (Qd) << 12;
16166 inst.instruction |= HI1 (Qm) << 5;
16167 inst.instruction |= LOW4 (Qm);
16168 inst.is_neon = 1;
16175 if (inst.instruction == M_MNEM_vqmovnt
16176 || inst.instruction == M_MNEM_vqmovnb)
16182 if (inst.cond > COND_ALWAYS)
16183 inst.pred_insn_type = INSIDE_VPT_INSN;
16185 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16187 inst.instruction |= (et.type == NT_unsigned) << 28;
16188 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16189 inst.instruction |= (et.size == 32) << 18;
16190 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16191 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16192 inst.instruction |= LOW4 (inst.operands[1].reg);
16193 inst.is_neon = 1;
16201 if (inst.cond > COND_ALWAYS)
16202 inst.pred_insn_type = INSIDE_VPT_INSN;
16204 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16206 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16207 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16208 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16209 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16210 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16211 inst.instruction |= LOW4 (inst.operands[2].reg);
16212 inst.is_neon = 1;
16218 if (inst.cond > COND_ALWAYS)
16219 inst.pred_insn_type = INSIDE_VPT_INSN;
16221 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16231 if (inst.cond > COND_ALWAYS)
16232 inst.pred_insn_type = INSIDE_VPT_INSN;
16234 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16236 inst.instruction |= (et.size == 16) << 28;
16237 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16238 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16239 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16240 inst.instruction |= LOW4 (inst.operands[1].reg);
16241 inst.is_neon = 1;
16251 if (inst.cond > COND_ALWAYS)
16252 inst.pred_insn_type = INSIDE_VPT_INSN;
16254 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16256 unsigned rot = inst.relocs[0].exp.X_add_number;
16260 if (et.size == 32 && (inst.operands[0].reg == inst.operands[1].reg
16261 || inst.operands[0].reg == inst.operands[2].reg))
16264 inst.instruction |= (et.size == 32) << 28;
16265 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16266 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16267 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16268 inst.instruction |= (rot > 90) << 12;
16269 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16270 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16271 inst.instruction |= LOW4 (inst.operands[2].reg);
16272 inst.instruction |= (rot == 90 || rot == 270);
16273 inst.is_neon = 1;
16281 unsigned long insn = inst.instruction;
16283 inst.instruction = THUMB_OP32 (inst.instruction);
16294 inst.instruction |= neon_logbits (et.size) << 20;
16295 inst.is_neon = 1;
16301 constraint (!inst.operands[0].present,
16306 if (!inst.operands[0].present)
16307 inst.instruction |= 1 << 21;
16318 constraint (inst.operands[1].isreg != 1, BAD_ARGS);
16321 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
16322 else if (inst.operands[1].reg == REG_PC)
16324 if (inst.operands[1].reg == REG_SP)
16327 inst.instruction |= (inst.operands[1].reg << 16);
16340 if (!inst.operands[0].isreg)
16347 constraint (inst.operands[2].present, BAD_SYNTAX);
16352 if (inst.operands[1].isreg)
16359 NEON_ENCODE (SINGLE, inst);
16364 NEON_ENCODE (DOUBLE, inst);
16373 switch (inst.instruction & 0x0fffffff)
16376 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
16379 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
16387 NEON_ENCODE (SINGLE, inst);
16392 NEON_ENCODE (DOUBLE, inst);
16406 inst.operands[1] = inst.operands[0];
16407 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
16408 inst.operands[0].reg = REG_SP;
16409 inst.operands[0].isreg = 1;
16410 inst.operands[0].writeback = 1;
16411 inst.operands[0].present = 1;
16442 if (inst.operands[2].reg == REG_SP)
16444 else if (inst.operands[2].reg == REG_PC)
16450 if (((unsigned)inst.instruction) == 0xd00)
16451 inst.instruction = 0xee300f40;
16453 else if (((unsigned)inst.instruction) == 0x200d00)
16454 inst.instruction = 0xee301f40;
16456 else if (((unsigned)inst.instruction) == 0x1000d10)
16457 inst.instruction = 0xee310e60;
16460 inst.instruction |= (size == 16) << 28;
16465 if (((unsigned)inst.instruction) == 0x800)
16466 inst.instruction = 0xee010f40;
16468 else if (((unsigned)inst.instruction) == 0x1000800)
16469 inst.instruction = 0xee011f40;
16471 else if (((unsigned)inst.instruction) == 0)
16472 inst.instruction = 0xee000f40;
16474 else if (((unsigned)inst.instruction) == 0x200)
16475 inst.instruction = 0xee001f40;
16477 else if (((unsigned)inst.instruction) == 0x900)
16478 inst.instruction = 0xee010e40;
16480 else if (((unsigned)inst.instruction) == 0x910)
16481 inst.instruction = 0xee011e60;
16483 else if (((unsigned)inst.instruction) == 0x10)
16484 inst.instruction = 0xee000f60;
16486 else if (((unsigned)inst.instruction) == 0x210)
16487 inst.instruction = 0xee001f60;
16489 else if (((unsigned)inst.instruction) == 0x3000b10)
16490 inst.instruction = 0xee000e40;
16492 else if (((unsigned)inst.instruction) == 0x0000b00)
16493 inst.instruction = 0xee010e60;
16495 else if (((unsigned)inst.instruction) == 0x1000b00)
16496 inst.instruction = 0xfe010e60;
16499 inst.instruction |= U << 28;
16502 inst.instruction |= neon_logbits (size) << 20;
16504 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16505 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16506 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16507 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16508 inst.instruction |= inst.operands[2].reg;
16509 inst.is_neon = 1;
16515 inst.instruction |= bit28 << 28;
16516 inst.instruction |= neon_logbits (size) << 20;
16517 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16518 inst.instruction |= inst.operands[0].reg << 12;
16519 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16520 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16521 inst.instruction |= LOW4 (inst.operands[2].reg);
16522 inst.is_neon = 1;
16529 inst.instruction |= (ubit != 0) << 28;
16530 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16531 inst.instruction |= neon_logbits (size) << 20;
16532 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16533 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16534 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16535 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16536 inst.instruction |= LOW4 (inst.operands[2].reg);
16538 inst.is_neon = 1;
16544 inst.instruction |= bit28 << 28;
16545 inst.instruction |= neon_logbits (size) << 18;
16546 inst.instruction |= inst.operands[0].reg << 12;
16547 inst.instruction |= LOW4 (inst.operands[1].reg);
16548 inst.is_neon = 1;
16554 constraint (inst.operands[3].reg > 14, MVE_BAD_QREG);
16556 inst.instruction |= U << 28;
16557 inst.instruction |= (inst.operands[1].reg >> 1) << 20;
16558 inst.instruction |= LOW4 (inst.operands[2].reg) << 16;
16559 inst.instruction |= (size == 32) << 16;
16560 inst.instruction |= inst.operands[0].reg << 12;
16561 inst.instruction |= HI1 (inst.operands[2].reg) << 7;
16562 inst.instruction |= inst.operands[3].reg;
16563 inst.is_neon = 1;
16570 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16571 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16572 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16573 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16574 inst.instruction |= LOW4 (inst.operands[2].reg);
16575 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16576 inst.instruction |= (isquad != 0) << 6;
16577 inst.is_neon = 1;
16592 inst.instruction |= (ubit != 0) << 24;
16594 inst.instruction |= neon_logbits (size) << 20;
16596 neon_dp_fixup (&inst);
16609 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16610 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16611 inst.instruction |= LOW4 (inst.operands[1].reg);
16612 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16613 inst.instruction |= (qbit != 0) << 6;
16614 inst.instruction |= (ubit != 0) << 24;
16617 inst.instruction |= neon_logbits (size) << 18;
16619 neon_dp_fixup (&inst);
16644 changed to inst.uncond_value. This is necessary because instructions shared
16654 if (inst.cond != COND_ALWAYS)
16659 if (inst.uncond_value != -1u)
16660 inst.instruction |= inst.uncond_value << 28;
16684 if (inst.cond > COND_ALWAYS)
16688 inst.error = BAD_FPU;
16691 inst.pred_insn_type = INSIDE_VPT_INSN;
16693 else if (inst.cond < COND_ALWAYS)
16696 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16707 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16764 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16765 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16766 inst.instruction |= LOW4 (inst.operands[1].reg);
16767 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16768 inst.instruction |= (isquad != 0) << 6;
16769 inst.instruction |= immbits << 16;
16770 inst.instruction |= (size >> 3) << 7;
16771 inst.instruction |= (size & 0x7) << 19;
16773 inst.instruction |= (uval != 0) << 24;
16775 neon_dp_fixup (&inst);
16784 if (!inst.operands[2].isreg)
16798 int imm = inst.operands[2].imm;
16802 NEON_ENCODE (IMMED, inst);
16823 constraint (inst.operands[0].reg != inst.operands[1].reg,
16825 if (inst.operands[2].reg == REG_SP)
16827 else if (inst.operands[2].reg == REG_PC)
16830 inst.instruction = 0xee311e60;
16831 inst.instruction |= (et.type == NT_unsigned) << 28;
16832 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16833 inst.instruction |= neon_logbits (et.size) << 18;
16834 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16835 inst.instruction |= inst.operands[2].reg;
16836 inst.is_neon = 1;
16849 tmp = inst.operands[2].reg;
16850 inst.operands[2].reg = inst.operands[1].reg;
16851 inst.operands[1].reg = tmp;
16852 NEON_ENCODE (INTEGER, inst);
16864 if (!inst.operands[2].isreg)
16878 int imm = inst.operands[2].imm;
16882 NEON_ENCODE (IMMED, inst);
16903 constraint (inst.operands[0].reg != inst.operands[1].reg,
16905 if (inst.operands[2].reg == REG_SP)
16907 else if (inst.operands[2].reg == REG_PC)
16910 inst.instruction = 0xee311ee0;
16911 inst.instruction |= (et.type == NT_unsigned) << 28;
16912 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16913 inst.instruction |= neon_logbits (et.size) << 18;
16914 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16915 inst.instruction |= inst.operands[2].reg;
16916 inst.is_neon = 1;
16923 tmp = inst.operands[2].reg;
16924 inst.operands[2].reg = inst.operands[1].reg;
16925 inst.operands[1].reg = tmp;
16926 NEON_ENCODE (INTEGER, inst);
16955 if (inst.operands[2].reg == REG_PC)
16957 else if (inst.operands[2].reg == REG_SP)
16960 constraint (inst.operands[0].reg != inst.operands[1].reg,
16963 if (inst.instruction == 0x0000510)
16965 inst.instruction = 0xee331ee0;
16968 inst.instruction = 0xee331e60;
16970 inst.instruction |= (et.type == NT_unsigned) << 28;
16971 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16972 inst.instruction |= neon_logbits (et.size) << 18;
16973 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16974 inst.instruction |= inst.operands[2].reg;
16975 inst.is_neon = 1;
16979 tmp = inst.operands[2].reg;
16980 inst.operands[2].reg = inst.operands[1].reg;
16981 inst.operands[1].reg = tmp;
17045 if (inst.operands[2].present && inst.operands[2].isreg)
17058 NEON_ENCODE (INTEGER, inst);
17063 const int three_ops_form = (inst.operands[2].present
17064 && !inst.operands[2].isreg);
17088 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
17094 constraint (inst.operands[0].reg != inst.operands[1].reg,
17097 NEON_ENCODE (IMMED, inst);
17099 immbits = inst.operands[immoperand].imm;
17104 if (immbits != (inst.operands[immoperand].regisimm ?
17105 inst.operands[immoperand].reg : 0))
17141 inst.instruction |= neon_quad (rs) << 6;
17142 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17143 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17144 inst.instruction |= cmode << 8;
17147 neon_dp_fixup (&inst);
17168 NEON_ENCODE (FLOAT, inst);
17176 NEON_ENCODE (INTEGER, inst);
17206 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
17207 constraint (!inst.operands[1].preind, BAD_ADDR_MODE);
17208 constraint (load && inst.operands[0].reg == inst.operands[1].reg,
17212 int imm = inst.relocs[0].exp.X_add_number;
17225 inst.instruction |= 0x11 << 24;
17226 inst.instruction |= add << 23;
17227 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17228 inst.instruction |= inst.operands[1].writeback << 21;
17229 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17230 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17231 inst.instruction |= 1 << 12;
17232 inst.instruction |= (size == 64) << 8;
17233 inst.instruction &= 0xffffff00;
17234 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
17235 inst.instruction |= imm >> neon_logbits (size);
17241 unsigned os = inst.operands[1].imm >> 5;
17242 unsigned type = inst.vectype.el[0].type;
17248 if (inst.operands[1].reg == REG_PC)
17266 constraint (inst.operands[1].writeback || !inst.operands[1].preind,
17270 constraint (inst.operands[0].reg == (inst.operands[1].imm & 0x1f),
17276 inst.instruction |= ((size == elsize) || (type == NT_unsigned)) << 28;
17283 inst.instruction |= 1 << 23;
17284 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17285 inst.instruction |= inst.operands[1].reg << 16;
17286 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17287 inst.instruction |= neon_logbits (elsize) << 7;
17288 inst.instruction |= HI1 (inst.operands[1].imm) << 5;
17289 inst.instruction |= LOW4 (inst.operands[1].imm);
17290 inst.instruction |= !!os;
17296 enum neon_el_type type = inst.vectype.el[0].type;
17320 int imm = inst.relocs[0].exp.X_add_number;
17348 constraint (inst.operands[1].reg > 7, BAD_HIREG);
17349 constraint (inst.operands[0].reg > 14,
17351 inst.instruction |= (load && type == NT_unsigned) << 28;
17352 inst.instruction |= (size == 16) << 19;
17353 inst.instruction |= neon_logbits (elsize) << 7;
17357 if (inst.operands[1].reg == REG_PC)
17359 else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
17361 inst.instruction |= 1 << 12;
17362 inst.instruction |= neon_logbits (size) << 7;
17364 inst.instruction |= inst.operands[1].preind << 24;
17365 inst.instruction |= add << 23;
17366 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17367 inst.instruction |= inst.operands[1].writeback << 21;
17368 inst.instruction |= inst.operands[1].reg << 16;
17369 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17370 inst.instruction &= 0xffffff80;
17371 inst.instruction |= imm >> neon_logbits (size);
17381 if (inst.cond > COND_ALWAYS)
17382 inst.pred_insn_type = INSIDE_VPT_INSN;
17384 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17386 switch (inst.instruction)
17416 unsigned elsize = inst.vectype.el[0].size;
17418 if (inst.operands[1].isquad)
17425 if (inst.operands[1].immisreg == 2)
17430 else if (!inst.operands[1].immisreg)
17439 inst.is_neon = 1;
17448 constraint (!inst.operands[1].preind || inst.relocs[0].exp.X_add_symbol != 0
17449 || inst.relocs[0].exp.X_add_number != 0
17450 || inst.operands[1].immisreg != 0,
17452 constraint (inst.vectype.el[0].size > 32, BAD_EL_TYPE);
17453 if (inst.operands[1].reg == REG_PC)
17455 else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
17463 if (inst.cond > COND_ALWAYS)
17467 else if (inst.cond < COND_ALWAYS)
17468 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17470 inst.pred_insn_type = MVE_UNPREDICABLE_INSN;
17472 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17473 inst.instruction |= inst.operands[1].writeback << 21;
17474 inst.instruction |= inst.operands[1].reg << 16;
17475 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17476 inst.instruction |= neon_logbits (inst.vectype.el[0].size) << 7;
17477 inst.is_neon = 1;
17490 if (inst.cond > COND_ALWAYS)
17491 inst.pred_insn_type = INSIDE_VPT_INSN;
17493 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17495 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
17497 inst.instruction |= (et.type == NT_unsigned) << 28;
17498 inst.instruction |= inst.operands[1].reg << 19;
17499 inst.instruction |= inst.operands[0].reg << 12;
17500 inst.instruction |= inst.operands[2].reg;
17501 inst.is_neon = 1;
17511 constraint ((inst.instruction == ((unsigned) N_MNEM_vmax)
17512 || inst.instruction == ((unsigned) N_MNEM_vmin))
17570 if (inst.operands[1].present)
17572 void *scratch = xmalloc (sizeof (inst.operands[0]));
17575 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
17576 inst.operands[1] = inst.operands[2];
17577 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
17582 inst.operands[1] = inst.operands[2];
17583 inst.operands[2] = inst.operands[0];
17590 if (inst.operands[2].isreg)
17602 NEON_ENCODE (IMMED, inst);
17603 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17604 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17605 inst.instruction |= LOW4 (inst.operands[1].reg);
17606 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
17607 inst.instruction |= neon_quad (rs) << 6;
17608 inst.instruction |= (et.type == NT_float) << 10;
17609 inst.instruction |= neon_logbits (et.size) << 18;
17611 neon_dp_fixup (&inst);
17683 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
17684 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17685 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17686 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17687 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
17688 inst.instruction |= LOW4 (scalar);
17689 inst.instruction |= HI1 (scalar) << 5;
17690 inst.instruction |= (et.type == NT_float) << 8;
17691 inst.instruction |= neon_logbits (et.size) << 20;
17692 inst.instruction |= (ubit != 0) << 24;
17694 neon_dp_fixup (&inst);
17706 if (inst.operands[2].isscalar)
17712 NEON_ENCODE (SCALAR, inst);
17715 else if (!inst.operands[2].isvec)
17741 if (inst.instruction != B_MNEM_vfmab)
17744 inst.instruction = B_MNEM_vfmat;
17747 if (inst.operands[2].isscalar)
17752 inst.instruction |= (1 << 25);
17753 int idx = inst.operands[2].reg & 0xf;
17755 inst.operands[2].reg >>= 4;
17756 constraint (!(inst.operands[2].reg < 8),
17759 inst.instruction |= ((idx & 1) << 3);
17760 inst.instruction |= ((idx & 2) << 4);
17790 if (inst.operands[2].reg == REG_SP)
17792 else if (inst.operands[2].reg == REG_PC)
17795 inst.instruction = 0xee310e40;
17796 inst.instruction |= (et.size == 16) << 28;
17797 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17798 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17799 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17800 inst.instruction |= HI1 (inst.operands[1].reg) << 6;
17801 inst.instruction |= inst.operands[2].reg;
17802 inst.is_neon = 1;
17808 constraint (!inst.operands[2].isvec, BAD_FPU);
17818 inst.cond == COND_ALWAYS)
17821 inst.instruction = N_MNEM_vfma;
17822 inst.pred_insn_type = INSIDE_VPT_INSN;
17823 inst.cond = 0xf;
17854 if (inst.operands[2].isscalar)
17874 constraint (!inst.operands[2].isvec, BAD_FPU);
17887 if (inst.operands[2].isscalar)
17893 NEON_ENCODE (SCALAR, inst);
17913 NEON_ENCODE (INTEGER, inst);
17932 if (inst.cond > COND_ALWAYS)
17933 inst.pred_insn_type = INSIDE_VPT_INSN;
17935 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17937 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
17949 if (inst.cond > COND_ALWAYS)
17950 inst.pred_insn_type = INSIDE_VPT_INSN;
17952 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17954 unsigned rot = inst.relocs[0].exp.X_add_number;
17957 if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
17962 inst.instruction |= (rot == 270) << 12;
17963 inst.is_neon = 1;
17974 && (inst.operands[0].reg == inst.operands[1].reg
17975 || (rs == NS_QQQ && inst.operands[0].reg == inst.operands[2].reg)))
17978 if (inst.cond > COND_ALWAYS)
17979 inst.pred_insn_type = INSIDE_VPT_INSN;
17981 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17986 inst.instruction |= 1;
17991 inst.instruction |= 0x3 << 5;
18005 if (inst.cond > COND_ALWAYS)
18006 inst.pred_insn_type = INSIDE_VPT_INSN;
18008 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18020 if (inst.cond > COND_ALWAYS)
18021 inst.pred_insn_type = INSIDE_VPT_INSN;
18023 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18033 if (inst.cond > COND_ALWAYS)
18034 inst.pred_insn_type = INSIDE_VPT_INSN;
18036 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18048 if (inst.cond > COND_ALWAYS)
18049 inst.pred_insn_type = INSIDE_VPT_INSN;
18051 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18063 if (inst.cond > COND_ALWAYS)
18064 inst.pred_insn_type = INSIDE_VPT_INSN;
18066 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18078 if (inst.cond > COND_ALWAYS)
18079 inst.pred_insn_type = INSIDE_VPT_INSN;
18081 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18093 if (inst.cond == COND_ALWAYS
18094 && ((unsigned)inst.instruction) == M_MNEM_vmullt)
18112 && (inst.operands[0].reg == inst.operands[1].reg
18113 || inst.operands[0].reg == inst.operands[2].reg))
18116 if (inst.cond > COND_ALWAYS)
18117 inst.pred_insn_type = INSIDE_VPT_INSN;
18119 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18129 inst.instruction = N_MNEM_vmul;
18130 inst.cond = 0xb;
18132 inst.pred_insn_type = INSIDE_IT_INSN;
18151 if (inst.cond > COND_ALWAYS)
18152 inst.pred_insn_type = INSIDE_VPT_INSN;
18154 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18167 && (inst.instruction == M_MNEM_vmladavx
18168 || inst.instruction == M_MNEM_vmladavax
18169 || inst.instruction == M_MNEM_vmlsdav
18170 || inst.instruction == M_MNEM_vmlsdava
18171 || inst.instruction == M_MNEM_vmlsdavx
18172 || inst.instruction == M_MNEM_vmlsdavax))
18175 constraint (inst.operands[2].reg > 14,
18178 if (inst.cond > COND_ALWAYS)
18179 inst.pred_insn_type = INSIDE_VPT_INSN;
18181 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18183 if (inst.instruction == M_MNEM_vmlsdav
18184 || inst.instruction == M_MNEM_vmlsdava
18185 || inst.instruction == M_MNEM_vmlsdavx
18186 || inst.instruction == M_MNEM_vmlsdavax)
18187 inst.instruction |= (et.size == 8) << 28;
18189 inst.instruction |= (et.size == 8) << 8;
18192 inst.instruction |= (et.size == 32) << 16;
18204 && (inst.instruction == M_MNEM_vmlsldav
18205 || inst.instruction == M_MNEM_vmlsldava
18206 || inst.instruction == M_MNEM_vmlsldavx
18207 || inst.instruction == M_MNEM_vmlsldavax))
18210 if (inst.cond > COND_ALWAYS)
18211 inst.pred_insn_type = INSIDE_VPT_INSN;
18213 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18222 if (inst.instruction == M_MNEM_vrmlsldavh
18223 || inst.instruction == M_MNEM_vrmlsldavha
18224 || inst.instruction == M_MNEM_vrmlsldavhx
18225 || inst.instruction == M_MNEM_vrmlsldavhax)
18228 if (inst.operands[1].reg == REG_SP)
18233 if (inst.instruction == M_MNEM_vrmlaldavhx
18234 || inst.instruction == M_MNEM_vrmlaldavhax)
18243 constraint (inst.operands[1].reg == REG_SP, BAD_SP);
18250 constraint ((inst.operands[1].reg % 2) != 1, BAD_EVEN);
18251 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
18253 if (inst.cond > COND_ALWAYS)
18254 inst.pred_insn_type = INSIDE_VPT_INSN;
18256 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18269 if (inst.cond > COND_ALWAYS)
18270 inst.pred_insn_type = INSIDE_VPT_INSN;
18272 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18274 if (inst.operands[0].reg == REG_SP)
18276 else if (inst.operands[0].reg == REG_PC)
18288 if (inst.instruction == M_MNEM_vmaxv || inst.instruction == M_MNEM_vminv)
18293 if (inst.cond > COND_ALWAYS)
18294 inst.pred_insn_type = INSIDE_VPT_INSN;
18296 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18298 if (inst.operands[0].reg == REG_SP)
18300 else if (inst.operands[0].reg == REG_PC)
18316 inst.error
18323 if (inst.operands[2].isscalar)
18328 NEON_ENCODE (SCALAR, inst);
18336 NEON_ENCODE (INTEGER, inst);
18347 NEON_ENCODE (INTEGER, inst);
18394 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18395 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18396 inst.instruction |= LOW4 (inst.operands[1].reg);
18397 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18398 inst.instruction |= neon_quad (rs) << 6;
18399 inst.instruction |= (et.type == NT_float) << 10;
18400 inst.instruction |= neon_logbits (et.size) << 18;
18402 neon_dp_fixup (&inst);
18425 int imm = inst.operands[2].imm;
18450 int imm = inst.operands[2].imm;
18476 int imm = inst.operands[2].imm;
18482 inst.instruction |= (et.type == NT_unsigned) << 8;
18494 NEON_ENCODE (INTEGER, inst);
18496 inst.instruction |= 0xc0;
18498 inst.instruction |= 0x80;
18508 NEON_ENCODE (INTEGER, inst);
18519 int imm = inst.operands[2].imm;
18528 inst.operands[2].present = 0;
18529 inst.instruction = N_MNEM_vqmovn;
18546 int imm = inst.operands[2].imm;
18555 inst.operands[2].present = 0;
18556 inst.instruction = N_MNEM_vqmovun;
18574 NEON_ENCODE (INTEGER, inst);
18583 int imm = inst.operands[2].imm;
18592 inst.operands[2].present = 0;
18593 inst.instruction = N_MNEM_vmovn;
18609 unsigned imm = inst.operands[2].imm;
18614 NEON_ENCODE (INTEGER, inst);
18615 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18616 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18617 inst.instruction |= LOW4 (inst.operands[1].reg);
18618 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18619 inst.instruction |= neon_logbits (et.size) << 18;
18621 neon_dp_fixup (&inst);
18628 NEON_ENCODE (IMMED, inst);
18693 inst.error = NULL; \
18745 constraint (inst.operands[0].reg != inst.operands[1].reg,
18747 inst.operands[1] = inst.operands[2];
18748 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
18855 NEON_ENCODE (FPV8, inst);
18856 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
18857 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
18858 inst.instruction |= sz << 8;
18864 inst.instruction |= op << 7;
18865 inst.instruction |= rm << 16;
18866 inst.instruction |= 0xf0000000;
18867 inst.is_neon = true;
18950 constraint (inst.operands[2].present && inst.operands[2].imm == 0,
18958 constraint (inst.operands[2].imm > 16,
18965 constraint (inst.operands[2].imm > 32,
18969 inst.error = BAD_FPU;
18976 if (inst.operands[2].present && inst.operands[2].imm == 0)
18978 NEON_ENCODE (IMMED, inst);
18980 inst.instruction |= enctab[flavour];
18981 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18982 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18983 inst.instruction |= LOW4 (inst.operands[1].reg);
18984 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18985 inst.instruction |= neon_quad (rs) << 6;
18986 inst.instruction |= 1 << 21;
18989 inst.instruction |= 1 << 21;
18990 immbits = 32 - inst.operands[2].imm;
18991 inst.instruction |= immbits << 16;
18995 inst.instruction |= 3 << 20;
18996 immbits = 16 - inst.operands[2].imm;
18997 inst.instruction |= immbits << 16;
18998 inst.instruction &= ~(1 << 9);
19001 neon_dp_fixup (&inst);
19036 NEON_ENCODE (FLOAT, inst);
19041 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19042 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19043 inst.instruction |= LOW4 (inst.operands[1].reg);
19044 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19045 inst.instruction |= neon_quad (rs) << 6;
19046 inst.instruction |= (flavour == neon_cvt_flavour_u16_f16
19048 inst.instruction |= mode << 8;
19052 inst.instruction = ((inst.instruction & 0xfff3ffff) | (1 << 18));
19055 inst.instruction |= 0xfc000000;
19057 inst.instruction |= 0xf0000000;
19066 NEON_ENCODE (INTEGER, inst);
19075 inst.instruction |= enctab[flavour];
19077 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19078 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19079 inst.instruction |= LOW4 (inst.operands[1].reg);
19080 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19081 inst.instruction |= neon_quad (rs) << 6;
19085 inst.instruction |= 1 << 18;
19087 inst.instruction |= 2 << 18;
19089 neon_dp_fixup (&inst);
19101 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
19108 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
19122 inst.instruction = 0x11b60640;
19126 inst.instruction = 0x3b60600;
19130 inst.instruction = 0x3b60700;
19132 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19133 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19134 inst.instruction |= LOW4 (inst.operands[1].reg);
19135 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19136 neon_dp_fixup (&inst);
19190 encode_arm_vfp_reg (inst.operands[0].reg,
19192 encode_arm_vfp_reg (inst.operands[1].reg,
19194 inst.instruction |= to ? 0x10000 : 0;
19195 inst.instruction |= t ? 0x80 : 0;
19196 inst.instruction |= is_double ? 0x100 : 0;
19226 inst.cond = 0xf;
19227 inst.instruction = N_MNEM_vcvt;
19240 unsigned op0 = inst.operands[0].reg;
19241 unsigned op1 = inst.operands[1].reg;
19242 /* NS_QQ so both registers are quads but inst.operands has their
19249 inst.instruction = 0xee3f0e01;
19250 inst.instruction |= single_to_half << 28;
19251 inst.instruction |= HI1 (op0) << 22;
19252 inst.instruction |= LOW4 (op0) << 13;
19253 inst.instruction |= t << 12;
19254 inst.instruction |= HI1 (op1) << 5;
19255 inst.instruction |= LOW4 (op1) << 1;
19256 inst.is_neon = 1;
19260 inst.error = NULL;
19265 inst.error = NULL;
19275 inst.error = NULL;
19285 inst.error = NULL;
19291 inst.error = NULL;
19292 inst.instruction |= (1 << 8);
19293 inst.instruction &= ~(1 << 9);
19326 op = (inst.instruction & (1 << 5)) != 0;
19328 immlo = inst.operands[1].imm;
19329 if (inst.operands[1].regisimm)
19330 immhi = inst.operands[1].reg;
19335 float_p = inst.operands[1].immisfloat;
19354 inst.instruction &= ~(1 << 5);
19355 inst.instruction |= op << 5;
19357 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19358 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19359 inst.instruction |= neon_quad (rs) << 6;
19360 inst.instruction |= cmode << 8;
19371 if (inst.operands[1].isreg)
19382 NEON_ENCODE (INTEGER, inst);
19383 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19384 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19385 inst.instruction |= LOW4 (inst.operands[1].reg);
19386 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19387 inst.instruction |= neon_quad (rs) << 6;
19391 NEON_ENCODE (IMMED, inst);
19395 neon_dp_fixup (&inst);
19399 constraint (!inst.operands[1].isreg && !inst.operands[0].isquad, BAD_FPU);
19411 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19412 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19413 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19414 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19415 inst.instruction |= LOW4 (inst.operands[2].reg);
19416 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
19417 inst.instruction |= (et.type == NT_unsigned) << 24;
19418 inst.instruction |= neon_logbits (size) << 20;
19420 neon_dp_fixup (&inst);
19432 NEON_ENCODE (INTEGER, inst);
19439 && (inst.cond == 0xf || inst.cond == 0x10))
19444 if (inst.cond == 0xf)
19445 inst.cond = 0xb;
19446 else if (inst.cond == 0x10)
19447 inst.cond = 0xd;
19449 inst.pred_insn_type = INSIDE_IT_INSN;
19451 if (inst.instruction == N_MNEM_vaddl)
19453 inst.instruction = N_MNEM_vadd;
19456 else if (inst.instruction == N_MNEM_vsubl)
19458 inst.instruction = N_MNEM_vsub;
19461 inst.instruction == N_MNEM_vabdl)
19463 inst.instruction = N_MNEM_vabd;
19482 if (inst.operands[2].isscalar)
19486 NEON_ENCODE (SCALAR, inst);
19493 NEON_ENCODE (INTEGER, inst);
19550 if (inst.operands[2].isscalar)
19562 inst.instruction |= (0x1 << 23);
19567 if (inst.cond != COND_ALWAYS)
19584 inst.instruction &= 0x00ffffff;
19585 inst.instruction |= high8;
19590 if (inst.operands[2].isscalar)
19593 = neon_scalar_for_fmac_fp16_long (inst.operands[2].reg, quad_p);
19594 inst.instruction &= 0xffffffd0;
19595 inst.instruction |= rm;
19600 inst.instruction &= 0xfff0ff7f;
19601 inst.instruction |= HI4 (inst.operands[1].reg) << 16;
19602 inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
19608 inst.instruction &= 0xfff0ff50;
19609 inst.instruction |= HI4 (inst.operands[1].reg) << 16;
19610 inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
19611 inst.instruction |= HI4 (inst.operands[2].reg);
19612 inst.instruction |= LOW1 (inst.operands[2].reg) << 5;
19656 if (inst.operands[2].isscalar)
19664 NEON_ENCODE (POLY, inst);
19666 NEON_ENCODE (INTEGER, inst);
19675 inst.error =
19691 unsigned imm = (inst.operands[3].imm * et.size) / 8;
19695 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19696 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19697 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19698 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19699 inst.instruction |= LOW4 (inst.operands[2].reg);
19700 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
19701 inst.instruction |= neon_quad (rs) << 6;
19702 inst.instruction |= imm << 8;
19704 neon_dp_fixup (&inst);
19722 unsigned op = (inst.instruction >> 7) & 3;
19729 && inst.operands[0].reg == inst.operands[1].reg)
19742 if (inst.operands[1].isscalar)
19750 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
19752 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
19757 NEON_ENCODE (SCALAR, inst);
19758 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19759 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19760 inst.instruction |= LOW4 (dm);
19761 inst.instruction |= HI1 (dm) << 5;
19762 inst.instruction |= neon_quad (rs) << 6;
19763 inst.instruction |= x << 17;
19764 inst.instruction |= sizebits << 16;
19766 neon_dp_fixup (&inst);
19784 if (inst.operands[1].reg == REG_SP)
19786 else if (inst.operands[1].reg == REG_PC)
19791 NEON_ENCODE (ARMREG, inst);
19794 case 8: inst.instruction |= 0x400000; break;
19795 case 16: inst.instruction |= 0x000020; break;
19796 case 32: inst.instruction |= 0x000000; break;
19799 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
19800 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
19801 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
19802 inst.instruction |= neon_quad (rs) << 21;
19814 if (inst.cond > COND_ALWAYS)
19815 inst.pred_insn_type = MVE_UNPREDICABLE_INSN;
19826 constraint (inst.operands[Q0].reg != inst.operands[Q1].reg + 2,
19829 constraint (!toQ && inst.operands[Rt].reg == inst.operands[Rt2].reg,
19831 constraint (inst.operands[Rt].reg == REG_SP
19832 || inst.operands[Rt2].reg == REG_SP,
19834 constraint (inst.operands[Rt].reg == REG_PC
19835 || inst.operands[Rt2].reg == REG_PC,
19838 inst.instruction = 0xec000f00;
19839 inst.instruction |= HI1 (inst.operands[Q1].reg / 32) << 23;
19840 inst.instruction |= !!toQ << 20;
19841 inst.instruction |= inst.operands[Rt2].reg << 16;
19842 inst.instruction |= LOW4 (inst.operands[Q1].reg / 32) << 13;
19843 inst.instruction |= (inst.operands[Q1].reg % 4) << 4;
19844 inst.instruction |= inst.operands[Rt].reg;
19853 if (inst.cond > COND_ALWAYS)
19854 inst.pred_insn_type = INSIDE_VPT_INSN;
19856 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
19861 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19862 inst.instruction |= (neon_logbits (et.size) - 1) << 18;
19863 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19864 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19865 inst.instruction |= LOW4 (inst.operands[1].reg);
19866 inst.is_neon = 1;
19931 inst.error = NULL;
19953 inst.instruction = 0x0200110;
19954 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19955 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19956 inst.instruction |= LOW4 (inst.operands[1].reg);
19957 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19958 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19959 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19960 inst.instruction |= neon_quad (rs) << 6;
19962 neon_dp_fixup (&inst);
19968 inst.error = NULL;
19981 inst.instruction = 0x0800010;
19983 neon_dp_fixup (&inst);
19990 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
19991 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
19994 if (inst.vectype.elems == 0
19995 && inst.operands[0].vectype.type == NT_invtype
19996 && inst.operands[1].vectype.type == NT_invtype)
19998 inst.vectype.el[0].type = NT_untyped;
19999 inst.vectype.el[0].size = 32;
20000 inst.vectype.elems = 1;
20021 if (inst.operands[1].reg == REG_SP)
20023 else if (inst.operands[1].reg == REG_PC)
20026 unsigned size = inst.operands[0].isscalar == 1 ? 64 : 128;
20042 inst.instruction = 0xe000b10;
20044 inst.instruction |= LOW4 (dn) << 16;
20045 inst.instruction |= HI1 (dn) << 7;
20046 inst.instruction |= inst.operands[1].reg << 12;
20047 inst.instruction |= (bcdebits & 3) << 5;
20048 inst.instruction |= ((bcdebits >> 2) & 3) << 21;
20049 inst.instruction |= (x >> (3-logsize)) << 16;
20058 inst.instruction = 0xc400b10;
20060 inst.instruction |= LOW4 (inst.operands[0].reg);
20061 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
20062 inst.instruction |= inst.operands[1].reg << 12;
20063 inst.instruction |= inst.operands[2].reg << 16;
20069 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
20070 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
20074 if (inst.vectype.elems == 0
20075 && inst.operands[0].vectype.type == NT_invtype
20076 && inst.operands[1].vectype.type == NT_invtype)
20078 inst.vectype.el[0].type = NT_untyped;
20079 inst.vectype.el[0].size = 32;
20080 inst.vectype.elems = 1;
20103 if (inst.operands[0].reg == REG_SP)
20105 else if (inst.operands[0].reg == REG_PC)
20109 unsigned size = inst.operands[1].isscalar == 1 ? 64 : 128;
20123 inst.instruction = 0xe100b10;
20125 inst.instruction |= LOW4 (dn) << 16;
20126 inst.instruction |= HI1 (dn) << 7;
20127 inst.instruction |= inst.operands[0].reg << 12;
20128 inst.instruction |= (abcdebits & 3) << 5;
20129 inst.instruction |= (abcdebits >> 2) << 21;
20130 inst.instruction |= (x >> (3-logsize)) << 16;
20139 inst.instruction = 0xc500b10;
20141 inst.instruction |= inst.operands[0].reg << 12;
20142 inst.instruction |= inst.operands[1].reg << 16;
20143 inst.instruction |= LOW4 (inst.operands[2].reg);
20144 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
20155 if (!inst.operands[1].immisfloat)
20159 float imm = (float) inst.operands[1].imm;
20166 if (is_quarter_float (inst.operands[1].imm))
20169 inst.operands[1].imm = new_imm;
20170 inst.operands[1].immisfloat = 1;
20174 if (is_quarter_float (inst.operands[1].imm))
20176 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
20218 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
20220 inst.operands[2].imm = 2;
20221 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
20229 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
20231 inst.operands[1] = inst.operands[2];
20232 inst.operands[2] = inst.operands[3];
20233 inst.operands[0].imm = 2;
20234 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
20251 if (!(inst.operands[0].present && inst.operands[0].isquad
20252 && inst.operands[1].present && inst.operands[1].isquad
20253 && !inst.operands[2].present))
20255 inst.instruction = 0;
20256 inst.cond = 0xb;
20266 if (inst.cond != COND_ALWAYS)
20267 inst.pred_insn_type = INSIDE_VPT_INSN;
20272 inst.instruction |= (et.type == NT_unsigned) << 28;
20273 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20274 inst.instruction |= (neon_logbits (et.size) + 1) << 19;
20275 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20276 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
20277 inst.instruction |= LOW4 (inst.operands[1].reg);
20278 inst.is_neon = 1;
20300 int imm = inst.operands[2].imm;
20305 inst.operands[2].present = 0;
20322 if (inst.cond != COND_ALWAYS)
20331 inst.error = BAD_COND;
20338 inst.is_neon = 1;
20339 inst.instruction |= 0xf0000000;
20348 inst.instruction |= sizebits << 19;
20358 NEON_ENCODE (INTEGER, inst);
20371 inst.instruction = N_MNEM_vtrn;
20400 inst.instruction |= (et.type == NT_unsigned) << 7;
20410 inst.instruction |= (et.type == NT_float) << 8;
20472 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
20478 listlenbits = inst.operands[1].imm - 1;
20479 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20480 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20481 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
20482 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
20483 inst.instruction |= LOW4 (inst.operands[2].reg);
20484 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
20485 inst.instruction |= listlenbits << 8;
20487 neon_dp_fixup (&inst);
20497 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
20498 unsigned offsetbits = inst.operands[1].imm * 2;
20500 if (inst.operands[1].issingle)
20506 constraint (is_dbmode && !inst.operands[0].writeback,
20509 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
20513 inst.instruction |= inst.operands[0].reg << 16;
20514 inst.instruction |= inst.operands[0].writeback << 21;
20515 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
20516 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
20518 inst.instruction |= offsetbits;
20528 if (inst.operands[1].issingle)
20530 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 32,
20535 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
20550 if (inst.operands[1].issingle)
20566 if (inst.operands[1].issingle)
20575 int is_ldr = (inst.instruction & (1 << 20)) != 0;
20580 && inst.operands[1].reg == REG_PC
20584 inst.error = _("Use of PC here is UNPREDICTABLE");
20589 if (inst.operands[0].issingle)
20597 if (inst.vectype.el[0].size == 16)
20613 bool is_vldr = ((inst
20616 if (inst.operands[1].reg == REG_PC)
20617 inst.error = _("Use of PC here is UNPREDICTABLE");
20619 if (inst.operands[1].immisreg)
20620 inst.error = _("instruction does not accept register index");
20622 if (!inst.operands[1].isreg)
20623 inst.error = _("instruction does not accept PC-relative addressing");
20625 if (abs (inst.operands[1].imm) >= (1 << 7))
20626 inst.error = _("immediate value out of range");
20628 inst.instruction = 0xec000f80;
20630 inst.instruction |= 1 << sysreg_vldr_bitno;
20632 inst.instruction |= (inst.operands[0].imm & 0x7) << 13;
20633 inst.instruction |= (inst.operands[0].imm & 0x8) << 19;
20639 bool sysreg_op = !inst.operands[0].isreg;
20686 if (inst.operands[1].immisalign)
20687 switch (inst.operands[1].imm >> 8)
20691 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
20692 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
20697 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
20707 inst.instruction |= alignbits << 4;
20708 inst.instruction |= neon_logbits (et.size) << 6;
20715 idx = ((inst.operands[0].imm >> 4) & 7)
20716 | (((inst.instruction >> 8) & 3) << 3);
20721 constraint (((inst.instruction >> 8) & 3) && et.size == 64,
20724 inst.instruction &= ~0xf00;
20725 inst.instruction |= typebits << 8;
20739 if (!inst.operands[1].immisalign)
20775 int align = inst.operands[1].imm >> 8;
20776 int n = (inst.instruction >> 8) & 3;
20782 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
20784 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
20786 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
20806 inst.instruction |= alignbits << 4;
20816 inst.instruction |= 1 << 4;
20820 constraint (inst.operands[1].immisalign,
20839 inst.instruction |= alignbits << 4;
20847 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
20848 inst.instruction |= 1 << (4 + logsize);
20850 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
20851 inst.instruction |= logsize << 10;
20865 switch ((inst.instruction >> 8) & 3)
20868 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
20869 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
20873 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
20876 case 2: inst.instruction |= 1 << 5; break;
20879 inst.instruction |= neon_logbits (et.size) << 6;
20883 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
20888 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
20890 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
20891 inst.instruction |= 1 << 5;
20892 inst.instruction |= neon_logbits (et.size) << 6;
20896 constraint (inst.operands[1].immisalign,
20898 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
20900 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
20901 inst.instruction |= 1 << 5;
20902 inst.instruction |= neon_logbits (et.size) << 6;
20907 int align = inst.operands[1].imm >> 8;
20912 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
20914 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
20915 inst.instruction |= 1 << 5;
20917 inst.instruction |= 0x3 << 6;
20919 inst.instruction |= neon_logbits (et.size) << 6;
20926 inst.instruction |= do_alignment << 4;
20935 if (inst.operands[1].isreg)
20936 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
20938 switch (NEON_LANE (inst.operands[0].imm))
20941 NEON_ENCODE (INTERLV, inst);
20946 NEON_ENCODE (DUP, inst);
20947 if (inst.instruction == N_INV)
20956 NEON_ENCODE (LANE, inst);
20961 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20962 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20963 inst.instruction |= inst.operands[1].reg << 16;
20965 if (inst.operands[1].postind)
20967 int postreg = inst.operands[1].imm & 0xf;
20968 constraint (!inst.operands[1].immisreg,
20972 inst.instruction |= postreg;
20976 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
20977 constraint (inst.relocs[0].exp.X_op != O_constant
20978 || inst.relocs[0].exp.X_add_number != 0,
20981 if (inst.operands[1].writeback)
20983 inst.instruction |= 0xd;
20986 inst.instruction |= 0xf;
20990 inst.instruction |= 0xf9000000;
20992 inst.instruction |= 0xf4000000;
21005 NEON_ENCODE (FPV8, inst);
21019 inst.instruction |= 0x100;
21021 inst.instruction |= 0xf0000000;
21072 NEON_ENCODE (FPV8, inst);
21080 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
21081 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
21082 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
21083 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
21084 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
21085 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
21086 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
21090 inst.instruction |= (rs == NS_DD) << 8;
21100 inst.error = NULL;
21110 NEON_ENCODE (FLOAT, inst);
21112 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21113 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21114 inst.instruction |= LOW4 (inst.operands[1].reg);
21115 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
21116 inst.instruction |= neon_quad (rs) << 6;
21118 inst.instruction = ((inst.instruction & 0xfff3ffff)
21123 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
21124 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
21125 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
21126 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
21127 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
21128 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
21129 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
21134 inst.instruction |= 0xfc000000;
21136 inst.instruction |= 0xf0000000;
21203 constraint (inst.relocs[0].exp.X_op != O_constant,
21205 unsigned rot = inst.relocs[0].exp.X_add_number;
21214 if (inst.operands[2].isscalar)
21221 unsigned m = neon_scalar_for_vcmla (inst.operands[2].reg, size);
21222 inst.is_neon = 1;
21223 inst.instruction = 0xfe000800;
21224 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21225 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21226 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
21227 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
21228 inst.instruction |= LOW4 (m);
21229 inst.instruction |= HI1 (m) << 5;
21230 inst.instruction |= neon_quad (rs) << 6;
21231 inst.instruction |= rot << 20;
21232 inst.instruction |= (size == 32) << 23;
21245 && (inst.operands[0].reg == inst.operands[1].reg
21246 || inst.operands[0].reg == inst.operands[2].reg))
21250 inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
21251 inst.instruction |= 0xfc200800;
21252 inst.instruction |= rot << 23;
21253 inst.instruction |= (size == 32) << 20;
21263 constraint (inst.relocs[0].exp.X_op != O_constant,
21266 unsigned rot = inst.relocs[0].exp.X_add_number;
21280 if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
21295 inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
21296 inst.instruction |= 0xfc800800;
21297 inst.instruction |= (rot == 270) << 24;
21298 inst.instruction |= (et.size == 32) << 20;
21303 inst.instruction = 0xfe000f00;
21304 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21305 inst.instruction |= neon_logbits (et.size) << 20;
21306 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
21307 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21308 inst.instruction |= (rot == 270) << 12;
21309 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
21310 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
21311 inst.instruction |= LOW4 (inst.operands[2].reg);
21312 inst.is_neon = 1;
21325 if (inst.cond != COND_ALWAYS)
21334 if (inst.operands[2].isscalar)
21336 scalar_oprd2 = neon_scalar_for_mul (inst.operands[2].reg, 32);
21358 inst.instruction &= 0x00ffffff;
21359 inst.instruction |= high8;
21361 inst.instruction |= (unsigned_p ? 1 : 0) << 4;
21363 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21365 if (inst.operands[2].isscalar)
21367 inst.instruction &= 0xffffffd0;
21368 inst.instruction |= LOW4 (scalar_oprd2);
21369 inst.instruction |= HI1 (scalar_oprd2) << 5;
21394 if (inst.operands[2].isscalar)
21399 inst.instruction |= (1 << 25);
21400 int idx = inst.operands[2].reg & 0xf;
21402 inst.operands[2].reg >>= 4;
21403 constraint (!(inst.operands[2].reg < 16),
21406 inst.instruction |= (idx << 5);
21410 inst.instruction |= (1 << 21);
21422 if (inst.operands[2].isscalar)
21427 inst.instruction |= (1 << 25);
21428 int idx = inst.operands[2].reg & 0xf;
21430 inst.operands[2].reg >>= 4;
21431 constraint (!(inst.operands[2].reg < 16),
21434 inst.instruction |= (idx << 5);
21465 unsigned Rx = inst.operands[idx].reg;
21466 bool isvec = inst.operands[idx].isvec;
21497 unsigned coproc = inst.operands[0].reg;
21500 inst.instruction |= coproc << cde_coproc_pos;
21513 inst.error = BAD_SYNTAX;
21526 Rd = inst.operands[1].reg;
21531 constraint (inst.operands[2].reg != Rd + 1,
21533 imm = inst.operands[3].imm;
21536 imm = inst.operands[2].imm;
21540 inst.instruction |= Rd << 12;
21541 inst.instruction |= (imm & 0x1F80) << 9;
21542 inst.instruction |= (imm & 0x0040) << 1;
21543 inst.instruction |= (imm & 0x003f);
21557 Rd = inst.operands[1].reg;
21561 constraint (inst.operands[2].reg != Rd + 1,
21563 imm = inst.operands[4].imm;
21564 Rn = inst.operands[3].reg;
21568 imm = inst.operands[3].imm;
21569 Rn = inst.operands[2].reg;
21577 inst.instruction |= Rd << 12;
21578 inst.instruction |= Rn << 16;
21580 inst.instruction |= (imm & 0x0380) << 13;
21581 inst.instruction |= (imm & 0x0040) << 1;
21582 inst.instruction |= (imm & 0x003f);
21596 Rd = inst.operands[1].reg;
21600 constraint (inst.operands[2].reg != Rd + 1,
21602 imm = inst.operands[5].imm;
21603 Rn = inst.operands[3].reg;
21604 Rm = inst.operands[4].reg;
21608 imm = inst.operands[4].imm;
21609 Rn = inst.operands[2].reg;
21610 Rm = inst.operands[3].reg;
21619 inst.instruction |= Rd;
21620 inst.instruction |= Rn << 16;
21621 inst.instruction |= Rm << 12;
21623 inst.instruction |= (imm & 0x0038) << 17;
21624 inst.instruction |= (imm & 0x0004) << 5;
21625 inst.instruction |= (imm & 0x0003) << 4;
21706 inst.instruction |= HI4 (regnum) << 12;
21707 inst.instruction |= LOW1 (regnum) << 22;
21713 inst.instruction |= HI4 (regnum);
21714 inst.instruction |= LOW1 (regnum) << 5;
21720 inst.instruction |= HI4 (regnum) << 16;
21721 inst.instruction |= LOW1 (regnum) << 7;
21756 inst.instruction |= 1 << vcx_vec_pos;
21758 inst.instruction |= 1 << vcx_size_pos;
21815 R = inst.operands[i+1].reg;
21833 if (inst.cond > COND_ALWAYS)
21834 inst.pred_insn_type = INSIDE_VPT_INSN;
21836 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
21837 else if (inst.cond == COND_ALWAYS)
21838 inst.pred_insn_type = OUTSIDE_PRED_INSN;
21840 inst.error = BAD_NOT_IT;
21868 unsigned imm = inst.operands[2].imm;
21869 inst.instruction |= (imm & 0x03f);
21870 inst.instruction |= (imm & 0x040) << 1;
21871 inst.instruction |= (imm & 0x780) << 9;
21875 inst.instruction |= (imm & 0x800) << 13;
21884 unsigned imm = inst.operands[3].imm;
21885 inst.instruction |= (imm & 0x01) << 4;
21886 inst.instruction |= (imm & 0x02) << 6;
21887 inst.instruction |= (imm & 0x3c) << 14;
21891 inst.instruction |= (imm & 0x40) << 18;
21900 unsigned imm = inst.operands[4].imm;
21901 inst.instruction |= (imm & 0x1) << 4;
21902 inst.instruction |= (imm & 0x6) << 19;
21906 inst.instruction |= (imm & 0x8) << 21;
21919 inst.error = NULL;
21921 NEON_ENCODE (INTEGER, inst);
21922 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21923 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21924 inst.instruction |= LOW4 (inst.operands[1].reg);
21925 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
21927 inst.instruction |= op << 6;
21930 inst.instruction |= 0xfc000000;
21932 inst.instruction |= 0xf0000000;
21944 inst.error = NULL;
21946 NEON_ENCODE (INTEGER, inst);
22037 unsigned int Rd = inst.operands[0].reg;
22038 unsigned int Rn = inst.operands[1].reg;
22039 unsigned int Rm = inst.operands[2].reg;
22042 inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
22043 inst.instruction |= LOW4 (Rn) << 16;
22044 inst.instruction |= LOW4 (Rm);
22045 inst.instruction |= sz << (thumb_mode ? 4 : 21);
22046 inst.instruction |= poly << (thumb_mode ? 20 : 9);
22104 if (inst.operands[2].isscalar)
22109 inst.instruction |= (1 << 25);
22110 int idx = inst.operands[2].reg & 0xf;
22112 inst.operands[2].reg >>= 4;
22113 constraint (!(inst.operands[2].reg < 16),
22116 inst.instruction |= (idx << 5);
22141 inst.instruction = THUMB_OP32 (inst.instruction);
22150 inst.instruction = THUMB_OP32 (inst.instruction);
22151 inst.instruction |= inst.operands[0].reg << 12;
22152 inst.instruction |= inst.operands[1].reg << 16;
22153 inst.instruction |= inst.operands[2].reg;
22162 inst.instruction = THUMB_OP32 (inst.instruction);
22163 inst.instruction |= inst.operands[0].reg << 8;
22164 inst.instruction |= inst.operands[1].reg << 16;
22165 inst.instruction |= inst.operands[2].reg;
22245 switch (inst.relocs[0].exp.X_op)
22248 sym = inst.relocs[0].exp.X_add_symbol;
22249 offset = inst.relocs[0].exp.X_add_number;
22253 offset = inst.relocs[0].exp.X_add_number;
22256 sym = make_expr_symbol (&inst.relocs[0].exp);
22261 inst.relax, sym, offset, NULL/*offset, opcode*/);
22262 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
22278 if (inst.error)
22280 as_bad ("%s -- `%s'", inst.error, str);
22283 if (inst.relax)
22288 if (inst.size == 0)
22291 to = frag_more (inst.size);
22298 if (thumb_mode && (inst.size > THUMB_SIZE))
22300 gas_assert (inst.size == (2 * THUMB_SIZE));
22301 put_thumb32_insn (to, inst.instruction);
22303 else if (inst.size > INSN_SIZE)
22305 gas_assert (inst.size == (2 * INSN_SIZE));
22306 md_number_to_chars (to, inst.instruction, INSN_SIZE);
22307 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
22310 md_number_to_chars (to, inst.instruction, inst.size);
22315 if (inst.relocs[r].type != BFD_RELOC_UNUSED)
22317 inst.size, & inst.relocs[r].exp, inst.relocs[r].pc_rel,
22318 inst.relocs[r].type);
22321 dwarf2_emit_insn (inst.size);
22419 infix; look it up in the conditions table and set inst.cond
22421 Again set inst.cond accordingly. Return the opcode structure.
22425 Otherwise, set inst.cond from the suffix we already looked up,
22459 inst.size_req = 4;
22461 inst.size_req = 2;
22465 inst.vectype.elems = 0;
22473 if (parse_neon_type (&inst
22491 inst.cond = COND_ALWAYS;
22501 inst.cond = cond->value;
22567 inst.cond = cond->value;
22573 inst.cond = cond->value;
22577 inst.error = BAD_COND;
22578 inst.cond = COND_ALWAYS;
22616 inst.cond = cond->value;
22689 on the inst.condition.
22709 that determines the insn IT type depending on the inst.cond code.
22713 IT instruction type based on the inst.cond code. Otherwise,
22725 In that case, inst.error is set.
22726 Therefore, inst.error has to be checked after the execution of
22736 if (inst.cond != COND_ALWAYS)
22737 inst.pred_insn_type = INSIDE_IT_INSN;
22739 inst.pred_insn_type = OUTSIDE_PRED_INSN;
22785 switch (inst.pred_insn_type)
22789 if (inst.cond < COND_ALWAYS)
22793 inst.error = BAD_SYNTAX;
22799 if (inst.cond > COND_ALWAYS)
22803 inst.error = BAD_SYNTAX;
22812 inst.error = BAD_OUT_VPT;
22817 if (inst.cond < COND_ALWAYS)
22833 new_automatic_it_block (inst.cond);
22834 if (inst.pred_insn_type == INSIDE_IT_LAST_INSN)
22839 inst.error = BAD_OUT_IT;
22845 else if (inst.cond > COND_ALWAYS)
22849 inst.error = BAD_SYNTAX;
22859 if (inst.cond != COND_ALWAYS)
22882 switch (inst.pred_insn_type)
22901 || !now_pred_compatible (inst.cond))
22904 if (inst.pred_insn_type != IF_INSIDE_IT_LAST_INSN)
22905 new_automatic_it_block (inst.cond);
22910 now_pred_add_mask (inst.cond);
22914 && (inst.pred_insn_type == INSIDE_IT_LAST_INSN
22915 || inst.pred_insn_type == IF_INSIDE_IT_LAST_INSN))
22959 switch (inst.pred_insn_type)
22964 if (inst.cond == COND_ALWAYS)
22968 inst.error = BAD_NOT_IT;
22971 else if (inst.cond > COND_ALWAYS)
22975 inst.error = BAD_SYNTAX;
22986 inst.error = BAD_NOT_IT;
23000 if (inst.cond == COND_ALWAYS)
23007 else if (inst.cond < COND_ALWAYS)
23011 inst.error = BAD_SYNTAX;
23019 if (inst
23023 inst.error = BAD_SYNTAX;
23026 else if (inst.cond == COND_ALWAYS)
23030 inst.error = BAD_NOT_VPT;
23042 if (inst.cond > COND_ALWAYS)
23046 inst.error = BAD_SYNTAX;
23052 if (cond != inst.cond)
23054 inst.error = now_pred.type == SCALAR_PRED ? BAD_IT_COND :
23063 inst.error = BAD_OUT_IT;
23073 inst.error = BAD_OUT_VPT;
23077 else if (cond != inst.cond)
23079 inst.error = BAD_VPT_COND;
23085 if (now_pred.type == VECTOR_PRED || inst.cond > COND_ALWAYS)
23089 inst.error = BAD_SYNTAX;
23092 else if (cond != inst.cond)
23094 inst.error = BAD_IT_COND;
23099 inst.error = BAD_BRANCH;
23112 inst.error = BAD_IT_IT;
23117 if (inst.cond == COND_ALWAYS)
23131 inst.error = BAD_SYNTAX;
23180 if (inst.instruction >= 0x10000)
23192 if ((inst.instruction & p->mask) == p->pattern)
23314 memset (&inst, '\0', sizeof (inst));
23317 inst.relocs[r].type = BFD_RELOC_UNUSED;
23336 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1u;
23357 if (inst.cond != COND_ALWAYS && !unified_syntax
23375 if (inst.size_req == 0)
23376 inst.size_req = 2;
23377 else if (inst.size_req == 4)
23389 inst.instruction = opcode->tvalue;
23402 if (!(inst.error || inst.relax))
23404 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
23405 inst.size = (inst.instruction > 0xffff ? 4 : 2);
23406 if (inst.size_req && inst.size_req != inst.size)
23415 gas_assert (inst.size_req == 0 || !inst.relax);
23427 if (inst.size == 4 && !t32_insn_ok (variant, opcode))
23433 if (!inst.error)
23453 if (inst.size_req)
23459 inst.instruction = opcode->avalue;
23461 inst.instruction |= 0xFU << 28;
23463 inst.instruction |= inst.cond << 28;
23464 inst.size = INSN_SIZE;
23481 if (!inst.error)
Indexes created Sat Feb 28 05:31:39 UTC 2026