Lines Matching defs:src0
1159 REG_T dst, REG_T src0, REG_T src1, int w0)
1183 ASSIGN_R (src0);
1192 REG_T dst, REG_T src0, REG_T src1, int w0)
1214 ASSIGN_R (src0);
1222 REG_T dst0, REG_T dst1, REG_T src0, REG_T src1)
1233 ASSIGN_R (src0);
1240 bfin_gen_dsp32shift (int sopcde, REG_T dst0, REG_T src0,
1250 ASSIGN_R (src0);
1641 bfin_gen_comp3op (REG_T src0, REG_T src1, REG_T dst, int opc)
1645 ASSIGN_R (src0);
2250 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2304 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2344 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
2473 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
2477 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
2527 return DREG_MASK (src0) | DREG_MASK (src1);
2531 OUTS (outf, dregs (src0));
2538 return DREG_MASK (src0) | DREG_MASK (src1);
2542 OUTS (outf, dregs (src0));