Lines Matching defs:immed
892 unsigned int immed = 0, immed2 = 0, temp;
1032 immed = 0;
1037 immed = exp.X_add_number;
1060 inst |= (immed << IMM_LOW) & IMM_MASK;
1069 immed = immed + 4;
1074 inst |= (immed << IMM_LOW) & IMM_MASK;
1079 temp = immed & 0xFFFF8000;
1091 inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
1100 inst |= (immed << IMM_LOW) & IMM_MASK;
1135 immed = exp.X_add_number;
1138 if (immed != (immed % 32))
1141 immed = immed % 32;
1145 inst |= (immed << IMM_LOW) & IMM5_MASK;
1181 immed = 1;
1184 immed = exp.X_add_number;
1186 if (opcode->instr == bsefi && immed > 31)
1214 if (immed + immed2 > 32)
1221 inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */
1223 immed + immed2 - 1) & IMM5_MASK)
1292 op_end = parse_reg (op_end + 1, &immed); /* Get rfslN. */
1296 immed = 0;
1304 inst |= (immed << IMM_LOW) & RFSL_MASK;
1331 immed = exp.X_add_number;
1334 inst |= (immed << IMM_LOW) & IMM15_MASK;
1346 op_end = parse_reg (op_end + 1, &immed); /* Get rfslN. */
1350 immed = 0;
1358 inst |= (immed << IMM_LOW) & RFSL_MASK;
1364 op_end = parse_reg (op_end + 1, &immed); /* Get rfslN. */
1368 immed = 0;
1370 inst |= (immed << IMM_LOW) & RFSL_MASK;
1426 immed = opcode->immval_mask | REG_MSR_MASK;
1428 immed = opcode->immval_mask | REG_PC_MASK;
1430 immed = opcode->immval_mask | REG_EAR_MASK;
1432 immed = opcode->immval_mask | REG_ESR_MASK;
1434 immed = opcode->immval_mask | REG_FSR_MASK;
1436 immed = opcode->immval_mask | REG_BTR_MASK;
1438 immed = opcode->immval_mask | REG_EDR_MASK;
1440 immed = opcode->immval_mask | REG_PID_MASK;
1442 immed = opcode->immval_mask | REG_ZPR_MASK;
1444 immed = opcode->immval_mask | REG_TLBX_MASK;
1446 immed = opcode->immval_mask | REG_TLBLO_MASK;
1448 immed = opcode->immval_mask | REG_TLBHI_MASK;
1450 immed = opcode->immval_mask | REG_SHR_MASK;
1452 immed = opcode->immval_mask | REG_SLR_MASK;
1454 immed = opcode->immval_mask | REG_PVR_MASK | reg2;
1458 inst |= (immed << IMM_LOW) & IMM_MASK;
1479 immed = opcode->immval_mask | REG_MSR_MASK;
1481 immed = opcode->immval_mask | REG_PC_MASK;
1483 immed = opcode->immval_mask | REG_EAR_MASK;
1485 immed = opcode->immval_mask | REG_ESR_MASK;
1487 immed = opcode->immval_mask | REG_FSR_MASK;
1489 immed = opcode->immval_mask | REG_BTR_MASK;
1491 immed = opcode->immval_mask | REG_EDR_MASK;
1493 immed = opcode->immval_mask | REG_PID_MASK;
1495 immed = opcode->immval_mask | REG_ZPR_MASK;
1497 immed = opcode->immval_mask | REG_TLBX_MASK;
1499 immed = opcode->immval_mask | REG_TLBLO_MASK;
1501 immed = opcode->immval_mask | REG_TLBHI_MASK;
1503 immed = opcode->immval_mask | REG_TLBSX_MASK;
1505 immed = opcode->immval_mask | REG_SHR_MASK;
1507 immed = opcode->immval_mask | REG_SLR_MASK;
1511 inst |= (immed << IMM_LOW) & IMM_MASK;
1605 immed = 0;
1610 immed = exp.X_add_number;
1613 temp = immed & 0xFFFF8000;
1625 inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
1634 inst |= (immed << IMM_LOW) & IMM_MASK;
1671 immed = 0;
1676 immed = exp.X_add_number;
1679 temp = immed & 0xFFFF8000;
1691 inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
1700 inst |= (immed << IMM_LOW) & IMM_MASK;
1743 immed = 0;
1748 immed = exp.X_add_number;
1752 temp = immed & 0xFFFF8000;
1764 inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
1771 inst |= (immed << IMM_LOW) & IMM_MASK;
1787 immed = exp.X_add_number;
1789 if (immed != (immed % 32)) {
1791 immed = immed % 32;
1793 inst |= (immed << IMM_MBAR);