Lines Matching defs:the
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
36 /* The offset for pc-relative addressing is currently defined to be 0. */
41 /* An enum containing all known CPU features. The values act as bit positions
344 Then use REP_NO_SEP in the SEP field. */
361 /* These macros take an initial argument X that gives the index into
362 an aarch64_feature_set. The macros then return the bitmask for
375 /* A mask of the features that are enabled by each architecture version,
450 /* Architectures are the sum of the base and extensions. */
559 including all the features that are enabled by default for that architecture
587 version ARCH, and additionally provides the N features listed in "...". */
594 /* An aarch64_feature_set initializer for the N features listed in "...". */
702 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
703 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
704 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
706 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
712 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
722 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
727 AARCH64_OPND_COND, /* Standard condition as the last operand. */
728 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
741 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
744 is only used to support the programmer-
745 friendly feature of using LDR/STR as the
746 the mnemonic name for LDUR/STUR instructions
992 AARCH64_OPND_SME_ZT0, /* The fixed token zt0/ZT0 (not encoded). */
1025 indicating the operand data size or a specific register. */
1033 size or the size of each SIMD vector element in the case of a SIMD
1036 indicate the size of data element a load/store instruction is
1038 They are also used for the immediate shift operand in e.g. SSHR. Such
1039 a use is only for the ease of operand encoding/decoding and qualifier
1040 sequence matching; such a use should not be applied widely; use the value
1048 4 x 1 byte or 2 x 2 byte are selected by the instruction. Other than that
1058 They are also used for the immediate shift operand in e.g. SSHR. Such
1059 a use is only for the ease of operand encoding/decoding and qualifier
1060 sequence matching; such a use should not be applied widely; use the value
1095 /* Special qualifier helping retrieve qualifier information during the
1229 the,
1362 /* FIXME: improve the efficiency. */
1384 /* The name of the mnemonic. */
1387 /* The opcode itself. Those bits which will be filled in with
1391 /* The opcode mask. This is used by the disassembler. This is a
1392 mask containing ones indicating those bits which must match the
1406 /* An array of operand codes. Each code is an index into the
1407 operand table. They appear in the order which the operands must
1412 code qualifies the corresponding operand code. Each operand
1420 /* Extra constraints on the instruction that the verifier checks. */
1424 are required to have the same register number. */
1435 /* Table describing all the AArch64 opcodes. */
1441 /* Disassembly preference priority 1-3 (the larger the higher). If nothing
1442 is specified, it is the priority 0 by default, i.e. the lowest priority. */
1448 /* Instruction has the field of 'sf'. */
1450 /* Instruction has the field of 'size:Q'. */
1452 /* Floating-point instruction has the field of 'type'. */
1454 /* AdvSIMD scalar instruction has the field of 'size'. */
1468 /* Default value for the optional operand when omitted from the assembly. */
1471 encoded/decoded by converting it to/from the real form, followed by
1472 the encoding/decoding according to the rules of the real opcode.
1473 This compares to the direct coding using the alias's information.
1477 friendly pseudo instruction available only in the assembly code (thus will
1478 not show up in the disassembly). */
1482 /* Instruction has the field of 'N'; used in conjunction with F_SF. */
1486 /* Instruction has the field of 'sz'. */
1497 /* Instruction takes a pair of optional operands. If we specify the Nth operand
1501 /* This instruction does not allow the full range of values that the
1502 width of fields in the assembler instruction would theoretically
1503 allow. This impacts the constraints on assembly but yields no
1506 /* For the instruction with size[22:23] field. */
1508 /* RCPC3 instruction has the field of 'size'. */
1510 /* This instruction need VGx2 or VGx4 mandatorily in the operand passed to
1515 Note the overlap between the set of subclass flags in each logical category
1516 (F_LDST_*, F_ARITH_*, F_BRANCH_* etc.); The usage of flags as
1556 /* This instruction has a predication constraint on the instruction at PC+4. */
1558 /* This instruction's operation width is determined by the operand with the
1592 /* Whether the opcode has the specific subclass flag.
1593 N.B. The overlap between F_LDST_*, F_ARITH_*, and F_BRANCH_* etc. subclass
1594 flags means that the callers of this function have the responsibility of
1595 checking for the flags appropriate for the specific iclass. */
1602 /* Deal with two possible scenarios: If F_OP_PAIR_OPT not set, as is the case
1734 /* A list of names with the first one as the disassembly preference;
1754 /* The 32-bit index register. */
1757 /* The first (or only) immediate offset. */
1760 /* The last immediate offset minus the first immediate offset.
1761 Unlike the range size, this is guaranteed not to overflow
1762 when the end offset > the start offset. */
1766 /* The vector group size, or 0 if none. */
1779 /* The difference between the nth and the n+1th register. */
1835 /* The encoding of the system register. */
1838 /* The system register flags. During assembly this contains the
1840 either F_REG_READ or F_REG_WRITE, depending upon the opcode. */
1848 /* The encoding of the PSTATE field. */
1856 /* Operand shifter; in use when the operand is a register offset address,
1862 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
1869 cases, we need to tell libopcodes to skip the
1870 constraint checking and the encoding for this
1871 operand, so that the libopcodes can pick up the
1872 right opcode before the operand is fixed-up. This
1873 flag should only be used during the
1875 unsigned present:1; /* Whether this operand is present in the assembly
1876 line; not used during the disassembly. */
1883 It is used during both the assembling and disassembling. The assembler
1884 fills an aarch64_inst after a successful parsing and then passes it to the
1885 encoding routine to do the encoding. During the disassembling, the
1886 disassembler calls the decoding routine to decode a binary instruction; on a
1887 successful return, such a structure will be filled with information of the
1888 instruction; then the disassembler uses the information to print out the
1893 /* The value of the binary instruction. */
1906 /* Defining the HINT #imm values for the aarch64_hint_options. */
1926 Less severe error found during the parsing, very possibly because that
1927 GAS has picked up a wrong instruction template for the parsing.
1930 The instruction forms (or is expected to form) part of a sequence,
1931 but the preceding instruction in the sequence wasn't the expected one.
1932 The message refers to two strings: the name of the current instruction,
1933 followed by the name of the expected preceding instruction.
1936 Same as AARCH64_OPDE_A_SHOULD_FOLLOW_B, but shifting the focus
1937 so that the current instruction is assumed to be the incorrect one:
1938 "since the previous instruction was B, the current one should be A".
1948 No syntax error, but the operands are not a valid combination, e.g.
1951 The following errors are only reported against an asm string that is
1955 Error about a "VGx<n>" modifier in a ZA index not having the
1957 AARCH64_OPDE_REG_LIST_LENGTH, since both errors relate to the number
1958 of vectors that an instruction operates on. However, the "VGx<n>"
1961 importance on the register list length when selecting an opcode table
1968 opcode entry that supports the given number of registers.
1971 Error about a register list operand having the correct number
1974 that the length is known to be correct. However, it is lower than
1976 the same number of registers but have different strides.
1979 The asm failed to use the same immediate for a destination operand
1983 The asm failed to use the same register for a destination operand
1994 Error of the highest severity and used for any severe issue that does not
1995 fall into any of the above categories.
1998 A register was syntactically valid and had the right type, but it was
1999 outside the range supported by the associated operand field. This is
2001 would accept the operands that precede the erroneous one (if any) and
2005 AARCH64_OPDE_FATAL_SYNTAX_ERROR are only detected by GAS while the
2007 only libopcodes has the information about the valid variants of each
2010 The enumerators have an increasing severity. This is helpful when there are
2012 FMOV); this mechanism will help choose the most suitable template from which
2013 the generated diagnostics can most closely describe the issues, if any.
2056 /* The instructions in the sequence, starting with the one that
2059 /* The number of instructions already in the sequence. */
2061 /* The number of instructions allocated to the sequence. */
2076 /* Given the opcode enumerator OP, return the pointer to the corresponding
2083 the callback within this structure is used to apply styling to the
2084 disassembler output. This structure encapsulates the callback and a
2089 /* The callback used to apply styling. Returns a string created from FMT
2090 and ARGS with STYLE applied to the string. STYLER is a pointer back
2091 to this object so that the callback can access the state member.
2093 The string returned from this callback must remain valid until the
2100 /* A pointer to a state object which can be used by the apply_style
2105 /* Generate the string representation of an operand. */
2141 /* Given an operand qualifier, return the expected data element size
Indexes created Sat Mar 28 00:23:22 UTC 2026