Lines Matching refs:opnd
968 dump_match_qualifiers (const struct aarch64_opnd_info *opnd,
976 curr[i] = opnd[i].qualifier;
1591 /* Check that indexed register operand OPND has a register in the range
1596 check_reglane (const aarch64_opnd_info *opnd,
1601 if (!value_in_range_p (opnd->reglane.regno, min_regno, max_regno))
1607 if (!value_in_range_p (opnd->reglane.index, min_index, max_index))
1616 /* Check that register list operand OPND has NUM_REGS registers and a
1620 check_reglist (const aarch64_opnd_info *opnd,
1624 if (opnd->reglist.num_regs != num_regs)
1629 if (opnd->reglist.stride != stride)
1686 /* Check that indexed ZA operand OPND has:
1699 check_za_access (const aarch64_opnd_info *opnd,
1704 if (!value_in_range_p (opnd->indexed_za.index.regno, min_wreg, min_wreg + 3))
1720 if (!value_in_range_p (opnd->indexed_za.index.imm, 0, max_index))
1726 if ((opnd->indexed_za.index.imm % range_size) != 0)
1736 if (opnd->indexed_za.index.countm1 != range_size - 1)
1754 if (opnd->indexed_za.group_size != group_size
1755 && (status_vg || opnd->indexed_za.group_size != 0 ))
1812 const aarch64_opnd_info *opnd = opnds + idx;
1813 aarch64_opnd_qualifier_t qualifier = opnd->qualifier;
1816 assert (opcode->operands[idx] == opnd->type && opnd->type == type);
1879 if (!aarch64_stack_pointer_p (opnd))
1903 if (!check_reglane (opnd, mismatch_detail, idx,
1911 if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31, 0, 1))
1918 if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31, 0, 3))
1923 size = aarch64_get_qualifier_esize (opnd->qualifier);
1924 if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31,
1930 size = aarch64_get_qualifier_esize (opnd->qualifier);
1931 if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31,
1939 if (!check_reglane (opnd, mismatch_detail, idx, "pn", 8, 15,
1960 if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31,
1977 if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 15,
1983 if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31, 0, 3))
1985 if ((opnd->reglane.regno & 20) != 20)
1995 if (opnd->reg.regno > 15)
2003 if (opnd->reg.regno > 15 || opnd->reg.regno % 2 != 0)
2012 if (opnd->reg.regno < 16 || opnd->reg.regno % 2 != 0)
2021 size = aarch64_get_qualifier_esize (opnd->qualifier);
2023 if (!check_za_access (opnd, mismatch_detail, idx,
2047 if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
2049 if (((opnd->reglist.first_regno % num) != 0)
2051 && opnd->reglist.first_regno > 15)
2053 && opnd->reglist.first_regno < 16))
2066 if (!check_reglist (opnd, mismatch_detail, idx, num, 16 / num))
2068 num = 16 | (opnd->reglist.stride - 1);
2069 if ((opnd->reglist.first_regno & ~num) != 0)
2081 if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
2087 if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
2093 if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
2095 if (opnd->reglist.first_regno > 7)
2113 size = aarch64_get_qualifier_esize (opnd->qualifier);
2115 if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value, 1,
2122 if (!check_za_access (opnd, mismatch_detail, idx, 12, 15, 1,
2130 if (!check_za_access (opnd, mismatch_detail, idx, 8, 7, 1,
2137 if (!check_za_access (opnd, mismatch_detail, idx, 8, 1, 4,
2144 if (!check_za_access (opnd, mismatch_detail, idx, 8, 3, 2,
2151 if (!check_za_access (opnd, mismatch_detail, idx, 8, 3, 4,
2158 if (!check_za_access (opnd, mismatch_detail, idx, 8, 7, 2,
2165 if (!check_za_access (opnd, mismatch_detail, idx, 12, 7, 2,
2172 if (!check_za_access (opnd, mismatch_detail, idx, 12, 3, 2,
2179 if (!check_za_access (opnd, mismatch_detail, idx, 12, 1, 2,
2186 if (!check_za_access (opnd, mismatch_detail, idx, 12, 0, 2,
2193 if (!check_za_access (opnd, mismatch_detail, idx, 12, 3, 4,
2200 if (!check_za_access (opnd, mismatch_detail, idx, 12, 1, 4,
2207 if (!check_za_access (opnd, mismatch_detail, idx, 12, 15, 1,
2215 if (!check_za_access (opnd, mismatch_detail, idx, 12, 0, 4,
2223 size = aarch64_get_qualifier_esize (opnd->qualifier);
2228 if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value, num,
2243 if (opnd->reg.regno < 8)
2251 if (opnd->reg.regno >= 8
2279 if (opnd->addr.writeback == 1)
2287 if (opnd->addr.writeback == 1 && opnd->addr.preind != 1)
2298 if (opnd->addr.writeback == 0)
2306 if (opnd->addr.writeback)
2308 && !opnd->addr.preind)
2310 && !opnd->addr.postind))
2319 assert (opnd->addr.writeback == 0);
2329 size = aarch64_get_qualifier_esize (opnd->qualifier);
2330 if (!value_in_range_p (opnd->addr.offset.imm, -64 * size, 63 * size))
2336 if (!value_aligned_p (opnd->addr.offset.imm, size))
2345 if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
2356 if ((value_in_range_p (opnd->addr.offset.imm, 0, 255)
2357 && !value_aligned_p (opnd->addr.offset.imm, size))
2358 || value_in_range_p (opnd->addr.offset.imm, -256, -1))
2366 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4088))
2371 if (!value_aligned_p (opnd->addr.offset.imm, 8))
2380 if (!value_in_range_p (opnd->addr.offset.imm, -1024, 1008))
2386 if (!value_aligned_p (opnd->addr.offset.imm, 16))
2395 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4080))
2401 if (!value_aligned_p (opnd->addr.offset.imm, 16))
2411 if (opnd->addr.offset.is_reg)
2413 if (value_in_range_p (opnd->addr.offset.regno, 0, 30))
2437 if ((int) num_bytes != opnd->addr.offset.imm)
2450 size = aarch64_get_qualifier_esize (opnd->qualifier);
2452 if (opnd->shifter.amount != 0
2453 && opnd->shifter.amount != (int)get_logsz (size))
2461 switch (opnd->shifter.kind)
2475 imm = opnd->addr.offset.imm;
2480 if (!value_in_range_p (opnd->addr.offset.imm, 0, 4095 * size))
2486 if (!value_aligned_p (opnd->addr.offset.imm, size))
2499 imm = opnd->imm.value;
2520 if (!value_in_range_p (opnd->addr.offset.imm, 0, 15))
2534 assert (!opnd->addr.offset.is_reg);
2535 assert (opnd->addr.preind);
2539 if ((opndopnd->shifter.operator_present)
2540 || (opnd->shifter.operator_present
2541 && opnd->shifter.kind != AARCH64_MOD_MUL_VL))
2547 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
2553 if (!value_aligned_p (opnd->addr.offset.imm, num))
2577 assert (!opnd->addr.offset.is_reg);
2578 assert (opnd->addr.preind);
2582 if (opnd->shifter.operator_present
2583 || opnd->shifter.amount_present)
2589 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
2595 if (!value_aligned_p (opnd->addr.offset.imm, num))
2612 assert (opnd->addr.offset.is_reg);
2613 assert (opnd->addr.preind);
2615 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
2616 assert (opnd->shifter.operator_present == 0);
2640 assert (opnd->addr.offset.is_reg);
2641 assert (opnd->addr.preind);
2643 && opnd->addr.offset.regno == 31)
2649 if (((1 << opnd->shifter.kind) & modifiers) == 0
2650 || (opnd->shifter.amount
2681 assert (opnd->addr.offset.is_reg);
2682 assert (opnd->addr.preind);
2683 if (((1 << opnd->shifter.kind) & modifiers) == 0
2684 || opnd->shifter.amount < 0
2685 || opnd->shifter.amount > 3)
2709 ? opnd->addr.offset.imm * -1
2710 : opnd->addr.offset.imm;
2712 && opnd->addr.offset.imm != 0)
2722 if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
2738 if (!value_in_range_p (opnd->reglist.index, 0, num))
2750 if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
2757 if (num != 1 && !check_reglist (opnd, mismatch_detail, idx, num, 1))
2765 if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
2771 if (opnd->reglist.stride != 1)
2780 imm = opnd->imm.value;
2795 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2801 if (opnd->shifter.amount != 0 && opnd->shifter.amount != 12)
2807 if (!value_fit_unsigned_field_p (opnd->imm.value, 12))
2817 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2824 if (!value_aligned_p (opnd->shifter.amount, 16))
2830 if (!value_in_range_p (opnd->shifter.amount, 0, size * 8 - 16))
2836 if (opnd->imm.value < 0)
2842 if (!value_fit_unsigned_field_p (opnd->imm.value, 16))
2853 imm = opnd->imm.value;
2901 if (!value_fit_unsigned_field_p (opnd->imm.value, size))
2911 if (!value_in_range_p (opnd->imm.value, 0, 1008))
2917 if (!value_aligned_p (opnd->imm.value, 16))
2932 if (!value_fit_signed_field_p (opnd->imm.value, size))
2945 if (opnd->imm.value + opnds[idx-1].imm.value > size)
2958 uint64_t uimm = opnd->imm.value;
2972 if (opnd->imm.value != 0)
2983 if (opnd->imm.value != 0
2984 && opnd->imm.value != 90
2985 && opnd->imm.value != 180
2986 && opnd->imm.value != 270)
2997 if (opnd->imm.value != 90 && opnd->imm.value != 270)
3008 if (opnd->imm.value != size)
3018 if (!value_in_range_p (opnd->imm.value, 0, size * 8 - 1))
3028 if (!value_in_range_p (opnd->imm.value, 1, size * 8))
3041 if (opnd->shifter.kind != AARCH64_MOD_LSL)
3049 if (opnd->shifter.kind != AARCH64_MOD_MSL)
3057 if (opnd->shifter.kind != AARCH64_MOD_NONE)
3073 if (!value_in_range_p (opnd->imm.value, -128, 255))
3079 else if (aarch64_shrink_expanded_imm8 (opnd->imm.value) < 0)
3089 switch (opnd->shifter.kind)
3093 if (!value_in_range_p (opnd->shifter.amount, 0, (size - 1) * 8))
3099 if (!value_aligned_p (opnd->shifter.amount, 8))
3107 if (opnd->shifter.amount != 8 && opnd->shifter.amount != 16)
3115 if (opnd->shifter.kind != AARCH64_MOD_NONE)
3128 if (opnd->imm.is_fp == 0)
3138 if (!value_in_range_p (opnd->imm.value, 0, 255))
3144 if (opnd->shifter.kind != AARCH64_MOD_NONE)
3155 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
3158 uvalue = opnd->imm.value;
3159 shift = opnd->shifter.amount;
3205 assert (opnd->imm.is_fp);
3206 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x3f800000)
3215 assert (opnd->imm.is_fp);
3216 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x40000000)
3225 assert (opnd->imm.is_fp);
3226 if (opnd->imm.value != 0 && opnd->imm.value != 0x3f800000)
3237 uint64_t uimm = ~opnd->imm.value;
3250 uint64_t uimm = opnd->imm.value;
3267 assert (opnd->shifter.kind == AARCH64_MOD_MUL);
3268 if (!value_in_range_p (opnd->shifter.amount, 1, 16))
3279 if (!value_in_range_p (opnd->imm.value, 0, 8 * size - 1))
3290 if (!value_in_range_p (opnd->imm.value, 1, size))
3303 if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
3311 if (!value_in_range_p (opnd->imm.value, 0, 56))
3316 if (opnd->imm.value % 8 != 0)
3325 if (!value_in_range_p (opnd->imm.value, 0, 3))
3342 if (aarch64_pstatefields[i].value == opnd->pstatefield)
3354 if (opcode->iclass == ldst_regoff && opnd->prfop->value >= 24)
3377 if (!check_reglane (opnd, mismatch_detail, idx, "v", 0, 31,
3388 if (!value_in_range_p (opnd->reglane.index, 0, num))
3404 && !value_in_range_p (opnd->reglane.regno, 0, 15))
3410 && !value_in_range_p (opnd->reglane.regno, 0, 7))
3422 if (!aarch64_extend_operator_p (opnd->shifter.kind)
3423 && opnd->shifter.kind != AARCH64_MOD_LSL)
3436 if (!opnd->shifter.operator_present)
3442 else if (opnd->shifter.kind == AARCH64_MOD_LSL)
3449 assert (opnd->shifter.operator_present /* Default to LSL. */
3450 || opnd->shifter.kind == AARCH64_MOD_LSL);
3451 if (!value_in_range_p (opnd->shifter.amount, 0, 4))
3462 && opnd->shifter.kind != AARCH64_MOD_LSL
3463 && opnd->shifter.kind != AARCH64_MOD_UXTX
3464 && opnd->shifter.kind != AARCH64_MOD_SXTX)
3474 if (!aarch64_shift_operator_p (opnd->shifter.kind))
3480 if (opnd->shifter.kind == AARCH64_MOD_ROR
3488 if (!value_in_range_p (opnd->shifter.amount, 0, num))
3496 /* We expect here that opnd->shifter.kind != AARCH64_MOD_LSL
3499 if (!value_in_range_p (opnd->shifter.amount, 0, 7))
3744 /* Get the name of the integer offset register in OPND, using the shift type
3748 get_offset_int_reg_name (const aarch64_opnd_info *opnd)
3750 switch (opnd->shifter.kind)
3754 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_W, 0);
3758 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_X, 0);
3765 /* Get the name of the SVE vector offset register in OPND, using the operand
3900 /* Produce the string representation of the register list operand *OPND
3904 print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
3908 const int num_regs = opnd->reglist.num_regs;
3909 const int stride = opnd->reglist.stride;
3910 const int first_reg = opnd->reglist.first_regno;
3912 const char *qlf_name = aarch64_get_qualifier_name (opnd->qualifier);
3915 assert (opnd->type != AARCH64_OPND_LEt || opnd->reglist.has_index);
3919 if (opnd->reglist.has_index)
3922 style_imm (styler, "%" PRIi64, (opnd->reglist.index % 100)));
3930 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3977 /* Print the register+immediate address in OPND to BUF, which has SIZE
3982 const aarch64_opnd_info *opnd,
3986 if (opnd->addr.writeback)
3988 if (opnd->addr.preind)
3990 if (opnd->type == AARCH64_OPND_ADDR_SIMM10 && !opnd->addr.offset.imm)
3995 style_imm (styler, "#%d", opnd->addr.offset.imm));
4000 style_imm (styler, "#%d", opnd->addr.offset.imm));
4004 if (opnd->shifter.operator_present)
4006 assert (opnd->shifter.kind == AARCH64_MOD_MUL_VL);
4009 style_imm (styler, "#%d", opnd->addr.offset.imm),
4012 else if (opnd->addr.offset.imm)
4015 style_imm (styler, "#%d", opnd->addr.offset.imm));
4022 *OPND in the buffer pointed by BUF of size SIZE. BASE and OFFSET are
4026 const aarch64_opnd_info *opnd,
4033 const char *shift_name = aarch64_operand_modifiers[opnd->shifter.kind].name;
4037 if (opnd->type == AARCH64_OPND_SVE_ADDR_ZX && offset != NULL
4047 if (!opnd->shifter.amount && (opnd->qualifier != AARCH64_OPND_QLF_S_B
4048 || !opnd->shifter.amount_present))
4056 if (opnd->shifter.kind == AARCH64_MOD_LSL)
4069 (opnd->shifter.amount % 100)));
4158 const aarch64_opnd_info *opnd = opnds + idx;
4174 switch (opnd->type)
4192 the <ic_op>, therefore we use opnd->present to override the
4194 if (opnd->type == AARCH64_OPND_Rt_SYS)
4196 if (!opnd->present)
4199 else if ((opnd->type == AARCH64_OPND_Rt_IN_SYS_ALIASES)
4200 && (opnd->reg.regno
4205 snprintf (comment, comment_size, "unpredictable encoding (Rt!=31): #%u", opnd->reg.regno);
4210 opnd->reg.regno
4213 assert (opnd->qualifier == AARCH64_OPND_QLF_W
4214 || opnd->qualifier == AARCH64_OPND_QLF_X);
4216 style_reg (styler, get_int_reg_name (opnd->reg.regno,
4217 opnd->qualifier, 0)));
4225 assert (opnd->qualifier == AARCH64_OPND_QLF_W
4226 || opnd->qualifier == AARCH64_OPND_QLF_WSP
4227 || opnd->qualifier == AARCH64_OPND_QLF_X
4228 || opnd->qualifier == AARCH64_OPND_QLF_SP);
4230 style_reg (styler, get_int_reg_name (opnd->reg.regno,
4231 opnd->qualifier, 1)));
4235 kind = opnd->shifter.kind;
4239 && ((opnd->qualifier == AARCH64_OPND_QLF_W
4242 || (opnd->qualifier == AARCH64_OPND_QLF_X
4247 if (opnd->shifter.amount == 0)
4252 get_int_reg_name (opnd->reg.regno,
4253 opnd->qualifier, 0)));
4257 if (opnd->shifter.amount)
4259 style_reg (styler, get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0)),
4261 style_imm (styler, "#%" PRIi64, opnd->shifter.amount));
4264 style_reg (styler, get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0)),
4269 assert (opnd->qualifier == AARCH64_OPND_QLF_W
4270 || opnd->qualifier == AARCH64_OPND_QLF_X);
4271 if (opnd->shifter.amount == 0 && opnd->shifter.kind == AARCH64_MOD_LSL)
4273 style_reg (styler, get_int_reg_name (opnd->reg.regno,
4274 opnd->qualifier, 0)));
4277 style_reg (styler, get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0)),
4278 style_sub_mnem (styler, aarch64_operand_modifiers[opnd->shifter.kind].name),
4279 style_imm (styler, "#%" PRIi64, opnd->shifter.amount));
4283 assert (opnd->qualifier == AARCH64_OPND_QLF_X);
4284 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
4285 if (opnd->shifter.amount == 0)
4287 style_reg (styler, get_int_reg_name (opnd->reg.regno,
4288 opnd->qualifier, 0)));
4291 style_reg (styler, get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0)),
4292 style_sub_mnem (styler, aarch64_operand_modifiers[opnd->shifter.kind].name),
4293 style_imm (styler, "#%" PRIi64, opnd->shifter.amount));
4311 aarch64_get_qualifier_name (opnd->qualifier),
4312 opnd->reg.regno));
4320 style_reg (styler, "v%d.%s", opnd->reg.regno,
4321 aarch64_get_qualifier_name (opnd->qualifier)));
4331 style_reg (styler, "v%d.%s", opnd->reglane.regno,
4332 aarch64_get_qualifier_name (opnd->qualifier)),
4333 style_imm (styler, "%" PRIi64, opnd->reglane.index));
4340 style_reg (styler, "v%d", opnd->reglane.regno),
4341 style_imm (styler, "%" PRIi64, opnd->reglane.index));
4347 style_reg (styler, "v%d.d", opnd->reg.regno),
4356 print_register_list (buf, size, opnd, "v", styler);
4368 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
4370 style_reg (styler, "p%d", opnd->reg.regno));
4371 else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z
4372 || opnd->qualifier == AARCH64_OPND_QLF_P_M)
4374 style_reg (styler, "p%d/%s", opnd->reg.regno,
4375 aarch64_get_qualifier_name (opnd->qualifier)));
4378 style_reg (styler, "p%d.%s", opnd->reg.regno,
4379 aarch64_get_qualifier_name (opnd->qualifier)));
4389 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
4391 style_reg (styler, "pn%d", opnd->reg.regno));
4392 else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z
4393 || opnd->qualifier == AARCH64_OPND_QLF_P_M)
4395 style_reg (styler, "pn%d/%s", opnd->reg.regno,
4396 aarch64_get_qualifier_name (opnd->qualifier)));
4399 style_reg (styler, "pn%d.%s", opnd->reg.regno,
4400 aarch64_get_qualifier_name (opnd->qualifier)));
4405 print_register_list (buf, size, opnd, "p", styler);
4411 style_reg (styler, "pn%d", opnd->reglane.regno),
4412 style_imm (styler, "%" PRIi64, opnd->reglane.index));
4426 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
4427 snprintf (buf, size, "%s", style_reg (styler, "z%d", opnd->reg.regno));
4430 style_reg (styler, "z%d.%s", opnd->reg.regno,
4431 aarch64_get_qualifier_name (opnd->qualifier)));
4449 print_register_list (buf, size, opnd, "z", styler);
4484 (opnd->qualifier == AARCH64_OPND_QLF_NIL
4485 ? style_reg (styler, "z%d", opnd->reglane.regno)
4486 : style_reg (styler, "z%d.%s", opnd->reglane.regno,
4487 aarch64_get_qualifier_name (opnd->qualifier))),
4488 style_imm (styler, "%" PRIi64, opnd->reglane.index));
4499 if (opnd->reglane.index == 0)
4500 snprintf (buf, size, "%s", style_reg (styler, "z%d", opnd->reg.regno));
4503 style_reg (styler, "z%d", opnd->reglane.regno),
4504 style_imm (styler, "%" PRIi64, opnd->reglane.index));
4511 style_reg (styler, "za%d.%s", opnd->reg.regno,
4512 aarch64_get_qualifier_name (opnd->qualifier)));
4530 opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "{" : "",
4532 opnd->indexed_za.regno,
4533 opnd->indexed_za.v == 1 ? 'v' : 'h',
4534 opnd->qualifier == AARCH64_OPND_QLF_NIL ? "" : ".",
4535 (opnd->qualifier == AARCH64_OPND_QLF_NIL
4537 : aarch64_get_qualifier_name (opnd->qualifier))),
4538 style_reg (styler, "w%d", opnd->indexed_za.index.regno),
4539 style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm),
4540 opnd->indexed_za.index.countm1 ? ":" : "",
4541 (opnd->indexed_za.index.countm1
4543 opnd->indexed_za.index.imm
4544 + opnd->indexed_za.index.countm1)
4546 opnd->indexed_za.group_size ? ", " : "",
4547 opnd->indexed_za.group_size == 2
4549 : opnd->indexed_za.group_size == 4
4551 opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "}" : "");
4555 print_sme_za_list (buf, size, opnd->imm.value, styler);
4567 opnd->qualifier == AARCH64_OPND_QLF_NIL ? "" : ".",
4568 (opnd->qualifier == AARCH64_OPND_QLF_NIL
4570 : aarch64_get_qualifier_name (opnd->qualifier))),
4571 style_reg (styler, "w%d", opnd->indexed_za.index.regno),
4572 style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm),
4573 opnd->indexed_za.index.countm1 ? ":" : "",
4574 (opnd->indexed_za.index.countm1
4576 opnd->indexed_za.index.imm
4577 + opnd->indexed_za.index.countm1)
4579 opnd->indexed_za.group_size ? ", " : "",
4580 opnd->indexed_za.group_size == 2
4582 : opnd->indexed_za.group_size == 4
4588 style_reg (styler, opnd->reg.regno == 's' ? "sm" : "za"));
4593 style_reg (styler, "p%d.%s", opnd->indexed_za.regno,
4594 aarch64_get_qualifier_name (opnd->qualifier)),
4595 style_reg (styler, "w%d", opnd->indexed_za.index.regno),
4596 style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm));
4601 enum_value = opnd->imm.value;
4608 enum_value = opnd->imm.value;
4617 style_reg (styler, "C%" PRIi64, opnd->imm.value));
4665 style_imm (styler, "#%" PRIi64, opnd->imm.value));
4673 c.i = opnd->imm.value;
4680 opnd->imm.value == get_optional_operand_default_value (opcode))
4682 enum_value = opnd->imm.value;
4689 style_imm (styler, "#%" PRIi64, opnd->imm.value));
4694 && !opnd->shifter.operator_present
4695 && opnd->imm.value == get_optional_operand_default_value (opcode))
4697 enum_value = opnd->imm.value;
4699 if (aarch64_sve_pattern_array[opnd->imm.value])
4702 aarch64_sve_pattern_array[opnd->imm.value]));
4705 style_imm (styler, "#%" PRIi64, opnd->imm.value));
4706 if (opnd->shifter.operator_present)
4710 = aarch64_operand_modifiers[opnd->shifter.kind].name;
4713 style_imm (styler, "#%" PRIi64, opnd->shifter.amount));
4718 enum_value = opnd->imm.value;
4725 style_imm (styler, "#%" PRIi64, opnd->imm.value));
4733 int imm32 = opnd->imm.value;
4741 opnd->imm.value));
4742 snprintf (comment, comment_size, "#%" PRIi64, opnd->imm.value);
4760 if (opnd->shifter.amount)
4762 style_imm (styler, "#0x%" PRIx64, opnd->imm.value),
4764 style_imm (styler, "#%" PRIi64, opnd->shifter.amount));
4767 style_imm (styler, "#0x%" PRIx64, opnd->imm.value));
4772 if ((! opnd->shifter.amount && opnd->shifter.kind == AARCH64_MOD_LSL)
4773 || opnd->shifter.kind == AARCH64_MOD_NONE)
4775 style_imm (styler, "#0x%" PRIx64, opnd->imm.value));
4778 style_imm (styler, "#0x%" PRIx64, opnd->imm.value),
4779 style_sub_mnem (styler, aarch64_operand_modifiers[opnd->shifter.kind].name),
4780 style_imm (styler, "#%" PRIi64, opnd->shifter.amount));
4785 if (opnd->shifter.amount)
4787 style_imm (styler, "#%" PRIi64, opnd->imm.value),
4789 style_imm (styler, "#%" PRIi64, opnd->shifter.amount));
4792 style_imm (styler, "#%" PRIi64, opnd->imm.value));
4803 c.i = expand_fp_imm (2, opnd->imm.value);
4810 c.i = expand_fp_imm (4, opnd->imm.value);
4817 c.i = expand_fp_imm (8, opnd->imm.value);
4835 && (opnd->imm.value ==
4840 style_imm (styler, "#0x%x", (unsigned int) opnd->imm.value));
4846 style_sub_mnem (styler, opnd->cond->names[0]));
4847 num_conds = ARRAY_SIZE (opnd->cond->names);
4848 for (i = 1; i < num_conds && opnd->cond->names[i]; ++i)
4853 opnd->cond->names[0], opnd->cond->names[i]);
4856 opnd->cond->names[i]);
4862 + opnd->imm.value;
4879 addr = pc + AARCH64_PCREL_OFFSET + opnd->imm.value;
4894 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
4895 if (opnd->type == AARCH64_OPND_SIMD_ADDR_POST)
4897 if (opnd->addr.offset.is_reg)
4900 style_reg (styler, "x%d", opnd->addr.offset.regno));
4904 style_imm (styler, "#%d", opnd->addr.offset.imm));
4927 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
4928 get_offset_int_reg_name (opnd), styler);
4933 (buf, size, opnd,
4934 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
4935 get_64bit_int_reg_name (opnd->addr.offset.regno, 0), styler);
4951 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
4952 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier),
4982 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
4991 (buf, size, opnd,
4992 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
5000 (buf, size, opnd,
5001 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
5002 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier),
5007 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
5008 if (opnd->addr.offset.imm)
5011 style_imm (styler, "#%d", opnd->addr.offset.imm));
5021 uint32_t op_flags = opnd->sysreg.flags;
5026 if (!(aarch64_sys_regs[i].value == opnd->sysreg.value)
5051 unsigned int value = opnd->sysreg.value;
5077 if (aarch64_pstatefields[i].value == opnd->pstatefield)
5083 && (PSTATE_DECODE_CRM (opnd->sysreg.flags)
5104 snprintf (buf, size, "%s", style_reg (styler, opnd->sysins_op->name));
5110 if (opnd->barrier->name[0] == '#')
5111 snprintf (buf, size, "%s", style_imm (styler, opnd->barrier->name));
5114 style_sub_mnem (styler, opnd->barrier->name));
5121 || (opnd->barrier->value
5124 style_imm (styler, "#0x%x", opnd->barrier->value));
5128 if ((opnd->prfop->name == NULL)
5129 || (opcode->iclass != ldst_pos && opnd->prfop->value == 0x18))
5131 style_imm (styler, "#0x%02x", opnd->prfop->value));
5133 snprintf (buf, size, "%s", style_sub_mnem (styler, opnd->prfop->name));
5137 enum_value = opnd->imm.value;
5144 style_imm (styler, "#%" PRIi64, opnd->imm.value));
5161 style_imm (styler, "%d", (int) opnd->imm.value));
5165 style_imm (styler, "%d", (int) opnd->imm.value),
5179 if (opnd->imm.value)
5185 style_sub_mnem (styler, opnd->hint_option->name));
5189 snprintf (buf, size, "%s", style_sub_mnem (styler, opnd->hint_option->name));
5193 if (*(opnd->hint_option->name))
5195 style_sub_mnem (styler, opnd->hint_option->name));
5202 get_int_reg_name (opnd->reg.regno,
5208 style_reg (styler, get_int_reg_name (opnd->reg.regno,
Indexes created Thu May 07 00:24:58 UTC 2026