Lines Matching defs:Vex
234 vex;
236 /* For APX EVEX-promoted prefix, EVEX.ND shares the same bit as vex.b. */
588 #define Vex { OP_VEX, x_mode }
728 /* operand size depends on REX.W / VEX.W. */
752 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
754 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
1907 'V' => print 'v' for VEX/EVEX and nothing for legacy encodings.
1926 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1932 "XV" => print "{vex} " pseudo prefix
1951 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1953 "BW" => print 'b' or 'w' depending on the VEX.W bit
3039 { "vpsrlw", { Vex, Ux, Ib }, PREFIX_DATA },
3041 { "vpsraw", { Vex, Ux, Ib }, PREFIX_DATA },
3043 { "vpsllw", { Vex, Ux, Ib }, PREFIX_DATA },
3049 { "vpsrld", { Vex, Ux, Ib }, PREFIX_DATA },
3051 { "vpsrad", { Vex, Ux, Ib }, PREFIX_DATA },
3053 { "vpslld", { Vex, Ux, Ib }, PREFIX_DATA },
3059 { "vpsrlq", { Vex, Ux, Ib }, PREFIX_DATA },
3060 { "vpsrldq", { Vex, Ux, Ib }, PREFIX_DATA },
3063 { "vpsllq", { Vex, Ux, Ib }, PREFIX_DATA },
3064 { "vpslldq", { Vex, Ux, Ib }, PREFIX_DATA },
3313 { "%XEVmovlpYX", { XM, Vex, Mq }, 0 },
3321 { "%XEVmovhpYX", { XM, Vex, Mq }, 0 },
3440 { "%XEVaddpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3442 { "%XEVaddpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3448 { "%XEVmulpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3450 { "%XEVmulpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3471 { "%XEVsubpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3473 { "%XEVsubpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3479 { "%XEVminpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3481 { "%XEVminpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3487 { "%XEVdivpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3489 { "%XEVdivpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3495 { "%XEVmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3497 { "%XEVmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3557 { "Vhaddpd", { XM, Vex, EXx }, 0 },
3558 { "Vhaddps", { XM, Vex, EXx }, 0 },
3565 { "Vhsubpd", { XM, Vex, EXx }, 0 },
3566 { "Vhsubps", { XM, Vex, EXx }, 0 },
3689 { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3691 { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3720 { "VaddsubpX", { XM, Vex, EXx }, 0 },
3721 { "VaddsubpX", { XM, Vex, EXx }, 0 },
4168 { "%XEvpdpbuud", { XM, Vex, EXx }, 0 },
4169 { "%XEvpdpbsud", { XM, Vex, EXx }, 0 },
4170 { "%XVvpdpbusd", { XM, Vex, EXx }, 0 },
4171 { "%XEvpdpbssd", { XM, Vex, EXx }, 0 },
4176 { "%XEvpdpbuuds", { XM, Vex, EXx }, 0 },
4177 { "%XEvpdpbsuds", { XM, Vex, EXx }, 0 },
4178 { "%XVvpdpbusds", { XM, Vex, EXx }, 0 },
4179 { "%XEvpdpbssds", { XM, Vex, EXx }, 0 },
4256 { "%XEvpdpwuud", { XM, Vex, EXx }, 0 },
4257 { "%XEvpdpwsud", { XM, Vex, EXx }, 0 },
4258 { "%XEvpdpwusd", { XM, Vex, EXx }, 0 },
4263 { "%XEvpdpwuuds", { XM, Vex, EXx }, 0 },
4264 { "%XEvpdpwsuds", { XM, Vex, EXx }, 0 },
4265 { "%XEvpdpwusds", { XM, Vex, EXx }, 0 },
4295 { "%XEvsm4key4", { XM, Vex, EXx }, 0 },
4297 { "%XEvsm4rnds4", { XM, Vex, EXx }, 0 },
5625 { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 },
6341 { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6342 { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6413 { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6414 { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6415 { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6416 { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6427 { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
6428 { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
6429 { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
6430 { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
6431 { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA },
6432 { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA },
6433 { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA },
6434 { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
6436 { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
6437 { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
6438 { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
6439 { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA },
6440 { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA },
6441 { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA },
6449 { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
6450 { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
6451 { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
6541 { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6554 { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
6555 { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
6556 { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
6557 { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA },
6558 { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA },
6562 { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
6563 { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
6564 { "vpminub", { XM, Vex, EXx }, PREFIX_DATA },
6565 { "vpand", { XM, Vex, EXx }, PREFIX_DATA },
6566 { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
6567 { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
6568 { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA },
6569 { "vpandn", { XM, Vex, EXx }, PREFIX_DATA },
6571 { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA },
6572 { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
6573 { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA },
6574 { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA },
6575 { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
6576 { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
6580 { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
6581 { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6582 { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA },
6583 { "vpor", { XM, Vex, EXx }, PREFIX_DATA },
6584 { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA },
6585 { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6586 { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
6587 { "vpxor", { XM, Vex, EXx }, PREFIX_DATA },
6590 { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
6591 { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
6592 { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
6593 { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
6594 { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
6595 { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA },
6598 { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA },
6599 { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA },
6600 { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA },
6601 { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA },
6602 Vex, EXx }, PREFIX_DATA },
6603 { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA },
6604 { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
6610 { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA },
6611 { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA },
6612 { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA },
6613 { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6614 { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
6615 { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA },
6616 { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA },
6617 { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6619 { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA },
6620 { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA },
6621 { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA },
6622 { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
6655 { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA },
6656 { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA },
6658 { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
6671 { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA },
6673 { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA },
6674 { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA },
6675 { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA },
6676 { "vpminud", { XM, Vex, EXx }, PREFIX_DATA },
6677 { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA },
6678 { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA },
6679 { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA },
6680 { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA },
6682 { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA },
6687 { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6689 { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6767 { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
6769 { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
6778 { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6779 { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6781 { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6783 { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6785 { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6787 { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6796 { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6797 { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6799 { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6801 { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6803 { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6805 { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6814 { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6815 { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6817 { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6819 { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6821 { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6823 { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6857 { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA },
6858 { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
6859 { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA },
6860 { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
6914 { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6915 { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6916 { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6917 { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6973 { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6975 { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6977 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6982 { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6983 { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
7004 { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7005 { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7006 { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7007 { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7018 { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7019 { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7022 { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7023 { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7036 { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7037 { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7040 { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7041 { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7201 { "%XEVmovlpYX", { XM, Vex, Mq }, 0 },
7216 { "%XEVmovhpYX", { XM, Vex, Mq }, 0 },
7334 { "%XEvpinsrwY", { XM, Vex, Edw, Ib }, PREFIX_DATA },
7435 { "vsha512rnds2", { XM, Vex, Rxmmq }, 0 },
7452 { "vsm3msg1", { XM, Vex, EXxmm }, 0 },
7457 { "vsm3msg2", { XM, Vex, EXxmm }, 0 },
7542 { "%XEvpinsrbY", { XM, Vex, Edb, Ib }, PREFIX_DATA },
7547 { "%XEvinsertpsY", { XM, Vex, EXd, Ib }, PREFIX_DATA },
7552 { "%XEvpinsrYK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
7589 { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7620 { "vsm3rnds2", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7710 { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 },
8024 { "%XEvpermilps", { XM, Vex, EXx }, PREFIX_DATA },
8028 { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
8044 { "vpermps", { XM, Vex, EXx }, PREFIX_DATA },
8060 { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA },
8064 Vex, Mx }, PREFIX_DATA },
8068 { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA },
8072 { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA },
8076 { "vpermd", { XM, Vex, EXx }, PREFIX_DATA },
8080 { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA },
8108 { "%XVvpdpwssd", { XM, Vex, EXx }, PREFIX_DATA },
8112 { "%XVvpdpwssds", { XM, Vex, EXx }, PREFIX_DATA },
8177 { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA },
8182 { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
8198 { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
8224 { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
8236 { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
8240 { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
8252 { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
8260 { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
8264 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
8268 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
8272 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
8277 { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
8282 { "%XEvgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
8310 { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
8314 { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
8318 { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 },
8322 { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 },
8326 { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
8330 { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 },
8334 { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 },
8338 { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 },
8342 { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 },
8346 { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
8350 { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
8354 { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 },
8374 { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 },
8378 { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 },
8382 { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 },
8386 { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 },
8390 { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
8394 { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
8398 { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
8402 { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
8532 { "%XEVmovlpYX", { XM, Vex, EXq }, 0 },
8533 { "%XEVmovhlpY%XS", { XM, Vex, EXq }, 0 },
8537 { "%XEVmovhpYX", { XM, Vex, EXq }, 0 },
8538 { "%XEVmovlhpY%XS", { XM, Vex, EXq }, 0 },
9089 /* The prefix in VEX is implicit. */
9090 switch (ins->vex.prefix)
9161 /* EVEX from VEX instructions are 64-bit only and require that EVEX.z,
9164 || (ins->vex.mask_register_specifier & 0x3) != 0
9165 || ins->vex.ll != 0
9166 || ins->vex.zeroing != 0
9167 || ins->vex.b)
9203 switch (ins->vex.length)
9210 128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid. */
9211 if (ins->vex.evex)
9227 if (!ins->vex.evex)
9230 switch (ins->vex.length)
9271 ins->vex.w = *ins->codep & 0x80;
9272 if (ins->vex.w && ins->address_mode == mode_64bit)
9275 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9282 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9288 ins->vex.prefix = DATA_PREFIX_OPCODE;
9291 ins->vex.prefix = REPE_PREFIX_OPCODE;
9294 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9308 if (ins->vex.prefix)
9313 /* VEX prefix. */
9339 ins->vex.w = *ins->codep & 0x80;
9342 if (ins->vex.w)
9347 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9349 VEX.vvvv is also ignored (but we mustn't clear it here). */
9352 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9353 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9359 ins->vex.prefix = DATA_PREFIX_OPCODE;
9362 ins->vex.prefix = REPE_PREFIX_OPCODE;
9365 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9397 /* VEX prefix. */
9402 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9403 VEX.vvvv is 1. */
9404 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9405 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9411 ins->vex.prefix = DATA_PREFIX_OPCODE;
9414 ins->vex.prefix = REPE_PREFIX_OPCODE;
9417 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9425 /* There is no MODRM byte for VEX 77. */
9435 dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w];
9441 ins->vex.evex = true;
9484 ins->vex.w = *ins->codep & 0x80;
9485 if (ins->vex.w && ins->address_mode == mode_64bit)
9488 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9498 ins->vex.prefix = DATA_PREFIX_OPCODE;
9501 ins->vex.prefix = REPE_PREFIX_OPCODE;
9504 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9512 ins->vex.ll = (*ins->codep >> 5) & 3;
9513 ins->vex.b = *ins->codep & 0x10;
9515 ins->vex.v = *ins->codep & 0x8;
9516 ins->vex.mask_register_specifier = *ins->codep & 0x7;
9517 ins->vex.scc = *ins->codep & 0xf;
9518 ins->vex.zeroing = *ins->codep & 0x80;
9521 ins->vex.nf = *ins->codep & 0x4;
9556 which has the same encoding as vex.length == 128 and they can share
9557 the same processing with vex.length in OP_VEX. */
9558 if (ins->modrm.mod == 3 && ins->vex.b && ins->evex_type != evex_from_legacy)
9559 ins->vex.length = 512;
9562 switch (ins->vex.ll)
9565 ins->vex.length = 128;
9568 ins->vex.length = 256;
9571 ins->vex.length = 512;
9965 && ins.vex.prefix == DATA_PREFIX_OPCODE)
9969 ins.vex.nf = false;
9975 ins.vex.mask_register_specifier &= 0x3;
9990 if (i == 0 && ins.vex.evex)
9993 if (ins.vex.mask_register_specifier)
9996 = att_names_mask[ins.vex.mask_register_specifier];
10002 if (ins.vex.zeroing)
10005 else if (ins.vex.zeroing)
10014 if (ins.vex.zeroing && dp->op[0].bytemode == mask_mode)
10021 && (ins.vex.mask_register_specifier == 0
10022 || ins.vex.zeroing))
10029 /* vex.nf is cleared after being consumed. */
10030 if (ins.vex.nf)
10035 if (ins.modrm.mod == 3 && ins.vex.b && ins.evex_type == evex_default
10043 oappend (&ins, names_rounding[ins.vex.ll]);
10098 if (!ins.vex.nd && (ins.vex.register_specifier || !ins.vex.v))
10107 if ((ins.vex.mask_register_specifier & 0x3) != 0
10108 || ins.vex.ll != 0 || ins.vex.zeroing != 0)
10115 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
10117 if (ins.need_vex && ins.vex.register_specifier != 0)
10137 if (ins.need_vex ? !ins.vex.prefix : !(ins.prefixes & PREFIX_DATA))
10152 ? ins.vex.prefix == REPE_PREFIX_OPCODE
10153 || ins.vex.prefix == REPNE_PREFIX_OPCODE
10159 ? ins.vex.prefix == DATA_PREFIX_OPCODE
10164 || (ins.vex.evex && dp->prefix_requirement != PREFIX_DATA
10165 && !ins.vex.w != !(ins.used_prefixes & PREFIX_DATA)))
10186 if (ins.vex.prefix == REPE_PREFIX_OPCODE
10187 || ins.vex.prefix == REPNE_PREFIX_OPCODE)
10196 if (ins.vex.prefix)
10833 if (ins->evex_type == evex_from_legacy && !ins->vex.nd
10869 if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd)
10896 if (!ins->vex.w)
10916 oappend (ins, scc_suffix[ins->vex.scc]);
10919 if (ins->vex.nd)
10924 ins->vex.v = 1;
10925 ins->vex.nf = false;
10926 ins->vex.mask_register_specifier = 0;
10949 if (!ins->vex.evex || ins->vex.w)
10990 if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2
10993 || !ins->vex.v || ins->vex.mask_register_specifier)
10998 if (ins->vex.w)
11051 if (ins->vex.nd && !ins->vex.nf)
11060 if (ins->vex.nf)
11064 ins->vex.nf = false;
11068 && ins->vex.v)
11077 int oszc_value = ~ins->vex.register_specifier & 0xf;
11083 ins->vex.register_specifier = 0;
11127 if (!ins->vex.w)
11244 if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd)
11260 *ins->obufp++ = ins->vex.w ? 'q' : 'd';
11333 if (!ins->vex.evex || !ins->vex.w)
11348 if (ins->vex.nd)
11365 if (ins->vex.evex)
11413 *ins->obufp++ = ins->vex.w ? 'd': 's';
11415 *ins->obufp++ = ins->vex.w ? 'w': 'b';
11426 ? ins->vex.prefix == DATA_PREFIX_OPCODE
11438 if (ins->vex.mask_register_specifier)
11446 || ((ins->modrm.mod == 3 || ins->vex.b)
11449 switch (ins->vex.length)
11458 if (!ins->vex.evex)
11476 if (!ins->vex.evex)
11479 || ((ins->modrm.mod == 3 || ins->vex.b)
11482 switch (ins->vex.length)
11685 if (ins->vex.b && ins->evex_type == evex_default)
11687 if (!ins->vex.no_broadcast)
11692 if (ins->vex.w)
11703 ins->vex.no_broadcast = true;
11805 switch (ins->vex.length)
11832 switch (ins->vex.length)
11852 switch (ins->vex.length)
11872 switch (ins->vex.length)
11891 switch (ins->vex.length)
11913 if (ins->vex.w)
11919 if (!ins->need_vex || ins->vex.length != 128)
11921 if (ins->vex.w)
11929 if (ins->vex.w)
11949 if (bytemode != mask_mode && ins->vex.mask_register_specifier)
12183 if (ins->vex.evex && ins->evex_type == evex_default)
12189 if (ins->vex.zeroing)
12215 shift = ins->vex.w ? 3 : 2;
12220 if (ins->vex.b)
12222 shift = ins->vex.w ? 2 : 1;
12228 if (ins->vex.b)
12230 shift = ins->vex.w ? 3 : 2;
12240 switch (ins->vex.length)
12258 || (bytemode == ymmq_mode && ins->vex.length == 128))
12277 shift = ins->vex.w ? 1 : 0;
12325 if (ins->vex.evex)
12334 if (!ins->vex.v)
12339 switch (ins->vex.length)
12345 if (!ins->vex.w
12352 if (!ins->vex.w
12408 if (ins->vex.evex && shift > 0)
12584 if (ins->vex.evex && shift > 0)
12618 if (ins->vex.b && ins->evex_type == evex_default)
12624 ins->vex.no_broadcast = true;
12626 if (!ins->vex.no_broadcast
12631 switch (ins->vex.length)
12648 ins->vex.no_broadcast = true;
12649 else if (ins->vex.w
12653 switch (ins->vex.length)
12671 switch (ins->vex.length)
12687 ins->vex.no_broadcast = true;
12689 if (ins->vex.no_broadcast)
12722 if (ins->vex.mask_register_specifier)
13301 switch (ins->vex.length)
13340 switch (ins->vex.length)
13346 if (ins->vex.w
13353 if (ins->vex.w
13376 if (ins->vex.evex)
13385 ins->vex.no_broadcast = true;
13474 bytemode = ins->vex.w ? q_mode : d_mode;
13483 if (ins->vex.evex)
13523 if (ins->vex.length <= 128)
13543 ins->vex.no_broadcast = true;
13965 switch (ins->vex.length)
13997 VEX. */
14011 if (!ins->vex.nd)
14015 reg = ins->vex.register_specifier;
14016 ins->vex.register_specifier = 0;
14019 if (ins->vex.evex && !ins->vex.v)
14027 else if (ins->vex.evex && !ins->vex.v)
14041 if (ins->vex.length == 128
14043 && !ins->vex.w))
14116 switch (ins->vex.length)
14185 if (ins->vex.w)
14213 if (bytemode == x_mode && ins->vex.length == 256)
14218 if (ins->vex.w)
14243 if (!ins->vex.evex)
14417 unsigned int reg = ins->vex.register_specifier;
14430 else if (ins->vex.evex && !ins->vex.v)
14457 if (ins->modrm.mod != 3 || !ins->vex.b)
14464 if (ins->address_mode != mode_64bit || !ins->vex.w)
14468 oappend (ins, names_rounding[ins->vex.ll]);
14515 unsigned int vvvv_reg = ins->vex.register_specifier
14516 | (!ins->vex.v << 4);
14521 if (!ins->vex.nd || vvvv_reg == 0x4 || rm_reg == 0x4
14569 bool dstmem = !ins->vex.nd && ins->vex.nf;
14579 ins->vex.nf = false;
14580 ins->vex.mask_register_specifier = 0;
Indexes created Sun Mar 01 05:31:48 UTC 2026