Cross Reference: /src/external/gpl3/gcc.old/dist/gcc/config/alpha/alpha.cc

Lines Matching defs:data_regs
3632   rtx ext_tmps[MAX_MOVE_WORDS], data_regs[MAX_MOVE_WORDS+1];
3643       data_regs[i] = out_regs[i];
3646   data_regs[words] = gen_reg_rtx (DImode);
3659       emit_move_insn (data_regs[i], tmp);
3668   emit_move_insn (data_regs[words], tmp);
3679       emit_insn (gen_extql (data_regs[i], data_regs[i], sreg));
3680       emit_insn (gen_extqh (ext_tmps[i], data_regs[i+1], sreg));
3691       out_regs[i] = expand_binop (DImode, ior_optab, data_regs[i],
3692 				  ext_tmps[i], data_regs[i], 1, OPTAB_WIDEN);
3696 /* Store an integral number of consecutive unaligned quadwords.  DATA_REGS
3700 alpha_expand_unaligned_store_words (rtx *data_regs, rtx dmem,
3714   if (data_regs != NULL)
3740   if (data_regs != NULL)
3744 	  emit_insn (gen_insqh (ins_tmps[i], data_regs[i], dreg));
3745 	  emit_insn (gen_insql (data_regs[i], data_regs[i], dreg));
3749 	  ins_tmps[i-1] = expand_binop (DImode, ior_optab, data_regs[i],
3759   if (data_regs != NULL)
3763       st_tmp_1 = expand_binop (DImode, ior_optab, st_tmp_1, data_regs[0],
3777       emit_move_insn (tmp, data_regs ? ins_tmps[i-1] : const0_rtx);
3801   rtx data_regs[2 * MAX_MOVE_WORDS + 16];
3860 	data_regs[nregs + i] = gen_reg_rtx (DImode);
3863 	emit_move_insn (data_regs[nregs + i],
3876 	data_regs[nregs + i] = gen_reg_rtx (SImode);
3879 	emit_move_insn (data_regs[nregs + i],
3892 	data_regs[nregs + i] = gen_reg_rtx (DImode);
3894       alpha_expand_unaligned_load_words (data_regs + nregs, orig_src,
3904       data_regs[nregs++] = tmp = gen_reg_rtx (SImode);
3915 	    data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
3923 	  data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
3932       data_regs[nregs++] = tmp = gen_reg_rtx (QImode);
3938   gcc_assert (nregs <= ARRAY_SIZE (data_regs));
3947       while (i < nregs && GET_MODE (data_regs[i]) == DImode)
3950 			  data_regs[i]);
3960       while (i < nregs && GET_MODE (data_regs[i]) == DImode)
3962 	  tmp = expand_binop (DImode, lshr_optab, data_regs[i], GEN_INT (32),
3966 			  gen_lowpart (SImode, data_regs[i]));
3973       while (i < nregs && GET_MODE (data_regs[i]) == SImode)
3976 			  data_regs[i]);
3982   if (i < nregs && GET_MODE (data_regs[i]) == DImode)
3987 	if (GET_MODE (data_regs[i + words]) != DImode)
3991 	alpha_expand_unaligned_store (orig_dst, data_regs[i], 8, ofs);
3993         alpha_expand_unaligned_store_words (data_regs + i, orig_dst,
4003   while (i < nregs && GET_MODE (data_regs[i]) == SImode)
4005       alpha_expand_unaligned_store (orig_dst, data_regs[i], 4, ofs);
4011     while (i < nregs && GET_MODE (data_regs[i]) == HImode)
4013 	emit_move_insn (adjust_address (orig_dst, HImode, ofs), data_regs[i]);
4018     while (i < nregs && GET_MODE (data_regs[i]) == HImode)
4020 	alpha_expand_unaligned_store (orig_dst, data_regs[i], 2, ofs);
4028       gcc_assert (GET_MODE (data_regs[i]) == QImode);
4029       emit_move_insn (adjust_address (orig_dst, QImode, ofs), data_regs[i]);
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