Lines Matching defs:sgpr
93 The SGPR count includes any special extra registers such as VCC. */
327 error ("too many arguments passed in sgpr registers");
705 /* Avoid returning classes that contain both vgpr and sgpr registers. */
1082 for instructions that require an SGPR.
1238 /* SGPR + CONST or VGPR + CONST */
1250 /* (SGPR + VGPR) + CONST */
1285 OFFSET is either 20bit unsigned immediate, SGPR or M0.
1286 Writes and atomics do not accept SGPR. */
1376 /* SGPR + CONST or VGPR + CONST */
1381 /* SGPR + VGPR */
1388 /* (SGPR + VGPR) + CONST */
1395 /* SGPR + CONST */
1410 OFFSET is either 20bit unsigned immediate, SGPR or M0.
1411 Writes and atomics do not accept SGPR. */
1799 MEM will be a DImode address of a vector in an SGPR.
1823 /* RF and RM base registers for vector modes should be always an SGPR. */
4926 /* VALU writes SGPR followed by VMEM reading the same SGPR
4954 /* VALU writes SGPR/VCC followed by v_{read,write}lane using
4955 SGPR/VCC as lane select requires 4 wait states. */
5300 int sgpr, vgpr;
5315 /* Determine count of sgpr/vgpr registers by looking for last
5317 for (sgpr = 101; sgpr >= 0; sgpr--)
5318 if (df_regs_ever_live_p (FIRST_SGPR_REG + sgpr))
5320 sgpr++;
5331 if (sgpr < MAX_NORMAL_SGPR_COUNT)
5332 sgpr = MAX_NORMAL_SGPR_COUNT;
5397 sgpr,
5430 sgpr, vgpr);
5700 /* (SGPR + VGPR) + CONST */
5709 /* SGPR + VGPR */
5712 /* VGPR + CONST or SGPR + CONST */
6085 /* (SGPR + VGPR) + CONST */
6092 /* SGPR + VGPR */
Indexes created Sun Mar 29 00:23:15 UTC 2026