Cross Reference: /src/external/gpl3/gcc.old/dist/gcc/config/i386/driver-i386.cc

Lines Matching refs:level2
45 describe_cache (struct cache_desc level1, struct cache_desc level2)
58 	    "--param l2-cache-size=%u ", level2.sizekb);
66 detect_l2_cache (struct cache_desc *level2)
73   level2->sizekb = (ecx >> 16) & 0xffff;
74   level2->line = ecx & 0xff;
86   level2->assoc = assoc;
96   struct cache_desc level1, level2 = {0, 0, 0};
108     detect_l2_cache (&level2);
110   return describe_cache (level1, level2);
120 		     struct cache_desc *level1, struct cache_desc *level2)
140 	level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
143 	level2->sizekb = 1024; level2->assoc = 16; level2->line = 64;
149 	level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
152 	level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
155 	level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
158 	level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
161 	level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
164 	level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
167 	level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
170 	level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
173 	level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
176 	level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
179 	level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
182 	level2->sizekb = 3072; level2->assoc = 12; level2->line = 64;
187 	level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
190 	level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
205 	level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
208 	level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
211 	level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
214 	level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
217 	level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
220 	level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
223 	level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
226 	level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
229 	level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
232 	level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
235 	level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
238 	level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
241 	level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
244 	level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
255 		      struct cache_desc *level1, struct cache_desc *level2)
269 	  decode_caches_intel (regs[i], xeon_mp, level1, level2);
288 detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2,
312 		cache = level2;
345   struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0};
348     detect_caches_cpuid4 (&level1, &level2, &level3);
350     detect_caches_cpuid2 (xeon_mp, &level1, &level2);
360     level2 = level3;
364   if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
365     detect_l2_cache (&level2);
367   *l2sizekb = level2.sizekb;
369   return describe_cache (level1, level2);
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