Lines Matching refs:cmp1
3540 /* Return true if CMP1 is a suitable second operand for integer ordering
3544 loongarch_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
3550 return reg_or_0_operand (cmp1, VOIDmode);
3554 return cmp1 == const1_rtx;
3558 return arith_operand (cmp1, VOIDmode);
3561 return sle_operand (cmp1, VOIDmode);
3564 return sleu_operand (cmp1, VOIDmode);
3571 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
3573 be formed by adjusting *CODE and *CMP1. When returning true, update
3574 *CODE and *CMP1 with the chosen code and operand, otherwise leave
3578 loongarch_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
3583 if (loongarch_int_order_operand_ok_p (*code, *cmp1))
3586 if (CONST_INT_P (*cmp1))
3590 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
3591 if (INTVAL (*cmp1) < plus_one)
3594 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3600 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
3604 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3615 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
3622 rtx target, rtx cmp0, rtx cmp1)
3628 fails, force CMP1 into a register and try again. */
3630 if (loongarch_canonicalize_int_order_test (&code, &cmp1, mode))
3631 loongarch_emit_binary (code, target, cmp0, cmp1);
3635 if (!loongarch_canonicalize_int_order_test (&inv_code, &cmp1, mode))
3637 cmp1 = force_reg (mode, cmp1);
3638 loongarch_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
3645 inv_code, cmp0, cmp1);
3651 loongarch_emit_binary (inv_code, target, cmp0, cmp1);
3656 /* Return a register that is zero if CMP0 and CMP1 are equal.
3660 loongarch_zero_if_equal (rtx cmp0, rtx cmp1)
3662 if (cmp1 == const0_rtx)
3665 if (uns_arith_operand (cmp1, VOIDmode))
3666 return expand_binop (GET_MODE (cmp0), xor_optab, cmp0, cmp1, 0, 0,
3669 return expand_binop (GET_MODE (cmp0), sub_optab, cmp0, cmp1, 0, 0,
Indexes created Mon Aug 17 00:26:26 UTC 2026