1 /* $NetBSD: atari_init.c,v 1.122 2026/09/21 03:43:49 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Leo Weppelman 5 * Copyright (c) 1994 Michael L. Hitch 6 * Copyright (c) 1993 Markus Wild 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Markus Wild. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: atari_init.c,v 1.122 2026/09/21 03:43:49 tsutsui Exp $"); 37 38 #include "opt_ddb.h" 39 #include "opt_mbtype.h" 40 #include "opt_m060sp.h" 41 #include "opt_m68k_arch.h" 42 #include "opt_st_pool_size.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/ioctl.h> 47 #include <sys/select.h> 48 #include <sys/tty.h> 49 #include <sys/buf.h> 50 #include <sys/msgbuf.h> 51 #include <sys/mbuf.h> 52 #include <sys/protosw.h> 53 #include <sys/domain.h> 54 #include <sys/reboot.h> 55 #include <sys/exec.h> 56 #include <sys/exec_aout.h> 57 #include <sys/core.h> 58 #include <sys/kcore.h> 59 #include <sys/bus.h> 60 61 #include <uvm/uvm_extern.h> 62 63 #include <machine/vmparam.h> 64 #include <machine/pte.h> 65 #include <machine/cpu.h> 66 #include <machine/iomap.h> 67 #include <machine/mfp.h> 68 #include <machine/scu.h> 69 #include <machine/acia.h> 70 #include <machine/kcore.h> 71 #include <machine/intr.h> 72 #include <machine/vectors.h> 73 74 #include <m68k/cpu.h> 75 #include <m68k/cacheops.h> 76 #include <m68k/pcr.h> 77 78 #include <atari/atari/stalloc.h> 79 #include <atari/dev/clockvar.h> 80 #include <atari/dev/ym2149reg.h> 81 82 #include "pci.h" 83 84 void *start_c(int, u_int, u_int, u_int, char *); 85 static void atari_hwinit(void); 86 static void cpu_init_kcorehdr(paddr_t, paddr_t); 87 static void initcpu(void); 88 static void mmu030_setup(paddr_t, u_int, paddr_t, psize_t, paddr_t, paddr_t); 89 static void map_io_areas(paddr_t, psize_t, u_int); 90 static void set_machtype(void); 91 92 #if defined(M68040) || defined(M68060) 93 static void mmu040_setup(paddr_t, u_int, paddr_t, psize_t, paddr_t, paddr_t); 94 #endif 95 96 #if defined(_MILANHW_) 97 static u_int milan_probe_bank_1(paddr_t paddr); 98 static u_int milan_probe_bank(paddr_t paddr); 99 100 #define NBANK 2 101 #define NSLOT 4 102 103 #define MB(n) ((n) * 1024 * 1024) 104 #define MB_END(n) (MB(n) - 1) 105 #define MAGIC_4M (4 - 1) 106 #define MAGIC_4M_INV ((uint8_t)~MAGIC_4M) 107 #define MAGIC_8M (8 - 1) 108 #define MAGIC_16M (16 - 1) 109 #define MAGIC_32M (32 - 1) 110 #define MAGIC_64M (64 - 1) 111 #endif 112 113 /* 114 * All info needed to generate a panic dump. All fields are setup by 115 * start_c(). 116 * XXX: Should sheck usage of phys_segs. There is some unwanted overlap 117 * here.... Also, the name is badly chosen. Phys_segs contains the 118 * segment descriptions _after_ reservations are made. 119 * XXX: 'lowram' is obsoleted by the new panicdump format 120 */ 121 static cpu_kcore_hdr_t cpu_kcore_hdr; 122 123 extern u_int lowram; 124 int machineid, mmutype, cputype; 125 126 extern char *esym; 127 extern struct pcb *curpcb; 128 129 /* 130 * This is the virtual address of physical page 0. Used by 'do_boot()'. 131 */ 132 vaddr_t page_zero; 133 134 /* 135 * Simple support for allocation in ST-ram. 136 * Currently 16 bit ST-ram is required to allocate DMA buffers for SCSI and 137 * FDC transfers, and video memory for the XFree68 based Xservers. 138 * The physical address is also returned because the video init needs it to 139 * setup the controller at the time the vm-system is not yet operational so 140 * 'kvtop()' cannot be used. 141 */ 142 #define ST_POOL_SIZE_MIN 24 /* for DMA bounce buffers */ 143 #ifndef ST_POOL_SIZE 144 #define ST_POOL_SIZE 56 /* Xserver requires 320KB (40 pages) */ 145 #endif 146 147 psize_t st_pool_size = ST_POOL_SIZE * PAGE_SIZE; /* Patchable */ 148 vaddr_t st_pool_virt; 149 paddr_t st_pool_phys; 150 151 /* 152 * Thresholds to restrict size of reserved ST memory to make sure 153 * the kernel at least boot even on lower memory machines. 154 * Nowadays we could assume most users have 4MB ST-RAM and 16MB TT-RAM. 155 */ 156 #define STRAM_MINTHRESH (2 * 1024 * 1024) 157 #define TTRAM_MINTHRESH (4 * 1024 * 1024) 158 159 /* I/O address space variables */ 160 vaddr_t stio_addr; /* Where the st io-area is mapped */ 161 vaddr_t pci_conf_addr; /* KVA base of PCI config space */ 162 vaddr_t pci_io_addr; /* KVA base of PCI io-space */ 163 vaddr_t pci_mem_addr; /* KVA base of PCI mem-space */ 164 vaddr_t pci_mem_uncached; /* KVA base of an uncached PCI mem-page */ 165 166 /* 167 * Are we relocating the kernel to TT-Ram if possible? It is faster, but 168 * it is also reported not to work on all TT's. So the default is NO. 169 */ 170 #ifndef RELOC_KERNEL 171 #define RELOC_KERNEL 0 172 #endif 173 int reloc_kernel = RELOC_KERNEL; /* Patchable */ 174 175 #define RELOC_PA(base, pa) ((base) + (pa)) /* used to set up PTE etc. */ 176 177 /* 178 * this is the C-level entry function, it's called from locore.s. 179 * Preconditions: 180 * Interrupts are disabled 181 * PA == VA, we don't have to relocate addresses before enabling 182 * the MMU 183 * Exec is no longer available (because we're loaded all over 184 * low memory, no ExecBase is available anymore) 185 * 186 * It's purpose is: 187 * Do the things that are done in locore.s in the hp300 version, 188 * this includes allocation of kernel maps and enabling the MMU. 189 * 190 * Some of the code in here is `stolen' from Amiga MACH, and was 191 * written by Bryan Ford and Niklas Hallqvist. 192 * 193 * Very crude 68040 support by Michael L. Hitch. 194 */ 195 int kernel_copyback = 1; 196 197 void * 198 start_c(int id, u_int ttphystart, u_int ttphysize, u_int stphysize, 199 char *esym_addr) 200 /* id: Machine id */ 201 /* ttphystart, ttphysize: Start address and size of TT-ram */ 202 /* stphysize: Size of ST-ram */ 203 /* esym_addr: Address of kernel '_esym' symbol */ 204 { 205 extern char end[]; 206 extern void etext(void); 207 paddr_t pstart; /* Next available physical address */ 208 vaddr_t vstart; /* Next available virtual address */ 209 vsize_t avail; 210 paddr_t ptpa; 211 psize_t ptsize; 212 u_int ptextra; 213 vaddr_t kva; 214 u_int i; 215 pt_entry_t *pg, *epg; 216 pt_entry_t pg_proto; 217 vaddr_t end_loaded; 218 paddr_t kbase; 219 u_int kstsize; 220 paddr_t Sysptmap_pa; 221 #if defined(_MILANHW_) 222 /* 223 * The Milan Lies about the presence of TT-RAM. If you insert 224 * 16MB it is split in 14MB ST starting at address 0 and 2MB TT RAM, 225 * starting at address 16MB as the BIOS remapping memory using MMU. 226 * 227 * Milan actually has four SIMM slots and each slot has two banks, 228 * so it could have up to 8 memory segment regions. 229 */ 230 const paddr_t simm_base[NBANK][NSLOT] = { 231 /* slot 0-3, bank 0 */ 232 { 0x00000000, 0x04000000, 0x08000000, 0x0c000000 }, 233 /* slot 0-3, bank 1 */ 234 { 0x10000000, 0x14000000, 0x18000000, 0x1c000000 } 235 }; 236 int slot, bank, seg; 237 u_int mb; 238 239 /* On Milan, all RAMs are fast 32 bit so no need to reloc kernel */ 240 reloc_kernel = 0; 241 242 /* probe memory region in all SIMM slots and banks */ 243 seg = 0; 244 ttphysize = 0; 245 for (bank = 0; bank < 2; bank++) { 246 for (slot = 0; slot < 4; slot++) { 247 if (bank == 0 && slot == 0) { 248 /* 249 * The first bank has at least 16MB because 250 * the Milan's ROM bootloader requires it 251 * to allocate ST RAM. 252 */ 253 mb = milan_probe_bank_1(simm_base[bank][slot]); 254 boot_segs[0].start = 0; 255 boot_segs[0].end = MB(mb); 256 stphysize = MB(mb); 257 seg++; 258 } else { 259 /* 260 * The rest banks could be empty or 261 * have 4, 8, 16, 32, or 64MB. 262 */ 263 mb = milan_probe_bank(simm_base[bank][slot]); 264 if (mb > 0) { 265 boot_segs[seg].start = 266 simm_base[bank][slot]; 267 boot_segs[seg].end = 268 simm_base[bank][slot] + MB(mb); 269 ttphysize += MB(mb); 270 seg++; 271 } 272 } 273 } 274 } 275 #else /* _MILANHW_ */ 276 boot_segs[0].start = 0; 277 boot_segs[0].end = stphysize; 278 boot_segs[1].start = ttphystart; 279 boot_segs[1].end = ttphystart + ttphysize; 280 boot_segs[2].start = boot_segs[2].end = 0; /* End of segments! */ 281 #endif 282 283 /* 284 * We do not know how much ST memory we really need until after 285 * configuration has finished, but typical users of ST memory 286 * are bounce buffers DMA against TT-RAM for SCSI and FDC, 287 * and video memory for the Xserver. 288 * If we have enough RAMs reserve ST memory including for the Xserver. 289 * Otherwise just allocate minimum one for SCSI and FDC. 290 * 291 * The round_page() call is meant to correct errors made by 292 * binpatching! 293 */ 294 if (st_pool_size > ST_POOL_SIZE_MIN * PAGE_SIZE && 295 (stphysize <= STRAM_MINTHRESH || ttphysize <= TTRAM_MINTHRESH)) { 296 st_pool_size = ST_POOL_SIZE_MIN * PAGE_SIZE; 297 } 298 st_pool_size = m68k_round_page(st_pool_size); 299 st_pool_phys = stphysize - st_pool_size; 300 stphysize = st_pool_phys; 301 302 physmem = btoc(stphysize) + btoc(ttphysize); 303 machineid = id; 304 esym = esym_addr; 305 306 /* 307 * the kernel ends at end() or esym. 308 */ 309 if (esym == NULL) 310 end_loaded = (vaddr_t)&end; 311 else 312 end_loaded = (vaddr_t)esym; 313 314 /* 315 * If we have enough fast-memory to put the kernel in and the 316 * RELOC_KERNEL option is set, do it! 317 */ 318 if ((reloc_kernel != 0) && (ttphysize >= end_loaded)) 319 kbase = ttphystart; 320 else 321 kbase = 0; 322 323 /* 324 * Determine the type of machine we are running on. This needs 325 * to be done early (and before initcpu())! 326 */ 327 set_machtype(); 328 329 /* 330 * Initialize CPU specific stuff 331 */ 332 initcpu(); 333 334 /* 335 * We run the kernel from ST memory at the moment. 336 * The kernel segment table is put just behind the loaded image. 337 * pstart: start of usable ST memory 338 * avail : size of ST memory available. 339 */ 340 vstart = (vaddr_t)end_loaded; 341 vstart = m68k_round_page(vstart); 342 pstart = (paddr_t)vstart; /* pre-reloc PA == kernel VA here */ 343 avail = stphysize - pstart; 344 345 /* 346 * Save KVA of lwp0 uarea and allocate it. 347 */ 348 lwp0uarea = vstart; 349 pstart += USPACE; 350 vstart += USPACE; 351 avail -= USPACE; 352 353 /* 354 * Calculate the number of pages needed for Sysseg. 355 * For the 68030, we need 256 descriptors (segment-table-entries). 356 * This easily fits into one page. 357 * For the 68040, both the level-1 and level-2 descriptors are 358 * stored into Sysseg. We currently handle a maximum sum of MAXKL2SIZE 359 * level-1 & level-2 tables. 360 */ 361 #if defined(M68040) || defined(M68060) 362 if (mmutype == MMU_68040) 363 kstsize = MAXKL2SIZE / (NPTEPG/SG4_LEV2SIZE); 364 else 365 #endif 366 kstsize = 1; 367 /* 368 * allocate the kernel segment table 369 */ 370 Sysseg_pa = pstart; /* pre-reloc PA to init STEs */ 371 Sysseg = (st_entry_t *)vstart; 372 pstart += kstsize * PAGE_SIZE; 373 vstart += kstsize * PAGE_SIZE; 374 avail -= kstsize * PAGE_SIZE; 375 376 /* 377 * allocate kernel page table map 378 */ 379 Sysptmap_pa = pstart; /* pre-reloc PA to init PTEs */ 380 Sysptmap = (pt_entry_t *)vstart; 381 pstart += PAGE_SIZE; 382 vstart += PAGE_SIZE; 383 avail -= PAGE_SIZE; 384 385 /* 386 * Determine the number of pte's we need for extra's like 387 * ST I/O map's. 388 */ 389 ptextra = btoc(STIO_SIZE); 390 391 /* 392 * If present, add pci areas 393 */ 394 if (machineid & ATARI_HADES) 395 ptextra += btoc(PCI_CONFIG_SIZE + PCI_IO_SIZE + PCI_MEM_SIZE); 396 if (machineid & ATARI_MILAN) 397 ptextra += btoc(PCI_IO_SIZE + PCI_MEM_SIZE); 398 ptextra += btoc(BOOTM_VA_POOL); 399 /* 400 * now need to account for the kmem area, which is allocated 401 * before pmap_init() is called. It is roughly the size of physical 402 * memory. 403 */ 404 ptextra += physmem; 405 406 /* 407 * The 'pt' (the initial kernel pagetable) has to map the kernel and 408 * the I/O areas. The various I/O areas are mapped (virtually) at 409 * the top of the address space mapped by 'pt' (ie. just below Sysmap). 410 */ 411 ptpa = pstart; /* pre-reloc PA to init PTEs */ 412 ptsize = (Sysptsize + howmany(ptextra, NPTEPG)) << PGSHIFT; 413 pstart += ptsize; 414 vstart += ptsize; 415 avail -= ptsize; 416 417 /* 418 * Sysmap is now placed at the end of Supervisor virtual address space. 419 */ 420 Sysmap = (pt_entry_t *)SYSMAP_VA; 421 422 /* 423 * Initialize segment tables 424 */ 425 #if defined(M68040) || defined(M68060) 426 if (mmutype == MMU_68040) 427 mmu040_setup(Sysseg_pa, kstsize, ptpa, ptsize, Sysptmap_pa, 428 kbase); 429 else 430 #endif /* defined(M68040) || defined(M68060) */ 431 mmu030_setup(Sysseg_pa, kstsize, ptpa, ptsize, Sysptmap_pa, 432 kbase); 433 434 /* 435 * initialize kernel page table page(s). 436 * Assume load at VA 0. 437 * - Text pages are RO 438 * - Page zero is invalid 439 */ 440 pg_proto = RELOC_PA(kbase, 0) | PG_RO | PG_V; 441 pg = (pt_entry_t *)ptpa; 442 *pg++ = PG_NV; 443 444 pg_proto += PAGE_SIZE; 445 for (kva = PAGE_SIZE; kva < (vaddr_t)etext; kva += PAGE_SIZE) { 446 *pg++ = pg_proto; 447 pg_proto += PAGE_SIZE; 448 } 449 450 /* 451 * data, bss and dynamic tables are read/write 452 */ 453 pg_proto = (pg_proto & PG_FRAME) | PG_RW | PG_V; 454 455 #if defined(M68040) || defined(M68060) 456 /* 457 * Map the kernel segment table cache invalidated for 68040/68060. 458 * (for the 68040 not strictly necessary, but recommended by Motorola; 459 * for the 68060 mandatory) 460 */ 461 if (mmutype == MMU_68040) { 462 463 if (kernel_copyback) 464 pg_proto |= PG_CCB; 465 466 for (; kva < (vaddr_t)Sysseg; kva += PAGE_SIZE) { 467 *pg++ = pg_proto; 468 pg_proto += PAGE_SIZE; 469 } 470 471 pg_proto = (pg_proto & ~PG_CCB) | PG_CI; 472 for (; kva < (vaddr_t)Sysptmap; kva += PAGE_SIZE) { 473 *pg++ = pg_proto; 474 pg_proto += PAGE_SIZE; 475 } 476 477 pg_proto = (pg_proto & ~PG_CI); 478 if (kernel_copyback) 479 pg_proto |= PG_CCB; 480 } 481 #endif /* defined(M68040) || defined(M68060) */ 482 483 /* 484 * go till end of data allocated so far 485 * plus lwp0 u-area (to be allocated) 486 */ 487 for (; kva < vstart; kva += PAGE_SIZE) { 488 *pg++ = pg_proto; 489 pg_proto += PAGE_SIZE; 490 } 491 492 /* 493 * invalidate remainder of kernel PT 494 */ 495 epg = (pt_entry_t *)ptpa; 496 epg = &epg[ptsize / sizeof(pt_entry_t)]; 497 while (pg < epg) 498 *pg++ = PG_NV; 499 500 /* 501 * Map various I/O areas 502 */ 503 map_io_areas(ptpa, ptsize, ptextra); 504 505 /* 506 * Map the allocated space in ST-ram now. In the contig-case, there 507 * is no need to make a distinction between virtual and physical 508 * addresses. But I make it anyway to be prepared. 509 * Physical space is already reserved! 510 */ 511 st_pool_virt = vstart; 512 pg = (pt_entry_t *)ptpa; 513 pg = &pg[vstart / PAGE_SIZE]; 514 pg_proto = st_pool_phys | PG_RW | PG_CI | PG_V; 515 vstart += st_pool_size; 516 while (pg_proto < (st_pool_phys + st_pool_size)) { 517 *pg++ = pg_proto; 518 pg_proto += PAGE_SIZE; 519 } 520 521 /* 522 * Map physical page_zero and page-zero+1 (First ST-ram page). We need 523 * to reference it in the reboot code. Two pages are mapped, because 524 * we must make sure 'doboot()' is contained in it (see the tricky 525 * copying there....). 526 */ 527 page_zero = vstart; 528 pg = (pt_entry_t *)ptpa; 529 pg = &pg[vstart / PAGE_SIZE]; 530 *pg++ = PG_RW | PG_CI | PG_V; 531 vstart += PAGE_SIZE; 532 *pg = PG_RW | PG_CI | PG_V | PAGE_SIZE; 533 vstart += PAGE_SIZE; 534 535 /* 536 * All necessary STEs and PTEs have been initialized. 537 * Update Sysseg_pa and Sysptmap_pa to point relocated PA. 538 */ 539 if (kbase) { 540 Sysseg_pa += kbase; 541 Sysptmap_pa += kbase; 542 } 543 544 lowram = 0 >> PGSHIFT; /* XXX */ 545 546 /* 547 * Fill in usable segments. The page indexes will be initialized 548 * later when all reservations are made. 549 */ 550 usable_segs[0].start = 0; 551 usable_segs[0].end = stphysize; 552 usable_segs[0].free_list = VM_FREELIST_STRAM; 553 #if defined(_MILANHW_) 554 for (i = 1; i < seg; i++) { 555 usable_segs[i].start = boot_segs[i].start; 556 usable_segs[i].end = boot_segs[i].end; 557 usable_segs[i].free_list = VM_FREELIST_TTRAM; 558 } 559 for (; i < NMEM_SEGS; i++) { 560 usable_segs[i].start = usable_segs[i].end = 0; 561 } 562 #else 563 usable_segs[1].start = ttphystart; 564 usable_segs[1].end = ttphystart + ttphysize; 565 usable_segs[1].free_list = VM_FREELIST_TTRAM; 566 usable_segs[2].start = usable_segs[2].end = 0; /* End of segments! */ 567 #endif 568 569 if (kbase) { 570 /* 571 * First page of ST-ram is unusable, reserve the space 572 * for the kernel in the TT-ram segment. 573 * Note: Because physical page-zero is partially mapped to ROM 574 * by hardware, it is unusable. 575 */ 576 usable_segs[0].start = PAGE_SIZE; 577 usable_segs[1].start += pstart; 578 } else 579 usable_segs[0].start += pstart; 580 581 /* 582 * As all segment sizes are now valid, calculate page indexes and 583 * available physical memory. 584 */ 585 usable_segs[0].first_page = 0; 586 for (i = 1; i < NMEM_SEGS && usable_segs[i].start; i++) { 587 usable_segs[i].first_page = usable_segs[i-1].first_page; 588 usable_segs[i].first_page += 589 (usable_segs[i-1].end - usable_segs[i-1].start) / PAGE_SIZE; 590 } 591 for (i = 0, physmem = 0; usable_segs[i].start; i++) 592 physmem += usable_segs[i].end - usable_segs[i].start; 593 physmem >>= PGSHIFT; 594 595 /* 596 * get the pmap module in sync with reality. 597 */ 598 pmap_bootstrap(vstart); 599 600 #if defined(M68030) 601 /* 602 * Prepare the SRP prototype before relocating the kernel. 603 * The relocated copy must contain the root table address 604 * when the MMU is enabled. 605 */ 606 protorp[1] = Sysseg_pa; 607 #endif 608 609 cpu_init_kcorehdr(kbase, Sysseg_pa); 610 611 /* 612 * copy over the kernel (and all now initialized variables) 613 * to fastram. DONT use bcopy(), this beast is much larger 614 * than 128k ! 615 */ 616 if (kbase) { 617 register paddr_t *lp, *le, *fp; 618 619 lp = (paddr_t *)0; 620 le = (paddr_t *)pstart; 621 fp = (paddr_t *)kbase; 622 while (lp < le) 623 *fp++ = *lp++; 624 } 625 #if defined(M68040) || defined(M68060) 626 if (mmutype == MMU_68040) { 627 /* 628 * movel Sysseg_pa,a0; 629 * movec a0,SRP; 630 * pflusha; 631 * movel #$0xc000,d0; 632 * movec d0,TC 633 */ 634 if (cputype == CPU_68060) { 635 /* XXX: Need the branch cache be cleared? */ 636 __asm volatile (".word 0x4e7a,0x0002;" 637 "orl #0x400000,%%d0;" 638 ".word 0x4e7b,0x0002" : : : "d0"); 639 } 640 __asm volatile ("movel %0,%%a0;" 641 ".word 0x4e7b,0x8807" : : "a" (Sysseg_pa) : "a0"); 642 __asm volatile (".word 0xf518" : : ); 643 __asm volatile ("movel #0xc000,%%d0;" 644 ".word 0x4e7b,0x0003" : : : "d0" ); 645 } else 646 #endif 647 { 648 #if defined(M68030) 649 __asm volatile ("pmove %0@,%%srp" 650 : 651 : "a" (&protorp[0]), "m" (protorp[0]), "m" (protorp[1])); 652 /* 653 * setup and load TC register. 654 * enable_cpr, enable_srp, pagesize=8k, 655 * A = 8 bits, B = 11 bits 656 */ 657 u_int tc = MMU51_TCR_BITS; 658 __asm volatile ("pflusha" : : ); 659 __asm volatile ("pmove %0@,%%tc" : : "a" (&tc), "m" (tc)); 660 #endif /* M68030 */ 661 } 662 663 /* 664 * Initialize the "u-area" pages etc. 665 */ 666 void *ksp = pmap_bootstrap2(); 667 668 /* 669 * Get the hardware into a defined state 670 */ 671 atari_hwinit(); 672 673 /* 674 * Initialize stmem allocator 675 */ 676 init_stmem(); 677 678 /* 679 * Initialize the iomem arena for bus_space(9) to manage address 680 * spaces and allocate the physical RAM from the extent map. 681 */ 682 atari_bus_space_arena_init(0x0, 0xffffffff); 683 for (i = 0; i < NMEM_SEGS && boot_segs[i].end != 0; i++) { 684 if (atari_bus_space_alloc_physmem(boot_segs[i].start, 685 boot_segs[i].end)) { 686 /* XXX: Ahum, should not happen ;-) */ 687 printf("Warning: Cannot allocate boot memory from" 688 " extent map!?\n"); 689 } 690 } 691 692 /* 693 * Initialize interrupt mapping. 694 */ 695 intr_init(); 696 697 return ksp; 698 } 699 700 #if defined(_MILANHW_) 701 /* 702 * Probe and return available memory size in MB at specified address. 703 * The first slot SIMM have at least 16MB, so check if it has 32 or 64 MB. 704 * 705 * Note it seems Milan does not generate bus errors on accesses against 706 * address regions where memory doesn't exist, but it returns memory images 707 * of lower address of the bank. 708 */ 709 static u_int 710 milan_probe_bank_1(paddr_t start_paddr) 711 { 712 volatile uint8_t *base; 713 u_int mb; 714 uint8_t save_16, save_32, save_64; 715 716 /* Assume that this bank has at least 16MB */ 717 mb = 16; 718 719 base = (uint8_t *)start_paddr; 720 721 /* save and write a MAGIC at the end of 16MB region */ 722 save_16 = base[MB_END(16)]; 723 base[MB_END(16)] = MAGIC_16M; 724 725 /* check bus error at the end of 32MB region */ 726 if (badbaddr(base + MB_END(32))) { 727 /* bus error; assume no memory there */ 728 goto out16; 729 } 730 731 /* check if the 32MB region is not image of the prior 16MB region */ 732 save_32 = base[MB_END(32)]; 733 base[MB_END(32)] = MAGIC_32M; 734 if (base[MB_END(32)] != MAGIC_32M || base[MB_END(16)] != MAGIC_16M) { 735 /* no memory or image at the 32MB region */ 736 goto out16; 737 } 738 /* we have at least 32MB */ 739 mb = 32; 740 741 /* check bus error at the end of 64MB region */ 742 if (badbaddr(base + MB_END(64))) { 743 /* bus error; assume no memory there */ 744 goto out32; 745 } 746 747 /* check if the 64MB region is not image of the prior 32MB region */ 748 save_64 = base[MB_END(64)]; 749 base[MB_END(64)] = MAGIC_64M; 750 if (base[MB_END(64)] != MAGIC_64M || base[MB_END(32)] != MAGIC_32M) { 751 /* no memory or image at the 64MB region */ 752 goto out32; 753 } 754 /* we have 64MB */ 755 mb = 64; 756 base[MB_END(64)] = save_64; 757 out32: 758 base[MB_END(32)] = save_32; 759 out16: 760 base[MB_END(16)] = save_16; 761 762 return mb; 763 } 764 765 /* 766 * Probe and return available memory size in MB at specified address. 767 * The rest slot could be empty so check all possible size. 768 */ 769 static u_int 770 milan_probe_bank(paddr_t start_paddr) 771 { 772 volatile uint8_t *base; 773 u_int mb; 774 uint8_t save_4, save_8, save_16; 775 776 /* The rest banks might have no memory */ 777 mb = 0; 778 779 base = (uint8_t *)start_paddr; 780 781 /* check bus error at the end of 4MB region */ 782 if (badbaddr(base + MB_END(4))) { 783 /* bus error; assume no memory there */ 784 goto out; 785 } 786 787 /* check if the 4MB region has memory */ 788 save_4 = base[MB_END(4)]; 789 base[MB_END(4)] = MAGIC_4M_INV; 790 if (base[MB_END(4)] != MAGIC_4M_INV) { 791 /* no memory */ 792 goto out; 793 } 794 base[MB_END(4)] = MAGIC_4M; 795 if (base[MB_END(4)] != MAGIC_4M) { 796 /* no memory */ 797 goto out; 798 } 799 /* we have at least 4MB */ 800 mb = 4; 801 802 /* check bus error at the end of 8MB region */ 803 if (badbaddr(base + MB_END(8))) { 804 /* bus error; assume no memory there */ 805 goto out4; 806 } 807 808 /* check if the 8MB region is not image of the prior 4MB region */ 809 save_8 = base[MB_END(8)]; 810 base[MB_END(8)] = MAGIC_8M; 811 if (base[MB_END(8)] != MAGIC_8M || base[MB_END(4)] != MAGIC_4M) { 812 /* no memory or image at the 8MB region */ 813 goto out4; 814 } 815 /* we have at least 8MB */ 816 mb = 8; 817 818 /* check bus error at the end of 16MB region */ 819 if (badbaddr(base + MB_END(16))) { 820 /* bus error; assume no memory there */ 821 goto out8; 822 } 823 824 /* check if the 16MB region is not image of the prior 8MB region */ 825 save_16 = base[MB_END(16)]; 826 base[MB_END(16)] = MAGIC_16M; 827 if (base[MB_END(16)] != MAGIC_16M || base[MB_END(8)] != MAGIC_8M) { 828 /* no memory or image at the 32MB region */ 829 goto out8; 830 } 831 /* we have at least 16MB, so check more region as the first bank */ 832 mb = milan_probe_bank_1(start_paddr); 833 834 base[MB_END(16)] = save_16; 835 out8: 836 base[MB_END(8)] = save_8; 837 out4: 838 base[MB_END(4)] = save_4; 839 out: 840 841 return mb; 842 } 843 #endif /* _MILANHW_ */ 844 845 /* 846 * Try to figure out on what type of machine we are running 847 * Note: This module runs *before* the io-mapping is setup! 848 */ 849 static void 850 set_machtype(void) 851 { 852 853 #ifdef _MILANHW_ 854 machineid |= ATARI_MILAN; 855 856 #else 857 stio_addr = 0xff8000; /* XXX: For TT & Falcon only */ 858 if (badbaddr(&MFP2->mf_gpip)) { 859 /* 860 * Watch out! We can also have a Hades with < 16Mb 861 * RAM here... 862 */ 863 if (!badbaddr(&MFP->mf_gpip)) { 864 machineid |= ATARI_FALCON; 865 return; 866 } 867 } 868 if (!badbaddr((void *)(PCI_CONFB_PHYS + PCI_CONFM_PHYS))) 869 machineid |= ATARI_HADES; 870 else 871 machineid |= ATARI_TT; 872 #endif /* _MILANHW_ */ 873 } 874 875 static void 876 atari_hwinit(void) 877 { 878 879 #if defined(_ATARIHW_) 880 /* 881 * Initialize the sound chip 882 */ 883 ym2149_init(); 884 885 /* 886 * Make sure that the midi acia will not generate an interrupt 887 * unless something attaches to it. We cannot do this for the 888 * keyboard acia because this breaks the '-d' option of the 889 * booter... 890 */ 891 MDI->ac_cs = 0; 892 #endif /* defined(_ATARIHW_) */ 893 894 /* 895 * Initialize both MFP chips (if both present!) to generate 896 * auto-vectored interrupts with EOI. The active-edge registers are 897 * set up. The interrupt enable registers are set to disable all 898 * interrupts. 899 */ 900 MFP->mf_iera = MFP->mf_ierb = 0; 901 MFP->mf_imra = MFP->mf_imrb = 0; 902 MFP->mf_aer = MFP->mf_ddr = 0; 903 MFP->mf_vr = 0x40; 904 905 #if defined(_ATARIHW_) 906 if (machineid & (ATARI_TT|ATARI_HADES)) { 907 MFP2->mf_iera = MFP2->mf_ierb = 0; 908 MFP2->mf_imra = MFP2->mf_imrb = 0; 909 MFP2->mf_aer = 0x80; 910 MFP2->mf_vr = 0x50; 911 } 912 913 if (machineid & ATARI_TT) { 914 /* 915 * Initialize the SCU, to enable interrupts on the SCC (ipl5), 916 * MFP (ipl6) and softints (ipl1). 917 */ 918 SCU->sys_mask = SCU_SYS_SOFT; 919 SCU->vme_mask = SCU_MFP | SCU_SCC; 920 #ifdef DDB 921 /* 922 * This allows people with the correct hardware modification 923 * to drop into the debugger from an NMI. 924 */ 925 SCU->sys_mask |= SCU_IRQ7; 926 #endif 927 } 928 #endif /* defined(_ATARIHW_) */ 929 930 /* 931 * Initialize a timer for delay(9). 932 */ 933 init_delay(); 934 935 #if NPCI > 0 936 if (machineid & (ATARI_HADES|ATARI_MILAN)) { 937 /* 938 * Configure PCI-bus 939 */ 940 init_pci_bus(); 941 } 942 #endif 943 944 } 945 946 /* 947 * Do the dull work of mapping the various I/O areas. They MUST be Cache 948 * inhibited! 949 * All I/O areas are virtually mapped at the end of the pt-table. 950 */ 951 static void 952 map_io_areas(paddr_t ptpa, psize_t ptsize, u_int ptextra) 953 /* ptsize: Size of 'pt' in bytes */ 954 /* ptextra: #of additional I/O pte's */ 955 { 956 vaddr_t ioaddr; 957 pt_entry_t *pt, *pg, *epg; 958 pt_entry_t pg_proto; 959 u_long mask; 960 961 pt = (pt_entry_t *)ptpa; 962 ioaddr = ((ptsize / sizeof(pt_entry_t)) - ptextra) * PAGE_SIZE; 963 964 /* 965 * Map ST-IO area 966 */ 967 stio_addr = ioaddr; 968 ioaddr += STIO_SIZE; 969 pg = &pt[stio_addr / PAGE_SIZE]; 970 epg = &pg[btoc(STIO_SIZE)]; 971 #ifdef _MILANHW_ 972 /* 973 * Turn on byte swaps in the ST I/O area. On the Milan, the 974 * U0 signal of the MMU controls the BigEndian signal 975 * of the PLX9080. We use this setting so we can read/write the 976 * PLX registers (and PCI-config space) in big-endian mode. 977 */ 978 pg_proto = STIO_PHYS | PG_RW | PG_CI | PG_V | 0x100; 979 #else 980 pg_proto = STIO_PHYS | PG_RW | PG_CI | PG_V; 981 #endif 982 while (pg < epg) { 983 *pg++ = pg_proto; 984 pg_proto += PAGE_SIZE; 985 } 986 987 /* 988 * Map PCI areas 989 */ 990 if (machineid & ATARI_HADES) { 991 /* 992 * Only Hades maps the PCI-config space! 993 */ 994 pci_conf_addr = ioaddr; 995 ioaddr += PCI_CONFIG_SIZE; 996 pg = &pt[pci_conf_addr / PAGE_SIZE]; 997 epg = &pg[btoc(PCI_CONFIG_SIZE)]; 998 mask = PCI_CONFM_PHYS; 999 pg_proto = PCI_CONFB_PHYS | PG_RW | PG_CI | PG_V; 1000 for (; pg < epg; mask <<= 1) 1001 *pg++ = pg_proto | mask; 1002 } else 1003 pci_conf_addr = 0; /* XXX: should crash */ 1004 1005 if (machineid & (ATARI_HADES|ATARI_MILAN)) { 1006 pci_io_addr = ioaddr; 1007 ioaddr += PCI_IO_SIZE; 1008 pg = &pt[pci_io_addr / PAGE_SIZE]; 1009 epg = &pg[btoc(PCI_IO_SIZE)]; 1010 pg_proto = PCI_IO_PHYS | PG_RW | PG_CI | PG_V; 1011 while (pg < epg) { 1012 *pg++ = pg_proto; 1013 pg_proto += PAGE_SIZE; 1014 } 1015 1016 pci_mem_addr = ioaddr; 1017 /* Provide an uncached PCI address for the MILAN */ 1018 pci_mem_uncached = ioaddr; 1019 ioaddr += PCI_MEM_SIZE; 1020 epg = &pg[btoc(PCI_MEM_SIZE)]; 1021 pg_proto = PCI_VGA_PHYS | PG_RW | PG_CI | PG_V; 1022 while (pg < epg) { 1023 *pg++ = pg_proto; 1024 pg_proto += PAGE_SIZE; 1025 } 1026 } 1027 1028 bootm_init(ioaddr, pg, BOOTM_VA_POOL); 1029 /* 1030 * ioaddr += BOOTM_VA_POOL; 1031 * pg = &pg[btoc(BOOTM_VA_POOL)]; 1032 */ 1033 } 1034 1035 /* 1036 * Used by dumpconf() to get the size of the machine-dependent panic-dump 1037 * header in disk blocks. 1038 */ 1039 1040 #define CHDRSIZE (ALIGN(sizeof(kcore_seg_t)) + ALIGN(sizeof(cpu_kcore_hdr_t))) 1041 #define MDHDRSIZE roundup(CHDRSIZE, dbtob(1)) 1042 1043 int 1044 cpu_dumpsize(void) 1045 { 1046 1047 return btodb(MDHDRSIZE); 1048 } 1049 1050 /* 1051 * Called by dumpsys() to dump the machine-dependent header. 1052 * XXX: Assumes that it will all fit in one diskblock. 1053 */ 1054 int 1055 cpu_dump(int (*dump)(dev_t, daddr_t, void *, size_t), daddr_t *p_blkno) 1056 { 1057 int buf[MDHDRSIZE/sizeof(int)]; 1058 int error; 1059 kcore_seg_t *kseg_p; 1060 cpu_kcore_hdr_t *chdr_p; 1061 1062 kseg_p = (kcore_seg_t *)buf; 1063 chdr_p = (cpu_kcore_hdr_t *)&buf[ALIGN(sizeof(*kseg_p)) / sizeof(int)]; 1064 1065 /* 1066 * Generate a segment header 1067 */ 1068 CORE_SETMAGIC(*kseg_p, KCORE_MAGIC, MID_MACHINE, CORE_CPU); 1069 kseg_p->c_size = MDHDRSIZE - ALIGN(sizeof(*kseg_p)); 1070 1071 /* 1072 * Add the md header 1073 */ 1074 *chdr_p = cpu_kcore_hdr; 1075 error = dump(dumpdev, *p_blkno, (void *)buf, sizeof(buf)); 1076 *p_blkno += btodb(sizeof(buf)); 1077 return (error); 1078 } 1079 1080 #if (M68K_NPHYS_RAM_SEGS < NMEM_SEGS) 1081 #error "Configuration error: M68K_NPHYS_RAM_SEGS < NMEM_SEGS" 1082 #endif 1083 /* 1084 * Initialize the cpu_kcore_header. 1085 */ 1086 static void 1087 cpu_init_kcorehdr(paddr_t kbase, paddr_t sysseg_pa) 1088 { 1089 cpu_kcore_hdr_t *h = &cpu_kcore_hdr; 1090 struct m68k_kcore_hdr *m = &h->un._m68k; 1091 extern char end[]; 1092 int i; 1093 1094 memset(&cpu_kcore_hdr, 0, sizeof(cpu_kcore_hdr)); 1095 1096 /* 1097 * Initialize the `dispatcher' portion of the header. 1098 */ 1099 strcpy(h->name, machine); 1100 h->page_size = PAGE_SIZE; 1101 h->kernbase = KERNBASE; 1102 1103 /* 1104 * Fill in information about our MMU configuration. 1105 */ 1106 m->mmutype = mmutype; 1107 m->sg_v = SG_V; 1108 m->sg_frame = SG_FRAME; 1109 m->sg_ishift = SG_ISHIFT; 1110 m->sg_pmask = SG_PMASK; 1111 m->sg40_shift1 = SG4_SHIFT1; 1112 m->sg40_mask2 = SG4_MASK2; 1113 m->sg40_shift2 = SG4_SHIFT2; 1114 m->sg40_mask3 = SG4_MASK3; 1115 m->sg40_shift3 = SG4_SHIFT3; 1116 m->sg40_addr1 = SG4_ADDR1; 1117 m->sg40_addr2 = SG4_ADDR2; 1118 m->pg_v = PG_V; 1119 m->pg_frame = PG_FRAME; 1120 1121 /* 1122 * Initialize pointer to kernel segment table. 1123 */ 1124 m->sysseg_pa = sysseg_pa; /* PA after relocation */ 1125 1126 /* 1127 * Initialize relocation value such that: 1128 * 1129 * pa = (va - KERNBASE) + reloc 1130 */ 1131 m->reloc = kbase; 1132 1133 /* 1134 * Define the end of the relocatable range. 1135 */ 1136 m->relocend = (vaddr_t)end; 1137 1138 for (i = 0; i < NMEM_SEGS; i++) { 1139 m->ram_segs[i].start = boot_segs[i].start; 1140 m->ram_segs[i].size = boot_segs[i].end - 1141 boot_segs[i].start; 1142 } 1143 } 1144 1145 void 1146 mmu030_setup(paddr_t sysseg_pa, u_int kstsize, paddr_t ptpa, psize_t ptsize, 1147 paddr_t sysptmap_pa, paddr_t kbase) 1148 /* sysseg_pa: System segment table */ 1149 /* kstsize: size of 'sysseg' in pages */ 1150 /* ptpa: Kernel page table */ 1151 /* ptsize: size of 'pt' in bytes */ 1152 /* sysptmap_pa: System page table */ 1153 { 1154 st_entry_t sg_proto, *sg, *esg; 1155 pt_entry_t pg_proto, *pg, *epg; 1156 1157 /* 1158 * Map the page table pages in both the HW segment table 1159 * and the software Sysptmap. 1160 */ 1161 sg = (st_entry_t *)sysseg_pa; 1162 pg = (pt_entry_t *)sysptmap_pa; 1163 epg = &pg[ptsize >> PGSHIFT]; 1164 sg_proto = RELOC_PA(kbase, ptpa) | SG_RW | SG_V; 1165 pg_proto = RELOC_PA(kbase, ptpa) | PG_RW | PG_CI | PG_V; 1166 while (pg < epg) { 1167 *sg++ = sg_proto; 1168 *pg++ = pg_proto; 1169 sg_proto += PAGE_SIZE; 1170 pg_proto += PAGE_SIZE; 1171 } 1172 1173 /* 1174 * Invalidate the remainder of the tables. 1175 */ 1176 esg = (st_entry_t *)sysseg_pa; 1177 esg = &esg[TIA_SIZE]; 1178 while (sg < esg) 1179 *sg++ = SG_NV; 1180 epg = (pt_entry_t *)sysptmap_pa; 1181 epg = &epg[TIB_SIZE]; 1182 while (pg < epg) 1183 *pg++ = PG_NV; 1184 1185 /* 1186 * Initialize the PTE for the last one to point Sysptmap. 1187 */ 1188 sg = (st_entry_t *)sysseg_pa; 1189 sg = &sg[SYSMAP_VA >> SEGSHIFT]; 1190 pg = (pt_entry_t *)sysptmap_pa; 1191 pg = &pg[SYSMAP_VA >> SEGSHIFT]; 1192 *sg = RELOC_PA(kbase, sysptmap_pa) | SG_RW | SG_V; 1193 *pg = RELOC_PA(kbase, sysptmap_pa) | PG_RW | PG_CI | PG_V; 1194 } 1195 1196 #if defined(M68040) || defined(M68060) 1197 void 1198 mmu040_setup(paddr_t sysseg_pa, u_int kstsize, paddr_t ptpa, psize_t ptsize, 1199 paddr_t sysptmap_pa, paddr_t kbase) 1200 /* sysseg_pa: System segment table */ 1201 /* kstsize: size of 'sysseg' in pages */ 1202 /* ptpa: Kernel page table */ 1203 /* ptsize: size of 'pt' in bytes */ 1204 /* sysptmap_pa: System page table */ 1205 { 1206 int nl1desc, nl2desc, i; 1207 st_entry_t sg_proto, *sg, *esg; 1208 pt_entry_t pg_proto, *pg, *epg; 1209 1210 /* 1211 * First invalidate the entire "segment table" pages 1212 * (levels 1 and 2 have the same "invalid" values). 1213 */ 1214 sg = (st_entry_t *)sysseg_pa; 1215 esg = &sg[kstsize * NPTEPG]; 1216 while (sg < esg) 1217 *sg++ = SG_NV; 1218 1219 /* 1220 * Initialize level 2 descriptors (which immediately 1221 * follow the level 1 table). 1222 * We need: 1223 * NPTEPG / SG4_LEV3SIZE 1224 * level 2 descriptors to map each of the nptpages 1225 * pages of PTEs. Note that we set the "used" bit 1226 * now to save the HW the expense of doing it. 1227 */ 1228 nl2desc = (ptsize >> PGSHIFT) * (NPTEPG / SG4_LEV3SIZE); 1229 sg = (st_entry_t *)sysseg_pa; 1230 sg = &sg[SG4_LEV1SIZE]; 1231 esg = &sg[nl2desc]; 1232 sg_proto = RELOC_PA(kbase, ptpa) | SG_U | SG_RW | SG_V; 1233 while (sg < esg) { 1234 *sg++ = sg_proto; 1235 sg_proto += (SG4_LEV3SIZE * sizeof(st_entry_t)); 1236 } 1237 1238 /* 1239 * Initialize level 1 descriptors. We need: 1240 * howmany(nl2desc, SG4_LEV2SIZE) 1241 * level 1 descriptors to map the 'nl2desc' level 2's. 1242 */ 1243 nl1desc = howmany(nl2desc, SG4_LEV2SIZE); 1244 sg = (st_entry_t *)sysseg_pa; 1245 esg = &sg[nl1desc]; 1246 sg_proto = RELOC_PA(kbase, (paddr_t)&sg[SG4_LEV1SIZE]) 1247 | SG_U | SG_RW | SG_V; 1248 while (sg < esg) { 1249 *sg++ = sg_proto; 1250 sg_proto += (SG4_LEV2SIZE * sizeof(st_entry_t)); 1251 } 1252 1253 /* Sysmap is last entry in level 1 */ 1254 sg = (st_entry_t *)sysseg_pa; 1255 sg = &sg[SG4_LEV1SIZE - 1]; 1256 *sg = sg_proto; 1257 1258 /* 1259 * Kernel segment table at end of next level 2 table 1260 */ 1261 i = SG4_LEV1SIZE + (nl1desc * SG4_LEV2SIZE); 1262 sg = (st_entry_t *)sysseg_pa; 1263 sg = &sg[i + SG4_LEV2SIZE - (NPTEPG / SG4_LEV3SIZE)]; 1264 esg = &sg[NPTEPG / SG4_LEV3SIZE]; 1265 sg_proto = RELOC_PA(kbase, sysptmap_pa) | SG_U | SG_RW | SG_V; 1266 while (sg < esg) { 1267 *sg++ = sg_proto; 1268 sg_proto += (SG4_LEV3SIZE * sizeof(st_entry_t)); 1269 } 1270 1271 /* Include additional level 2 table for Sysmap in protostfree */ 1272 protostfree = (~0 << (1 + nl1desc + 1)) /* & ~(~0 << MAXKL2SIZE) */; 1273 1274 /* 1275 * Initialize Sysptmap 1276 */ 1277 pg = (pt_entry_t *)sysptmap_pa; 1278 epg = &pg[ptsize >> PGSHIFT]; 1279 pg_proto = RELOC_PA(kbase, ptpa) | PG_RW | PG_CI | PG_V; 1280 while (pg < epg) { 1281 *pg++ = pg_proto; 1282 pg_proto += PAGE_SIZE; 1283 } 1284 1285 /* 1286 * Invalidate rest of Sysptmap page. 1287 */ 1288 epg = (pt_entry_t *)sysptmap_pa; 1289 epg = &epg[TIB_SIZE]; 1290 while (pg < epg) 1291 *pg++ = PG_NV; 1292 1293 /* 1294 * Initialize the PTE for the last one to point Sysptmap. 1295 */ 1296 pg = (pt_entry_t *)sysptmap_pa; 1297 pg = &pg[SYSMAP_VA >> SEGSHIFT]; 1298 *pg = RELOC_PA(kbase, sysptmap_pa) | PG_RW | PG_CI | PG_V; 1299 } 1300 #endif /* M68040 */ 1301 1302 #if defined(M68060) 1303 int m68060_pcr_init = PCR_ESS; /* make this patchable */ 1304 #endif 1305 1306 static void 1307 initcpu(void) 1308 { 1309 #if defined(M68060) 1310 if (cputype == CPU_68060) { 1311 __asm volatile ("movl %0,%%d0; .word 0x4e7b,0x0808" : : 1312 "d"(m68060_pcr_init):"d0" ); 1313 } 1314 #endif 1315 /* Initialize the vector table. */ 1316 vec_init(); 1317 } 1318 1319 #ifdef DEBUG 1320 void dump_segtable(u_int *); 1321 void dump_pagetable(u_int *, u_int, u_int); 1322 u_int vmtophys(u_int *, u_int); 1323 1324 void 1325 dump_segtable(u_int *stp) 1326 { 1327 u_int *s, *es; 1328 int shift, i; 1329 1330 s = stp; 1331 { 1332 es = s + (M68K_STSIZE >> 2); 1333 shift = SG_ISHIFT; 1334 } 1335 1336 /* 1337 * XXX need changes for 68040 1338 */ 1339 for (i = 0; s < es; s++, i++) 1340 if (*s & SG_V) 1341 printf("$%08x: $%08x\t", i << shift, *s & SG_FRAME); 1342 printf("\n"); 1343 } 1344 1345 void 1346 dump_pagetable(u_int *ptp, u_int i, u_int n) 1347 { 1348 u_int *p, *ep; 1349 1350 p = ptp + i; 1351 ep = p + n; 1352 for (; p < ep; p++, i++) 1353 if (*p & PG_V) 1354 printf("$%08x -> $%08x\t", i, *p & PG_FRAME); 1355 printf("\n"); 1356 } 1357 1358 u_int 1359 vmtophys(u_int *ste, u_int vm) 1360 { 1361 1362 ste = (u_int *)(*(ste + (vm >> SEGSHIFT)) & SG_FRAME); 1363 ste += (vm & SG_PMASK) >> PGSHIFT; 1364 return (*ste & -PAGE_SIZE) | (vm & (PAGE_SIZE - 1)); 1365 } 1366 1367 #endif 1368
Indexes created Sun Oct 25 00:26:45 UTC 2026