Lines Matching defs:trueop0
2560 rtx trueop0, trueop1;
2575 trueop0 = avoid_constant_pool_reference (op0);
2578 tem = simplify_const_binary_operation (code, mode, trueop0, trueop1);
2581 tem = simplify_binary_operation_1 (code, mode, op0, op1, trueop0, trueop1);
2588 if (trueop0 != op0 || trueop1 != op1)
2589 return simplify_gen_binary (code, mode, trueop0, trueop1);
2686 OP1 are constant pool references, TRUEOP0 and TRUEOP1 represent the
2693 rtx trueop0, rtx trueop1)
2934 if (rtx_equal_p (trueop0, trueop1)
2943 if (!HONOR_SIGNED_ZEROS (mode) && trueop0 == CONST0_RTX (mode))
2949 if (trueop0 == constm1_rtx
3097 && trueop0 == const1_rtx
3269 if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0))
3445 if (rtx_equal_p (trueop0, trueop1)
3695 HOST_WIDE_INT nzop0 = nonzero_bits (trueop0, mode);
3711 if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0)
3903 if (trueop0 == CONST0_RTX (mode)
3907 return simplify_gen_binary (AND, mode, op1, trueop0);
3908 return trueop0;
3932 if (trueop0 == CONST0_RTX (mode)
3967 if (trueop0 == CONST0_RTX (mode)
3971 return simplify_gen_binary (AND, mode, op1, trueop0);
3972 return trueop0;
3993 if (trueop0 == CONST0_RTX (mode))
3996 return simplify_gen_binary (AND, mode, op1, trueop0);
3997 return trueop0;
4016 if (trueop0 == CONST0_RTX (mode))
4019 return simplify_gen_binary (AND, mode, op1, trueop0);
4020 return trueop0;
4055 if (trueop0 == CONST0_RTX (mode) && ! side_effects_p (op1))
4058 if (CONST_INT_P (trueop0)
4060 && UINTVAL (trueop0) == GET_MODE_MASK (mode)
4120 if (CONST_INT_P (trueop0)
4122 && (UINTVAL (trueop0) == (GET_MODE_MASK (mode) >> 1)
4123 || mode_signbit_p (mode, trueop0))
4129 if (CONST_INT_P (trueop0)
4131 && UINTVAL (trueop0) == GET_MODE_MASK (mode)
4140 if (trueop0 == CONST0_RTX (mode) && ! side_effects_p (op1))
4159 if (trueop0 == CONST0_RTX (mode) && ! side_effects_p (op1))
4183 if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0))
4196 if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0))
4206 if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0))
4216 if (rtx_equal_p (trueop0, trueop1) && ! side_effects_p (op0))
4270 gcc_assert (VECTOR_MODE_P (GET_MODE (trueop0)));
4271 gcc_assert (mode == GET_MODE_INNER (GET_MODE (trueop0)));
4279 if (vec_duplicate_p (trueop0, &elt0))
4282 if (GET_CODE (trueop0) == CONST_VECTOR)
4283 return CONST_VECTOR_ELT (trueop0, INTVAL (XVECEXP
4293 if (GET_CODE (trueop0) == VEC_SELECT
4294 && (GET_MODE_NUNITS (GET_MODE (XEXP (trueop0, 0)))
4297 rtx op0 = XEXP (trueop0, 0);
4298 rtx op1 = XEXP (trueop0, 1);
4355 gcc_assert (VECTOR_MODE_P (GET_MODE (trueop0)));
4357 == GET_MODE_INNER (GET_MODE (trueop0)));
4360 if (vec_duplicate_p (trueop0, &elt0))
4365 if (GET_CODE (trueop0) == CONST_VECTOR)
4379 RTVEC_ELT (v, i) = CONST_VECTOR_ELT (trueop0,
4387 if (GET_MODE (trueop0) == mode)
4400 return trueop0;
4404 if (vec_series_lowpart_p (mode, GET_MODE (trueop0), trueop1))
4406 rtx new_rtx = lowpart_subreg (mode, trueop0,
4407 GET_MODE (trueop0));
4416 && GET_CODE (trueop0) == VEC_CONCAT
4417 && GET_CODE (XEXP (trueop0, 0)) == VEC_CONCAT
4418 && GET_MODE (XEXP (trueop0, 0)) == mode
4419 && GET_CODE (XEXP (trueop0, 1)) == VEC_CONCAT
4420 && GET_MODE (XEXP (trueop0, 1)) == mode)
4427 subop0 = XEXP (XEXP (trueop0, i0 / 2), i0 % 2);
4428 subop1 = XEXP (XEXP (trueop0, i1 / 2), i1 % 2);
4436 && GET_CODE (trueop0) == VEC_CONCAT
4437 && GET_MODE (trueop0) == mode)
4444 subop0 = XEXP (trueop0, i0);
4445 subop1 = XEXP (trueop0, i1);
4452 if (GET_CODE (trueop0) == VEC_CONCAT
4453 && (GET_MODE_NUNITS (GET_MODE (XEXP (trueop0, 0)))
4455 && (GET_MODE_NUNITS (GET_MODE (XEXP (trueop0, 1)))
4459 rtx subop0 = XEXP (trueop0, 0);
4460 rtx subop1 = XEXP (trueop0, 1);
4499 if (GET_CODE (trueop0) == SUBREG
4501 == GET_MODE_INNER (GET_MODE (SUBREG_REG (trueop0)))
4503 && constant_multiple_p (subreg_memory_offset (trueop0),
4508 = GET_MODE_NUNITS (GET_MODE (SUBREG_REG (trueop0)));
4533 return gen_rtx_VEC_SELECT (mode, SUBREG_REG (trueop0), par);
4540 && GET_CODE (trueop0) == VEC_CONCAT)
4542 rtx vec = trueop0;
4558 vec_size = GET_MODE_SIZE (GET_MODE (trueop0))
4607 if (GET_CODE (trueop0) == VEC_SELECT
4608 && GET_MODE (XEXP (trueop0, 0)) == mode)
4610 rtx op0_subop1 = XEXP (trueop0, 1);
4627 return XEXP (trueop0, 0);
4633 machine_mode op0_mode = (GET_MODE (trueop0) != VOIDmode
4634 ? GET_MODE (trueop0)
4658 if ((GET_CODE (trueop0) == CONST_VECTOR
4659 || CONST_SCALAR_INT_P (trueop0)
4660 || CONST_DOUBLE_AS_FLOAT_P (trueop0))
4674 RTVEC_ELT (v, i) = trueop0;
4676 RTVEC_ELT (v, i) = CONST_VECTOR_ELT (trueop0, i);
4694 if (GET_CODE (trueop0) == VEC_SELECT
4696 && rtx_equal_p (XEXP (trueop0, 0), XEXP (trueop1, 0))
4697 && GET_MODE_INNER (GET_MODE (XEXP (trueop0, 0)))
4700 rtx par0 = XEXP (trueop0, 1);
4709 return simplify_gen_binary (VEC_SELECT, mode, XEXP (trueop0, 0),
5653 rtx tem, trueop0, trueop1;
5677 trueop0 = avoid_constant_pool_reference (op0);
5680 trueop0, trueop1);
6018 rtx trueop0;
6051 trueop0 = avoid_constant_pool_reference (op0);
6066 && ! ((REG_P (op0) || CONST_INT_P (trueop0))
6084 if ((! HONOR_NANS (trueop0)
6087 && ! HONOR_SNANS (trueop0)))
6088 && rtx_equal_p (trueop0, trueop1)
6089 && ! side_effects_p (trueop0))
6094 if (CONST_DOUBLE_AS_FLOAT_P (trueop0)
6096 && SCALAR_FLOAT_MODE_P (GET_MODE (trueop0)))
6098 const REAL_VALUE_TYPE *d0 = CONST_DOUBLE_REAL_VALUE (trueop0);
6132 && CONST_SCALAR_INT_P (trueop0) && CONST_SCALAR_INT_P (trueop1))
6138 rtx_mode_t ptrueop0 = rtx_mode_t (trueop0, cmode);
6156 && !side_effects_p (trueop0))
6159 unsigned HOST_WIDE_INT nonzero = nonzero_bits (trueop0, int_mode);
6187 = num_sign_bit_copies (trueop0, int_mode);
6272 && !side_effects_p (trueop0))
6276 if (nonzero_address_p (trueop0))
6323 if (trueop1 == CONST0_RTX (mode) && !side_effects_p (trueop0)
6324 && (GET_CODE (trueop0) == ABS
6325 || (GET_CODE (trueop0) == FLOAT_EXTEND
6326 && GET_CODE (XEXP (trueop0, 0)) == ABS)))
6686 rtx trueop0 = avoid_constant_pool_reference (op0);
6688 if (GET_CODE (trueop0) == CONST_VECTOR
6696 ? CONST_VECTOR_ELT (trueop0, i)
Indexes created Sat Mar 21 00:23:06 UTC 2026