Cross Reference: /src/external/gpl3/gcc.old/dist/libgcc/config/libbid/bid

Lines Matching refs:Ql
231 #define __imul_64x128_full(Ph, Ql, A, B)          \
238 	(Ql).w[0] = ALBL.w[0];                          \
242 	(Ql).w[1] = QM2.w[0];                          \
358 #define __mul_128x128_full(Qh, Ql, A, B)          \
368 	(Ql).w[0] = ALBL.w[0];                          \
371 	(Ql).w[1] = QM2.w[0];                          \
373 #define __mul_128x128_low(Ql, A, B)               \
381 	(Ql).w[0] = ALBL.w[0];                          \
382 	(Ql).w[1] = QM64 + ALBL.w[1];                 \
384 #define __mul_64x128_low(Ql, A, B)                \
389   (Ql).w[0] = ALBL.w[0];                          \
391   (Ql).w[1] = QM2.w[0];                           \
393 #define __mul_64x128_full(Ph, Ql, A, B)           \
400 	(Ql).w[0] = ALBL.w[0];                          \
402 	(Ql).w[1] = QM2.w[0];                          \
640 #define __mul_64x128_short(Ql, A, B)              \
645 	__mul_64x64_to_128((Ql), (A), (B).w[0]);       \
647 	(Ql).w[1] += ALBH_L;                          \
699 #define __mul_64x128_to_128(Ql, A, B)           \
704   (Ql).w[0] = ALBL.w[0];                          \
706   (Ql
1483   UINT128 T128, TP128, Qh, Ql, Qh1, Stemp, Tmp, Tmp1, CQ2, CQ8;
1533   __mul_128x128_full (Qh, Ql, CQ, TP128);
1554 	  && (Ql.w[1] < reciprocals10_128[ed2].w[1]
1555 	      || (Ql.w[1] == reciprocals10_128[ed2].w[1]
1556 		  && Ql.w[0] < reciprocals10_128[ed2].w[0]))) {
1576 	  && (Ql.w[1] < reciprocals10_128[ed2].w[1]
1577 	      || (Ql.w[1] == reciprocals10_128[ed2].w[1]
1578 		  && Ql.w[0] < reciprocals10_128[ed2].w[0])))
1584 	  && (Ql.w[1] < reciprocals10_128[ed2].w[1]
1585 	      || (Ql.w[1] == reciprocals10_128[ed2].w[1]
1586 		  && Ql.w[0] < reciprocals10_128[ed2].w[0])))
1591       __add_carry_out (Stemp.w[0], CY, Ql.w[0],
1593       __add_carry_in_out (Stemp.w[1], carry, Ql.w[1],
1626   UINT128 T128, TP128, Qh, Ql, Qh1, Stemp, Tmp, Tmp1;
1667   __mul_128x128_full (Qh, Ql, CQ, TP128);
1688 	  && (Ql.w[1] < reciprocals10_128[ed2].w[1]
1689 	      || (Ql.w[1] == reciprocals10_128[ed2].w[1]
1690 		  && Ql.w[0] < reciprocals10_128[ed2].w[0]))) {
1710 	  && (Ql.w[1] < reciprocals10_128[ed2].w[1]
1711 	      || (Ql.w[1] == reciprocals10_128[ed2].w[1]
1712 		  && Ql.w[0] < reciprocals10_128[ed2].w[0])))
1718 	  && (Ql.w[1] < reciprocals10_128[ed2].w[1]
1719 	      || (Ql.w[1] == reciprocals10_128[ed2].w[1]
1720 		  && Ql.w[0] < reciprocals10_128[ed2].w[0])))
1725       __add_carry_out (Stemp.w[0], CY, Ql.w[0],
1727       __add_carry_in_out (Stemp.w[1], carry, Ql.w[1],
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