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Lines Matching defs:reg_vd

12794       uint32_t reg_count, reg_vd;
12798       reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
12801       /* REG_VD is the first D register number.  If the instruction
12803 	 number is (REG_VD << 1 | bit D), so the corresponding D
12804 	 register number is (REG_VD << 1 | bit D) / 2 = REG_VD.  */
12806 	reg_vd = reg_vd | (bit_d << 4);
12825 	  record_buf[reg_index++] = ARM_D0_REGNUM + reg_vd + reg_count - 1;
12864       uint32_t reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
12868 	  reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4);
12869 	  record_buf[0] = ARM_D0_REGNUM + reg_vd;
12873 	  reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22);
12875 	  record_buf[0] = ARM_D0_REGNUM + reg_vd / 2;
12890   uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd;
12895   reg_vd = bits (arm_insn_r->arm_insn, 12, 15);
13065 	reg_vd = reg_vd | (bit_d << 4);
13066 	record_buf[0] = reg_vd + ARM_D0_REGNUM;
13067 	record_buf[1] = reg_vd + ARM_D0_REGNUM + 1;
13072 	reg_vd = reg_vd | (bit_d << 4);
13073 	record_buf[0] = reg_vd + ARM_D0_REGNUM;
13078 	reg_vd = (reg_vd << 1) | bit_d;
13079 	record_buf[0] = reg_vd + ARM_D0_REGNUM;
14255   uint32_t reg_rn, reg_vd, address, f_elem;
14263   reg_vd = bits (thumb2_insn_r->arm_insn, 12, 15);
14264   reg_vd = (bit (thumb2_insn_r->arm_insn, 22) << 4) | reg_vd;
14418 	    record_buf[index_r] = reg_vd + ARM_D0_REGNUM + index_r;