Lines Matching refs:dsc
716 arm_displaced_step_copy_insn_closure *dsc = nullptr;
720 dsc = ((arm_displaced_step_copy_insn_closure * )
726 if (dsc)
729 (unsigned long) dsc->insn_addr,
731 memaddr = dsc->insn_addr;
5494 displaced_read_reg (regcache *regs, arm_displaced_step_copy_insn_closure *dsc,
5498 CORE_ADDR from = dsc->insn_addr;
5508 if (!dsc->is_thumb)
5542 branch_write_pc (regcache *regs, arm_displaced_step_copy_insn_closure *dsc,
5545 if (!dsc->is_thumb)
5588 load_write_pc (regcache *regs, arm_displaced_step_copy_insn_closure *dsc,
5594 branch_write_pc (regs, dsc, val);
5600 alu_write_pc (regcache *regs, arm_displaced_step_copy_insn_closure *dsc,
5603 if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb)
5606 branch_write_pc (regs, dsc, val);
5614 displaced_write_reg (regcache *regs, arm_displaced_step_copy_insn_closure *dsc,
5624 branch_write_pc (regs, dsc, val);
5632 load_write_pc (regs, dsc, val);
5636 alu_write_pc (regs, dsc, val);
5648 dsc->wrote_to_pc = 1;
5695 arm_displaced_step_copy_insn_closure *dsc)
5700 dsc->modinsn[0] = insn;
5708 arm_displaced_step_copy_insn_closure *dsc)
5713 dsc->modinsn[0] = insn1;
5714 dsc->modinsn[1] = insn2;
5715 dsc->numinsns = 2;
5725 arm_displaced_step_copy_insn_closure *dsc)
5730 dsc->modinsn[0] = insn;
5739 arm_displaced_step_copy_insn_closure *dsc)
5741 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5742 if (!dsc->u.preload.immed)
5743 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
5748 arm_displaced_step_copy_insn_closure *dsc, unsigned int rn)
5757 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5758 rn_val = displaced_read_reg (regs, dsc, rn);
5759 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5760 dsc->u.preload.immed = 1;
5762 dsc->cleanup = &cleanup_preload;
5767 arm_displaced_step_copy_insn_closure *dsc)
5772 return arm_copy_unmodified (gdbarch, insn, "preload", dsc);
5776 dsc->modinsn[0] = insn & 0xfff0ffff;
5778 install_preload (gdbarch, regs, dsc, rn);
5785 regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
5793 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "preload", dsc);
5798 (unsigned int) dsc->insn_addr, u_bit ? '+' : '-',
5811 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5812 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5814 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
5816 displaced_write_reg (regs, dsc, 0, pc_val, CANNOT_WRITE_PC);
5817 displaced_write_reg (regs, dsc, 1, imm12, CANNOT_WRITE_PC);
5818 dsc->u.preload.immed = 0;
5821 dsc->modinsn[0] = insn1 & 0xfff0;
5822 dsc->modinsn[1] = 0xf001;
5823 dsc->numinsns = 2;
5825 dsc->cleanup = &cleanup_preload;
5833 arm_displaced_step_copy_insn_closure *dsc, unsigned int rn,
5844 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5845 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
5846 rn_val = displaced_read_reg (regs, dsc, rn);
5847 rm_val = displaced_read_reg (regs, dsc, rm);
5848 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5849 displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC);
5850 dsc->u.preload.immed = 0;
5852 dsc->cleanup = &cleanup_preload;
5858 arm_displaced_step_copy_insn_closure *dsc)
5865 return arm_copy_unmodified (gdbarch, insn, "preload reg", dsc);
5870 dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1;
5872 install_preload_reg (gdbarch, regs, dsc, rn, rm);
5881 arm_displaced_step_copy_insn_closure *dsc)
5883 ULONGEST rn_val = displaced_read_reg (regs, dsc, 0);
5885 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
5887 if (dsc->u.ldst.writeback)
5888 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC);
5893 arm_displaced_step_copy_insn_closure *dsc,
5906 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
5907 rn_val = displaced_read_reg (regs, dsc, rn);
5910 displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
5912 dsc->u.ldst.writeback = writeback;
5913 dsc->u.ldst.rn = rn;
5915 dsc->cleanup = &cleanup_copro_load_store;
5921 arm_displaced_step_copy_insn_closure *dsc)
5926 return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc);
5931 dsc->modinsn[0] = insn & 0xfff0ffff;
5933 install_copro_load_store (gdbarch, regs, dsc, bit (insn, 25), rn);
5941 arm_displaced_step_copy_insn_closure *dsc)
5947 "copro load/store", dsc);
5952 dsc->modinsn[0] = insn1 & 0xfff0;
5953 dsc->modinsn[1] = insn2;
5954 dsc->numinsns = 2;
5958 install_copro_load_store (gdbarch, regs, dsc, 0, rn);
5968 arm_displaced_step_copy_insn_closure *dsc)
5970 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
5971 dsc->u.branch.cond, status);
5972 enum pc_write_style write_pc = dsc->u.branch.exchange
5978 if (dsc->u.branch.link)
5983 ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size;
5985 if (dsc->is_thumb)
5988 displaced_write_reg (regs, dsc, ARM_LR_REGNUM, next_insn_addr,
5992 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, dsc->u.branch.dest, write_pc);
5999 arm_displaced_step_copy_insn_closure *dsc,
6010 dsc->u.branch.cond = cond;
6011 dsc->u.branch.link = link;
6012 dsc->u.branch.exchange = exchange;
6014 dsc->u.branch.dest = dsc->insn_addr;
6017 dsc->u.branch.dest = dsc->u.branch.dest & 0xfffffffc;
6019 if (dsc->is_thumb)
6020 dsc->u.branch.dest += 4 + offset;
6022 dsc->u.branch.dest += 8 + offset;
6024 dsc->cleanup = &cleanup_branch;
6028 regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
6048 dsc->modinsn[0] = ARM_NOP;
6050 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
6057 arm_displaced_step_copy_insn_closure *dsc)
6101 dsc->modinsn[0] = THUMB_NOP;
6103 install_b_bl_blx (gdbarch, regs, dsc, cond, exchange, link, offset);
6110 arm_displaced_step_copy_insn_closure *dsc)
6115 CORE_ADDR from = dsc->insn_addr;
6132 dsc->u.branch.cond = cond;
6133 dsc->u.branch.link = 0;
6134 dsc->u.branch.exchange = 0;
6135 dsc->u.branch.dest = from + 4 + offset;
6137 dsc->modinsn[0] = THUMB_NOP;
6139 dsc->cleanup = &cleanup_branch;
6148 arm_displaced_step_copy_insn_closure *dsc, int link,
6159 dsc->u.branch.dest = displaced_read_reg (regs, dsc, rm);
6161 dsc->u.branch.cond = cond;
6162 dsc->u.branch.link = link;
6164 dsc->u.branch.exchange = 1;
6166 dsc->cleanup = &cleanup_branch;
6171 regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
6181 dsc->modinsn[0] = ARM_NOP;
6183 install_bx_blx_reg (gdbarch, regs, dsc, link, cond, rm);
6190 arm_displaced_step_copy_insn_closure *dsc)
6197 dsc->modinsn[0] = THUMB_NOP;
6199 install_bx_blx_reg (gdbarch, regs, dsc, link, INST_AL, rm);
6209 regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
6211 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
6212 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6213 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6214 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6219 arm_displaced_step_copy_insn_closure *dsc)
6228 return arm_copy_unmodified (gdbarch, insn, "ALU immediate", dsc);
6246 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6247 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6248 rn_val = displaced_read_reg (regs, dsc, rn);
6249 rd_val = displaced_read_reg (regs, dsc, rd);
6250 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6251 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6252 dsc->rd = rd;
6255 dsc->modinsn[0] = insn & 0xfff00fff;
6257 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000;
6259 dsc->cleanup = &cleanup_alu_imm;
6267 arm_displaced_step_copy_insn_closure *dsc)
6281 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ALU imm", dsc);
6297 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6298 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6299 rn_val = displaced_read_reg (regs, dsc, rn);
6300 rd_val = displaced_read_reg (regs, dsc, rd);
6301 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6302 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6303 dsc->rd = rd;
6305 dsc->modinsn[0] = insn1;
6306 dsc->modinsn[1] = ((insn2 & 0xf0f0) | 0x1);
6307 dsc->numinsns = 2;
6309 dsc->cleanup = &cleanup_alu_imm;
6318 regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
6323 rd_val = displaced_read_reg (regs, dsc, 0);
6326 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
6328 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6333 arm_displaced_step_copy_insn_closure *dsc,
6350 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6351 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6352 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6353 rd_val = displaced_read_reg (regs, dsc, rd);
6354 rn_val = displaced_read_reg (regs, dsc, rn);
6355 rm_val = displaced_read_reg (regs, dsc, rm);
6356 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6357 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6358 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
6359 dsc->rd = rd;
6361 dsc->cleanup = &cleanup_alu_reg;
6366 arm_displaced_step_copy_insn_closure *dsc)
6372 return arm_copy_unmodified (gdbarch, insn, "ALU reg", dsc);
6378 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2;
6380 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002;
6382 install_alu_reg (gdbarch, regs, dsc, bits (insn, 12, 15), bits (insn, 16, 19),
6390 arm_displaced_step_copy_insn_closure *dsc)
6398 return thumb_copy_unmodified_16bit (gdbarch, insn, "ALU reg", dsc);
6402 dsc->modinsn[0] = ((insn & 0xff00) | 0x10);
6404 install_alu_reg (gdbarch, regs, dsc, rd, rd, rm);
6414 arm_displaced_step_copy_insn_closure *dsc)
6416 ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
6420 displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC);
6422 displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC);
6427 arm_displaced_step_copy_insn_closure *dsc,
6449 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
6451 rd_val = displaced_read_reg (regs, dsc, rd);
6452 rn_val = displaced_read_reg (regs, dsc, rn);
6453 rm_val = displaced_read_reg (regs, dsc, rm);
6454 rs_val = displaced_read_reg (regs, dsc, rs);
6455 displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC);
6456 displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC);
6457 displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC);
6458 displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC);
6459 dsc->rd = rd;
6460 dsc->cleanup = &cleanup_alu_shifted_reg;
6466 arm_displaced_step_copy_insn_closure *dsc)
6473 return arm_copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc);
6485 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302;
6487 dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302;
6489 install_alu_shifted_reg (gdbarch, regs, dsc, rd, rn, rm, rs);
6498 arm_displaced_step_copy_insn_closure *dsc)
6502 rt_val = displaced_read_reg (regs, dsc, 0);
6503 if (dsc->u.ldst.xfersize == 8)
6504 rt_val2 = displaced_read_reg (regs, dsc, 1);
6505 rn_val = displaced_read_reg (regs, dsc, 2);
6507 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6508 if (dsc->u.ldst.xfersize > 4)
6509 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6510 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
6511 if (!dsc->u.ldst.immed)
6512 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
6515 if (dsc->u.ldst.writeback)
6516 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
6518 displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC);
6519 if (dsc->u.ldst.xfersize == 8)
6520 displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC);
6527 arm_displaced_step_copy_insn_closure *dsc)
6529 ULONGEST rn_val = displaced_read_reg (regs, dsc, 2);
6531 displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
6532 if (dsc->u.ldst.xfersize > 4)
6533 displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC);
6534 displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC);
6535 if (!dsc->u.ldst.immed)
6536 displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC);
6537 if (!dsc->u.ldst.restore_r4)
6538 displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC);
6541 if (dsc->u.ldst.writeback)
6542 displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC);
6550 regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
6564 return arm_copy_unmodified (gdbarch, insn, "extra load/store", dsc);
6575 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6576 dsc->tmp[1] = displaced_read_reg (regs, dsc, 1);
6577 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6579 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6581 rt_val = displaced_read_reg (regs, dsc, rt);
6583 rt_val2 = displaced_read_reg (regs, dsc, rt + 1);
6584 rn_val = displaced_read_reg (regs, dsc, rn);
6586 rm_val = displaced_read_reg (regs, dsc, rm);
6588 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
6590 displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC);
6591 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
6593 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
6595 dsc->rd = rt;
6596 dsc->u.ldst.xfersize = bytesize[opcode];
6597 dsc->u.ldst.rn = rn;
6598 dsc->u.ldst.immed = immed;
6599 dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0;
6600 dsc->u.ldst.restore_r4 = 0;
6606 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6611 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6613 dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store;
6622 arm_displaced_step_copy_insn_closure *dsc, int load,
6628 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6629 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6631 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6633 dsc->tmp[4] = displaced_read_reg (regs, dsc, 4);
6635 rt_val = displaced_read_reg (regs, dsc, rt);
6636 rn_val = displaced_read_reg (regs, dsc, rn);
6638 rm_val = displaced_read_reg (regs, dsc, rm);
6640 displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC);
6641 displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC);
6643 displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC);
6644 dsc->rd = rt;
6645 dsc->u.ldst.xfersize = size;
6646 dsc->u.ldst.rn = rn;
6647 dsc->u.ldst.immed = immed;
6648 dsc->u.ldst.writeback = writeback;
6671 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
6678 arm_displaced_step_copy_insn_closure *dsc, int size)
6686 (unsigned int) dsc->insn_addr, rt, u_bit ? '+' : '-',
6701 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
6702 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
6703 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
6705 pc_val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
6709 displaced_write_reg (regs, dsc, 2, pc_val, CANNOT_WRITE_PC);
6710 displaced_write_reg (regs, dsc, 3, imm12, CANNOT_WRITE_PC);
6712 dsc->rd = rt;
6714 dsc->u.ldst.xfersize = size;
6715 dsc->u.ldst.immed = 0;
6716 dsc->u.ldst.writeback = 0;
6717 dsc->u.ldst.restore_r4 = 0;
6720 dsc->modinsn[0] = 0xf852;
6721 dsc->modinsn[1] = 0x3;
6722 dsc->numinsns = 2;
6724 dsc->cleanup = &cleanup_load;
6732 arm_displaced_step_copy_insn_closure *dsc,
6743 dsc);
6748 install_load_store (gdbarch, regs, dsc, 1, immed, writeback, 4,
6751 dsc->u.ldst.restore_r4 = 0;
6758 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
6759 dsc->modinsn[1] = insn2 & 0x0fff;
6766 dsc->modinsn[0] = (insn1 & 0xfff0) | 0x2;
6767 dsc->modinsn[1] = (insn2 & 0x0ff0) | 0x3;
6770 dsc->numinsns = 2;
6779 arm_displaced_step_copy_insn_closure *dsc,
6789 return arm_copy_unmodified (gdbarch, insn, "load/store", dsc);
6798 install_load_store (gdbarch, regs, dsc, load, immed, writeback, size,
6803 dsc->u.ldst.restore_r4 = 0;
6809 dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6814 dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6819 dsc->u.ldst.restore_r4 = 1;
6820 dsc->modinsn[0] = 0xe92d8000; /* push {pc} */
6821 dsc->modinsn[1] = 0xe8bd0010; /* pop {r4} */
6822 dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */
6823 dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */
6824 dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */
6828 dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000;
6830 dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003;
6832 dsc->numinsns = 6;
6835 dsc->cleanup = load ? &cleanup_load : &cleanup_store;
6862 arm_displaced_step_copy_insn_closure *dsc)
6864 int inc = dsc->u.block.increment;
6865 int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0;
6866 int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4);
6867 uint32_t regmask = dsc->u.block.regmask;
6869 CORE_ADDR xfer_addr = dsc->u.block.xfer_addr;
6870 int exception_return = dsc->u.block.load && dsc->u.block.user
6872 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6873 int do_transfer = condition_true (dsc->u.block.cond, status);
6885 gdb_assert (dsc->u.block.load != 0);
6888 dsc->u.block.load ? "ldm" : "stm",
6889 dsc->u.block.increment ? "inc" : "dec",
6890 dsc->u.block.before ? "before" : "after");
6906 displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC);
6913 if (dsc->u.block.writeback)
6914 displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr,
6922 arm_displaced_step_copy_insn_closure *dsc)
6924 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6925 int store_executed = condition_true (dsc->u.block.cond, status);
6927 = count_one_bits (dsc->u.block.regmask);
6937 if (dsc->u.block.increment)
6939 pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs;
6941 if (dsc->u.block.before)
6946 pc_stored_at = dsc->u.block.xfer_addr;
6948 if (dsc->u.block.before)
6953 stm_insn_addr = dsc->scratch_base;
6962 dsc->insn_addr + offset);
6973 arm_displaced_step_copy_insn_closure *dsc)
6975 uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
6976 int load_executed = condition_true (dsc->u.block.cond, status);
6977 unsigned int mask = dsc->u.block.regmask, write_reg = ARM_PC_REGNUM;
6998 ULONGEST rval = displaced_read_reg (regs, dsc, read_reg);
6999 displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC);
7020 displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg],
7029 if (dsc->u.block.writeback)
7031 ULONGEST new_rn_val = dsc->u.block.xfer_addr;
7033 if (dsc->u.block.increment)
7038 displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val,
7049 arm_displaced_step_copy_insn_closure *dsc)
7061 return arm_copy_unmodified (gdbarch, insn, "ldm/stm", dsc);
7067 return arm_copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc);
7073 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
7074 dsc->u.block.rn = rn;
7076 dsc->u.block.load = load;
7077 dsc->u.block.user = user;
7078 dsc->u.block.increment = increment;
7079 dsc->u.block.before = before;
7080 dsc->u.block.writeback = writeback;
7081 dsc->u.block.cond = bits (insn, 28, 31);
7083 dsc->u.block.regmask = insn & 0xffff;
7094 dsc->modinsn[0] = ARM_NOP;
7096 dsc->cleanup = &cleanup_block_load_all;
7109 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
7137 dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff);
7139 dsc->cleanup = &cleanup_block_load_pc;
7150 dsc->modinsn[0] = insn;
7152 dsc->cleanup = &cleanup_block_store_pc;
7161 arm_displaced_step_copy_insn_closure *dsc)
7170 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "ldm/stm", dsc);
7177 "unpredictable ldm/stm", dsc);
7184 dsc->u.block.regmask = (insn2 & 0xdfff);
7185 dsc->u.block.rn = rn;
7187 dsc->u.block.load = load;
7188 dsc->u.block.user = 0;
7189 dsc->u.block.increment = bit (insn1, 7);
7190 dsc->u.block.before = bit (insn1, 8);
7191 dsc->u.block.writeback = writeback;
7192 dsc->u.block.cond = INST_AL;
7193 dsc->u.block.xfer_addr = displaced_read_reg (regs, dsc, rn);
7197 if (dsc->u.block.regmask == 0xffff)
7204 unsigned int regmask = dsc->u.block.regmask;
7209 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
7219 (int) dsc->u.block.regmask, new_regmask);
7221 dsc->modinsn[0] = insn1;
7222 dsc->modinsn[1] = (new_regmask & 0xffff);
7223 dsc->numinsns = 2;
7225 dsc->cleanup = &cleanup_block_load_pc;
7230 dsc->modinsn[0] = insn1;
7231 dsc->modinsn[1] = insn2;
7232 dsc->numinsns = 2;
7233 dsc->cleanup = &cleanup_block_store_pc;
7306 arm_displaced_step_copy_insn_closure *dsc)
7308 CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size;
7313 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC);
7321 arm_displaced_step_copy_insn_closure *dsc)
7329 dsc->wrote_to_pc = 1;
7332 if (dsc->u.svc.copy_svc_os)
7333 return dsc->u.svc.copy_svc_os (gdbarch, regs, dsc);
7336 dsc->cleanup = &cleanup_svc;
7343 regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
7349 dsc->modinsn[0] = insn;
7351 return install_svc (gdbarch, regs, dsc);
7356 regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
7361 dsc->modinsn[0] = insn;
7363 return install_svc (gdbarch, regs, dsc);
7370 arm_displaced_step_copy_insn_closure *dsc)
7375 dsc->modinsn[0] = insn;
7382 arm_displaced_step_copy_insn_closure *dsc)
7388 dsc->modinsn[0] = insn1;
7389 dsc->modinsn[1] = insn2;
7390 dsc->numinsns = 2;
7399 arm_displaced_step_copy_insn_closure *dsc)
7404 dsc->modinsn[0] = insn;
7415 arm_displaced_step_copy_insn_closure *dsc)
7421 return arm_copy_unmodified (gdbarch, insn, "cps", dsc);
7423 return arm_copy_unmodified (gdbarch, insn, "setend", dsc);
7425 return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc);
7428 dsc);
7430 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
7432 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pli. */
7436 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
7438 return arm_copy_unpred (gdbarch, insn, dsc);
7441 return arm_copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */
7445 case 0x1: return arm_copy_unmodified (gdbarch, insn, "clrex", dsc);
7446 case 0x4: return arm_copy_unmodified (gdbarch, insn, "dsb", dsc);
7447 case 0x5: return arm_copy_unmodified (gdbarch, insn, "dmb", dsc);
7448 case 0x6: return arm_copy_unmodified (gdbarch, insn, "isb", dsc);
7449 default: return arm_copy_unpred (gdbarch, insn, dsc);
7452 return arm_copy_unpred (gdbarch, insn, dsc);
7457 return arm_copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc);
7459 return arm_copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */
7462 return arm_copy_preload_reg (gdbarch, insn, regs, dsc);
7464 return arm_copy_unpred (gdbarch, insn, dsc);
7466 return arm_copy_undef (gdbarch, insn, dsc);
7469 return arm_copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */
7475 arm_displaced_step_copy_insn_closure *dsc)
7478 return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc);
7483 return arm_copy_unmodified (gdbarch, insn, "srs", dsc);
7486 return arm_copy_unmodified (gdbarch, insn, "rfe", dsc);
7489 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
7496 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7499 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
7502 return arm_copy_undef (gdbarch, insn, dsc);
7512 return rn_f ? arm_copy_undef (gdbarch, insn, dsc)
7513 : arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7516 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
7520 return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc)
7521 : arm_copy_undef (gdbarch, insn, dsc);
7524 return arm_copy_undef (gdbarch, insn, dsc);
7529 return arm_copy_unmodified (gdbarch, insn, "stc/stc2", dsc);
7534 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7536 return arm_copy_undef (gdbarch, insn, dsc);
7540 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
7542 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7546 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
7548 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7551 return arm_copy_undef (gdbarch, insn, dsc);
7560 arm_displaced_step_copy_insn_closure *dsc)
7568 return arm_copy_unmodified (gdbarch, insn, "mrs/msr", dsc);
7572 return arm_copy_bx_blx_reg (gdbarch, insn, regs, dsc);
7574 return arm_copy_unmodified (gdbarch, insn, "clz", dsc);
7576 return arm_copy_undef (gdbarch, insn, dsc);
7581 return arm_copy_unmodified (gdbarch, insn, "bxj", dsc);
7583 return arm_copy_undef (gdbarch, insn, dsc);
7588 regs, dsc); /* blx register. */
7590 return arm_copy_undef (gdbarch, insn, dsc);
7593 return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc);
7597 return arm_copy_unmodified (gdbarch, insn, "bkpt", dsc);
7600 return arm_copy_unmodified (gdbarch, insn, "smc", dsc);
7604 return arm_copy_undef (gdbarch, insn, dsc);
7611 arm_displaced_step_copy_insn_closure *dsc)
7617 return arm_copy_unmodified (gdbarch, insn, "movw", dsc);
7620 return arm_copy_unmodified (gdbarch, insn, "movt", dsc);
7623 return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc);
7626 return arm_copy_alu_imm (gdbarch, insn, regs, dsc);
7633 return arm_copy_alu_reg (gdbarch, insn, regs, dsc);
7635 return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc);
7637 return arm_decode_miscellaneous (gdbarch, insn, regs, dsc);
7639 dsc);
7641 return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc);
7643 return arm_copy_unmodified (gdbarch, insn, "synch", dsc);
7647 dsc);
7657 arm_displaced_step_copy_insn_closure *dsc)
7664 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 0);
7667 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 4, 1);
7670 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 0);
7673 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 4, 1);
7676 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0);
7679 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1);
7682 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0);
7685 return arm_copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1);
7693 arm_displaced_step_copy_insn_closure *dsc)
7698 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc);
7701 return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc);
7706 "decode/pack/unpack/saturate/reverse", dsc);
7712 return arm_copy_unmodified (gdbarch, insn, "usad8", dsc);
7714 return arm_copy_unmodified (gdbarch, insn, "usada8", dsc);
7717 return arm_copy_undef (gdbarch, insn, dsc);
7721 return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc);
7723 return arm_copy_undef (gdbarch, insn, dsc);
7729 return arm_copy_unmodified (gdbarch, insn, "bfc", dsc);
7731 return arm_copy_unmodified (gdbarch, insn, "bfi", dsc);
7734 return arm_copy_undef (gdbarch, insn, dsc);
7738 return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc);
7740 return arm_copy_undef (gdbarch, insn, dsc);
7750 arm_displaced_step_copy_insn_closure *dsc)
7753 return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
7755 return arm_copy_block_xfer (gdbarch, insn, regs, dsc);
7761 arm_displaced_step_copy_insn_closure *dsc)
7768 return arm_copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc);
7772 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc);
7776 return arm_copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc);
7782 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7794 arm_displaced_step_copy_insn_closure *dsc)
7802 return thumb2_copy_alu_imm (gdbarch, insn1, insn2, regs, dsc);
7805 "dp (shift reg)", dsc);
7815 arm_displaced_step_copy_insn_closure *dsc)
7823 "vfp/neon vmov", dsc);
7829 "vfp/neon vstm/vpush", dsc);
7835 "vfp/neon vldm/vpop", dsc);
7839 "vstr", dsc);
7841 return thumb2_copy_copro_load_store (gdbarch, insn1, insn2, regs, dsc);
7850 regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
7857 return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc);
7861 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7865 return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
7867 return arm_copy_undef (gdbarch, insn, dsc);
7869 return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc);
7871 return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
7873 return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
7877 return arm_copy_unmodified (gdbarch, insn, "vfp dataproc", dsc);
7879 return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
7882 return arm_copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc);
7884 return arm_copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc);
7886 return arm_copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc);
7888 return arm_copy_svc (gdbarch, insn, regs, dsc);
7890 return arm_copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */
7896 arm_displaced_step_copy_insn_closure *dsc)
7908 dsc);
7910 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
7916 dsc);
7921 "stc/stc2", dsc);
7924 regs, dsc);
7929 return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2, "coproc", dsc);
7936 arm_displaced_step_copy_insn_closure *dsc, int rd)
7948 int val = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
7949 displaced_write_reg (regs, dsc, rd, val, CANNOT_WRITE_PC);
7954 arm_displaced_step_copy_insn_closure *dsc,
7959 dsc->modinsn[0] = (0x3000 | (rd << 8) | imm);
7961 install_pc_relative (gdbarch, regs, dsc, rd);
7969 arm_displaced_step_copy_insn_closure *dsc)
7977 return thumb_copy_pc_relative_16bit (gdbarch, regs, dsc, rd, imm8);
7983 arm_displaced_step_copy_insn_closure *dsc)
7999 dsc->modinsn[0] = (0xf1a0 | rd | imm_i);
8000 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
8005 dsc->modinsn[0] = (0xf100 | rd | imm_i);
8006 dsc->modinsn[1] = ((rd << 8) | imm_3_8);
8008 dsc->numinsns = 2;
8010 install_pc_relative (gdbarch, regs, dsc, rd);
8018 arm_displaced_step_copy_insn_closure *dsc)
8035 dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
8036 dsc->tmp[2] = displaced_read_reg (regs, dsc, 2);
8037 dsc->tmp[3] = displaced_read_reg (regs, dsc, 3);
8038 pc = displaced_read_reg (regs, dsc, ARM_PC_REGNUM);
8043 displaced_write_reg (regs, dsc, 2, pc, CANNOT_WRITE_PC);
8044 displaced_write_reg (regs, dsc, 3, imm8, CANNOT_WRITE_PC);
8046 dsc->rd = rt;
8047 dsc->u.ldst.xfersize = 4;
8048 dsc->u.ldst.rn = 0;
8049 dsc->u.ldst.immed = 0;
8050 dsc->u.ldst.writeback = 0;
8051 dsc->u.ldst.restore_r4 = 0;
8053 dsc->modinsn[0] = 0x58d0; /* ldr r0, [r2, r3]*/
8055 dsc->cleanup = &cleanup_load;
8065 arm_displaced_step_copy_insn_closure *dsc)
8069 CORE_ADDR from = dsc->insn_addr;
8071 int rn_val = displaced_read_reg (regs, dsc, rn);
8073 dsc->u.branch.cond = (rn_val && non_zero) || (!rn_val && !non_zero);
8077 if (dsc->u.branch.cond)
8079 dsc->u.branch.cond = INST_AL;
8080 dsc->u.branch.dest = from + 4 + imm5;
8083 dsc->u.branch.dest = from + 2;
8085 dsc->u.branch.link = 0;
8086 dsc->u.branch.exchange = 0;
8090 rn, rn_val, insn1, dsc->u.branch.dest);
8092 dsc->modinsn[0] = THUMB_NOP;
8094 dsc->cleanup = &cleanup_branch;
8102 arm_displaced_step_copy_insn_closure *dsc)
8109 rn_val = displaced_read_reg (regs, dsc, bits (insn1, 0, 3));
8110 rm_val = displaced_read_reg (regs, dsc, bits (insn2, 0, 3));
8132 dsc->u.branch.cond = INST_AL;
8133 dsc->u.branch.link = 0;
8134 dsc->u.branch.exchange = 0;
8135 dsc->u.branch.dest = dsc->insn_addr + 4 + 2 * halfwords;
8137 dsc->cleanup = &cleanup_branch;
8144 arm_displaced_step_copy_insn_closure *dsc)
8147 int val = displaced_read_reg (regs, dsc
8148 displaced_write_reg (regs, dsc, ARM_PC_REGNUM, val, BX_WRITE_PC);
8151 val = displaced_read_reg (regs, dsc, 8);
8152 displaced_write_reg (regs, dsc, 7, val, CANNOT_WRITE_PC);
8155 displaced_write_reg (regs, dsc, 8, dsc->tmp[0], CANNOT_WRITE_PC);
8162 arm_displaced_step_copy_insn_closure *dsc)
8164 dsc->u.block.regmask = insn1 & 0x00ff;
8188 dsc->u.block.regmask, insn1);
8190 if (dsc->u.block.regmask == 0xff)
8192 dsc->tmp[0] = displaced_read_reg (regs, dsc, 8);
8194 dsc->modinsn[0] = (insn1 & 0xfeff); /* POP {r0,r1,...,r6, r7} */
8195 dsc->modinsn[1] = 0x46b8; /* MOV r8, r7 */
8196 dsc->modinsn[2] = 0xbc80; /* POP {r7} */
8198 dsc->numinsns = 3;
8199 dsc->cleanup = &cleanup_pop_pc_16bit_all;
8203 unsigned int num_in_list = count_one_bits (dsc->u.block.regmask);
8208 dsc->tmp[i] = displaced_read_reg (regs, dsc, i);
8214 (int) dsc->u.block.regmask, new_regmask);
8216 dsc->u.block.regmask |= 0x8000;
8217 dsc->u.block.writeback = 0;
8218 dsc->u.block.cond = INST_AL;
8220 dsc->modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff);
8222 dsc->cleanup = &cleanup_block_load_pc;
8231 arm_displaced_step_copy_insn_closure *dsc)
8244 dsc);
8252 dsc);
8258 err = thumb_copy_bx_blx_reg (gdbarch, insn1, regs, dsc);
8260 err = thumb_copy_alu_reg (gdbarch, insn1, regs, dsc);
8263 dsc);
8267 err = thumb_copy_16bit_ldr_literal (gdbarch, insn1, regs, dsc);
8271 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldr/str", dsc);
8275 err = thumb_decode_pc_relative_16bit (gdbarch, insn1, regs, dsc);
8277 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "sp-relative", dsc);
8284 err = thumb_copy_cbnz_cbz (gdbarch, insn1, regs, dsc);
8288 err = thumb_copy_pop_pc_16bit (gdbarch, insn1, regs, dsc);
8290 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "pop", dsc);
8298 dsc);
8300 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "hints", dsc);
8303 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "misc", dsc);
8309 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "stm", dsc);
8311 err = thumb_copy_unmodified_16bit (gdbarch, insn1, "ldm", dsc);
8315 err = thumb_copy_b (gdbarch, insn1, dsc);
8317 err = thumb_copy_svc (gdbarch, insn1, regs, dsc);
8320 err = thumb_copy_b (gdbarch, insn1, dsc);
8334 arm_displaced_step_copy_insn_closure *dsc)
8347 return thumb2_copy_preload (gdbarch, insn1, insn2, regs, dsc);
8350 "pli/pld", dsc);
8355 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
8360 dsc);
8367 "pld/unalloc memhint", dsc);
8371 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc,
8375 "ldrh/ldrht", dsc);
8383 return thumb2_copy_load_literal (gdbarch, insn1, insn2, regs, dsc, 4);
8385 return thumb2_copy_load_reg_imm (gdbarch, insn1, insn2, regs, dsc,
8392 dsc, bit (insn2, 8), 1);
8395 "ldrt", dsc);
8399 dsc, 0, 0);
8404 return thumb_32bit_copy_undef (gdbarch, insn1, insn2, dsc);
8413 arm_displaced_step_copy_insn_closure *dsc)
8432 dsc);
8437 "load/store dual/ex", dsc);
8445 "srs/rfe", dsc);
8448 err = thumb2_copy_block_xfer (gdbarch, insn1, insn2, regs, dsc);
8457 dsc);
8460 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
8471 err = thumb2_copy_b_bl_blx (gdbarch, insn1, insn2, regs, dsc);
8474 "misc ctrl", dsc);
8484 regs, dsc);
8487 "dp/pb", dsc);
8491 "dp/mi", dsc);
8500 regs, dsc);
8504 dsc);
8511 "dp(reg)", dsc);
8515 "mul/mua/diff", dsc);
8519 "lmul/lmua", dsc);
8524 err = thumb2_decode_svc_copro (gdbarch, insn1, insn2, regs, dsc);
8540 arm_displaced_step_copy_insn_closure *dsc)
8549 dsc->is_thumb = 1;
8550 dsc->insn_size = thumb_insn_size (insn1);
8555 thumb_process_displaced_32bit_insn (gdbarch, insn1, insn2, regs, dsc);
8558 thumb_process_displaced_16bit_insn (gdbarch, insn1, regs, dsc);
8564 arm_displaced_step_copy_insn_closure *dsc)
8572 dsc->numinsns = 1;
8573 dsc->insn_addr = from;
8574 dsc->scratch_base = to;
8575 dsc->cleanup = NULL;
8576 dsc->wrote_to_pc = 0;
8579 return thumb_process_displaced_insn (gdbarch, from, regs, dsc);
8581 dsc->is_thumb = 0;
8582 dsc->insn_size = 4;
8588 err = arm_decode_unconditional (gdbarch, insn, regs, dsc);
8592 err = arm_decode_dp_misc (gdbarch, insn, regs, dsc);
8596 err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc);
8600 err = arm_decode_media (gdbarch, insn, dsc);
8604 err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc);
8608 err = arm_decode_svc_copro (gdbarch, insn, regs, dsc);
8621 arm_displaced_step_copy_insn_closure *dsc)
8626 int size = dsc->is_thumb ? 2 : 4;
8631 for (i = 0; i < dsc->numinsns; i++)
8635 dsc->modinsn[i], (unsigned long) to + offset);
8638 (unsigned short) dsc->modinsn[i],
8643 dsc->modinsn[i]);
8648 if (dsc->is_thumb)
8699 arm_displaced_step_copy_insn_closure *dsc
8702 if (dsc->cleanup)
8703 dsc->cleanup (gdbarch, regs, dsc);
8705 if (!dsc->wrote_to_pc)
8707 dsc->insn_addr + dsc->insn_size);
Indexes created Sun Apr 26 00:22:38 UTC 2026