Lines Matching defs:FIELD
305 /* The 'asm_data' field of a register set's hardware table entry
850 from the ELF header's e_flags field of the current executable
877 then use the 'module_opt' field we computed when we build the
1402 32-bit instruction, you have to consult the major opcode field ---
1406 field until you know if it's a 16- or a 32-bit instruction ---
1502 /* Return the LEN-bit field at POS from I. */
1503 #define FIELD(i, pos, len) (((i) >> (pos)) & ((1 << (len)) - 1))
1505 /* Like FIELD, but sign-extend the field's value. */
1506 #define SFIELD(i, pos, len) (SEXT (FIELD ((i), (pos), (len)), (len)))
1513 field is always in the same place, regardless of the width of the
1527 #define SWBH_32_BASE(i) (FIELD (i, 20, 4))
1528 #define SWBH_32_SOURCE(i) (FIELD (i, 24, 4))
1533 #define SW_IMMD_SOURCE(i) (FIELD (i, 24, 4))
1534 #define SW_IMMD_OFFSET(i) (FIELD (i, 18, 5) << 2)
1538 #define SW_REG_SOURCE(i) (FIELD (i, 24, 4))
1539 #define SW_REG_BASE(i) (FIELD (i, 20, 4))
1543 #define ADD3_16_REG_SRC1(i) (FIELD (i, 20, 4)) /* n */
1544 #define ADD3_16_REG_SRC2(i) (FIELD (i, 24, 4)) /* m */
1548 #define ADD3_32_TARGET(i) (FIELD (i, 24, 4))
1549 #define ADD3_32_SOURCE(i) (FIELD (i, 20, 4))
1554 #define ADD3_16_TARGET(i) (FIELD (i, 24, 4))
1555 #define ADD3_16_OFFSET(i) (FIELD (i, 18, 5) << 2)
1559 #define ADD_TARGET(i) (FIELD (i, 24, 4))
1565 #define LDC_IMM(i) ((FIELD (i, 16, 1) << 4) | FIELD (i, 20, 4))
1566 #define LDC_TARGET(i) (FIELD (i, 24, 4))
1570 #define LW_TARGET(i) (FIELD (i, 24, 4))
1571 #define LW_BASE(i) (FIELD (i, 20, 4))
1576 #define MOV_TARGET(i) (FIELD (i, 24, 4))
1577 #define MOV_SOURCE(i) (FIELD (i, 20, 4))
2398 the right me_module: the ELF header's e_flags field needs to
Indexes created Mon Apr 13 00:22:24 UTC 2026