Cross Reference: /src/external/gpl3/gdb.old/dist/gdb/stubs/m32r-stub.c

Lines Matching refs:registers
57  *    g             return the value of the CPU registers  hex data or ENN
58  *    G             set the value of the CPU registers     OK or ENN
118 /* Number of bytes of registers.  */
153 static int registers[NUMREGS];
226       mem2hex ((unsigned char *) &registers[PC], buf, 4, 0);
242   ptr = mem2hex ((unsigned char *) &registers[PC], ptr, 4, 0);	/* PC */
248   ptr = mem2hex ((unsigned char *) &registers[R13], ptr, 4, 0);	/* FP */
254   ptr = mem2hex ((unsigned char *) &registers[R15], ptr, 4, 0);	/* SP */
260       mem2hex ((unsigned char *) &registers[PC], buf, 4, 0);
261       switch (registers[R0])
267 	  sigval = registers[R1] & 0xff;
282 	  if (registers[R1] == 1 ||	/* write to stdout  */
283 	      registers[R1] == 2)	/* write to stderr  */
285 	      registers[R0] =
286 		gdb_write ((void *) registers[R2], registers[R3]);
328 	    registers[PC] = addr;
396 	case 'g':		/* return the value of the CPU registers */
397 	  mem2hex ((unsigned char *) registers, remcomOutBuffer, NUMREGBYTES,
409 		  hex2mem (ptr, (unsigned char *) &registers[regno], 4, 0);
414 		  stackmode = registers[PSW] & 0x80;
418 			registers[SPI] = registers[R15];
420 			registers[SPU] = registers[R15];
425 			registers[R15] = registers[SPU];
430 			registers[R15] = registers[SPI];
435 			registers[R15] = registers[SPI];
437 			registers[R15] = registers[SPU];
445 	case 'G':		/* set the value of the CPU registers - return OK */
446 	  hex2mem (ptr, (unsigned char *) registers, NUMREGBYTES, 0);
454 	    registers[PC] = addr;
470 		  ptr = mem2hex ((unsigned char *) &registers[PC], ptr, 4, 0);
477 		    mem2hex ((unsigned char *) &registers[R13], ptr, 4, 0);
484 		    mem2hex ((unsigned char *) &registers[R15], ptr, 4, 0);
497 	      if ((registers[PC] & 2) != 0)
724    that the compiler won't save any registers (if there is a fault
1038 	  return (registers[CBR] != 0);
1040 	  return (registers[CBR] == 0);
1051 	  return (registers[instr[0] & 0x0F] == registers[instr[1] & 0x0F]);
1053 	  return (registers[instr[0] & 0x0F] != registers[instr[1] & 0x0F]);
1061 	  return (registers[instr[1] & 0x0F] == 0);
1063 	  return (registers[instr[1] & 0x0F] != 0);
1065 	  return (registers[instr[1] & 0x0F] < 0);
1067 	  return (registers[instr[1] & 0x0F] >= 0);
1069 	  return (registers[instr[1] & 0x0F] <= 0);
1071 	  return (registers[instr[1] & 0x0F] > 0);
1089       return registers[BPC] & ~3;	/* pop BPC into PC */
1091       return registers[instr[1] & 0x0F] & ~3;	/* jump thru a register */
1124 	registers[R14] = (registers[PC] & ~3) + 4;
1166   unsigned long pc = registers[PC];
1180 	registers[PC] = branchDestination ((unsigned char *) pc, branchCode);
1182 	registers[PC] = pc + INSTRUCTION_SIZE (pc);
1263    Upon entry, all other registers are assumed to have not been modified
1270 	seth r1, #shigh(registers)\n\
1271 	add3 r1, r1, #low(registers)\n\
1317   psw = (struct PSWreg *) &registers[PSW];	/* fields of PSW register */
1321   registers[CBR] = psw->bc;	/* fix up pre-trap "C" register */
1331   registers[PC] = registers[BPC];	/* pre-trap PC */
1335     registers[SPU] = registers[R15];
1337     registers[SPI] = registers[R15];
1342 	seth r0, #shigh(registers+8)\n\
1343 	add3 r0, r0, #low(registers+8)\n\
1373 	seth r0, #shigh(registers)\n\
1374 	add3 r0, r0, #low(registers)\n\
1379 /* General trap handler, called after the registers have been stashed.
1416 	seth r1, #shigh(registers + 21*4) ; PC\n\
1417 	add3 r1, r1, #low(registers + 21*4)\n\
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