Lines Matching refs:opnd
956 dump_match_qualifiers (const struct aarch64_opnd_info *opnd,
964 curr[i] = opnd[i].qualifier;
1579 /* Check that indexed register operand OPND has a register in the range
1584 check_reglane (const aarch64_opnd_info *opnd,
1589 if (!value_in_range_p (opnd->reglane.regno, min_regno, max_regno))
1595 if (!value_in_range_p (opnd->reglane.index, min_index, max_index))
1604 /* Check that register list operand OPND has NUM_REGS registers and a
1608 check_reglist (const aarch64_opnd_info *opnd,
1612 if (opnd->reglist.num_regs != num_regs)
1617 if (opnd->reglist.stride != stride)
1674 /* Check that indexed ZA operand OPND has:
1687 check_za_access (const aarch64_opnd_info *opnd,
1692 if (!value_in_range_p (opnd->indexed_za.index.regno, min_wreg, min_wreg + 3))
1708 if (!value_in_range_p (opnd->indexed_za.index.imm, 0, max_index))
1714 if ((opnd->indexed_za.index.imm % range_size) != 0)
1724 if (opnd->indexed_za.index.countm1 != range_size - 1)
1742 if (opnd->indexed_za.group_size != group_size
1743 && (status_vg || opnd->indexed_za.group_size != 0 ))
1800 const aarch64_opnd_info *opnd = opnds + idx;
1801 aarch64_opnd_qualifier_t qualifier = opnd->qualifier;
1804 assert (opcode->operands[idx] == opnd->type && opnd->type == type);
1864 if (!aarch64_stack_pointer_p (opnd))
1888 if (!check_reglane (opnd, mismatch_detail, idx,
1896 if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31, 0, 1))
1902 if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31, 0, 3))
1907 size = aarch64_get_qualifier_esize (opnd->qualifier);
1908 if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31,
1914 size = aarch64_get_qualifier_esize (opnd->qualifier);
1915 if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31,
1923 if (!check_reglane (opnd, mismatch_detail, idx, "pn", 8, 15,
1944 if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31,
1961 if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 15,
1967 if (opnd->reg.regno > 15)
1975 size = aarch64_get_qualifier_esize (opnd->qualifier);
1977 if (!check_za_access (opnd, mismatch_detail, idx,
1999 if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
2001 if ((opnd->reglist.first_regno % num) != 0)
2015 if (!check_reglist (opnd, mismatch_detail, idx, num, 16 / num))
2017 num = 16 | (opnd->reglist.stride - 1);
2018 if ((opnd->reglist.first_regno & ~num) != 0)
2030 if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
2045 size = aarch64_get_qualifier_esize (opnd->qualifier);
2047 if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value, 1,
2054 if (!check_za_access (opnd, mismatch_detail, idx, 12, 15, 1,
2062 if (!check_za_access (opnd, mismatch_detail, idx, 8, 7, 1,
2069 if (!check_za_access (opnd, mismatch_detail, idx, 8, 1, 4,
2076 opnd, mismatch_detail, idx, 8, 3, 2,
2083 if (!check_za_access (opnd, mismatch_detail, idx, 8, 3, 4,
2090 if (!check_za_access (opnd, mismatch_detail, idx, 8, 7, 2,
2097 if (!check_za_access (opnd, mismatch_detail, idx, 12, 7, 2,
2104 if (!check_za_access (opnd, mismatch_detail, idx, 12, 3, 2,
2111 if (!check_za_access (opnd, mismatch_detail, idx, 12, 1, 2,
2118 if (!check_za_access (opnd, mismatch_detail, idx, 12, 0, 2,
2125 if (!check_za_access (opnd, mismatch_detail, idx, 12, 3, 4,
2132 if (!check_za_access (opnd, mismatch_detail, idx, 12, 1, 4,
2139 if (!check_za_access (opnd, mismatch_detail, idx, 12, 15, 1,
2147 if (!check_za_access (opnd, mismatch_detail, idx, 12, 0, 4,
2155 size = aarch64_get_qualifier_esize (opnd->qualifier);
2160 if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value, num,
2175 if (opnd->reg.regno < 8)
2183 if (opnd->reg.regno >= 8
2211 if (opnd->addr.writeback == 1)
2219 if (opnd->addr.writeback == 1 && opnd->addr.preind != 1)
2230 if (opnd->addr.writeback == 0)
2238 if (opnd->addr.writeback)
2240 && !opnd->addr.preind)
2242 && !opnd->addr.postind))
2251 assert (opnd->addr.writeback == 0);
2261 size = aarch64_get_qualifier_esize (opnd->qualifier);
2262 if (!value_in_range_p (opnd->addr.offset.imm, -64 * size, 63 * size))
2268 if (!value_aligned_p (opnd->addr.offset.imm, size))
2277 if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
2288 if ((value_in_range_p (opnd->addr.offset.imm, 0, 255)
2289 && !value_aligned_p (opnd->addr.offset.imm, size))
2290 || value_in_range_p (opnd->addr.offset.imm, -256, -1))
2298 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4088))
2303 if (!value_aligned_p (opnd->addr.offset.imm, 8))
2312 if (!value_in_range_p (opnd->addr.offset.imm, -1024, 1008))
2318 if (!value_aligned_p (opnd->addr.offset.imm, 16))
2327 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4080))
2333 if (!value_aligned_p (opnd->addr.offset.imm, 16))
2343 if (opnd->addr.offset.is_reg)
2345 if (value_in_range_p (opnd->addr.offset.regno, 0, 30))
2369 if ((int) num_bytes != opnd->addr.offset.imm)
2382 size = aarch64_get_qualifier_esize (opnd->qualifier);
2384 if (opnd->shifter.amount != 0
2385 && opnd->shifter.amount != (int)get_logsz (size))
2393 switch (opnd->shifter.kind)
2407 imm = opnd->addr.offset.imm;
2412 if (!value_in_range_p (opnd->addr.offset.imm, 0, 4095 * size))
2418 if (!value_aligned_p (opnd->addr.offset.imm, size))
2430 imm = opnd->imm.value;
2451 if (!value_in_range_p (opnd->addr.offset.imm, 0, 15))
2465 assert (!opnd->addr.offset.is_reg);
2466 assert (opnd->addr.preind);
2470 if ((opnd->addr.offset.imm != 0 && !opnd->shifter.operator_present)
2471 || (opnd->shifter.operator_present
2472 && opnd->shifter.kind != AARCH64_MOD_MUL_VL))
2478 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
2484 if (!value_aligned_p (opnd->addr.offset.imm, num))
2508 assert (!opnd->addr.offset.is_reg);
2509 assert (opnd->addr.preind);
2513 if (opnd->shifter.operator_present
2514 || opnd->shifter.amount_present)
2520 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
2526 if (!value_aligned_p (opnd->addr.offset.imm, num))
2543 assert (opnd->addr.offset.is_reg);
2544 assert (opnd->addr.preind);
2546 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
2547 assert (opnd->shifter.operator_present == 0);
2567 assert (opnd->addr.offset.is_reg);
2568 assert (opnd->addr.preind);
2570 && opnd->addr.offset.regno == 31)
2576 if (((1 << opnd->shifter.kind) & modifiers) == 0
2577 || (opnd->shifter.amount
2608 assert (opnd->addr.offset.is_reg);
2609 assert (opnd->addr.preind);
2610 if (((1 << opnd->shifter.kind) & modifiers) == 0
2611 || opnd->shifter.amount < 0
2612 || opnd->shifter.amount > 3)
2636 ? opnd->addr.offset.imm * -1
2637 : opnd->addr.offset.imm;
2639 && opnd->addr.offset.imm != 0)
2649 if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
2665 if (!value_in_range_p (opnd->reglist.index, 0, num))
2677 if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
2684 if (num != 1 && !check_reglist (opnd, mismatch_detail, idx, num, 1))
2692 if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
2698 if (opnd->reglist.stride != 1)
2707 imm = opnd->imm.value;
2722 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2728 if (opnd->shifter.amount != 0 && opnd->shifter.amount != 12)
2734 if (!value_fit_unsigned_field_p (opnd->imm.value, 12))
2744 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2751 if (!value_aligned_p (opnd->shifter.amount, 16))
2757 if (!value_in_range_p (opnd->shifter.amount, 0, size * 8 - 16))
2763 if (opnd->imm.value < 0)
2769 if (!value_fit_unsigned_field_p (opnd->imm.value, 16))
2780 imm = opnd->imm.value;
2828 if (!value_fit_unsigned_field_p (opnd->imm.value, size))
2838 if (!value_in_range_p (opnd->imm.value, 0, 1008))
2844 if (!value_aligned_p (opnd->imm.value, 16))
2859 if (!value_fit_signed_field_p (opnd->imm.value, size))
2872 if (opnd->imm.value + opnds[idx-1].imm.value > size)
2885 uint64_t uimm = opnd->imm.value;
2899 if (opnd->imm.value != 0)
2910 if (opnd->imm.value != 0
2911 && opnd->imm.value != 90
2912 && opnd->imm.value != 180
2913 && opnd->imm.value != 270)
2924 if (opnd->imm.value != 90 && opnd->imm.value != 270)
2935 if (opnd->imm.value != size)
2945 if (!value_in_range_p (opnd->imm.value, 0, size * 8 - 1))
2955 if (!value_in_range_p (opnd->imm.value, 1, size * 8))
2968 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2976 if (opnd->shifter.kind != AARCH64_MOD_MSL)
2984 if (opnd->shifter.kind != AARCH64_MOD_NONE)
3000 if (!value_in_range_p (opnd->imm.value, -128, 255))
3006 else if (aarch64_shrink_expanded_imm8 (opnd->imm.value) < 0)
3016 switch (opnd->shifter.kind)
3020 if (!value_in_range_p (opnd->shifter.amount, 0, (size - 1) * 8))
3026 if (!value_aligned_p (opnd->shifter.amount, 8))
3034 if (opnd->shifter.amount != 8 && opnd->shifter.amount != 16)
3042 if (opnd->shifter.kind != AARCH64_MOD_NONE)
3055 if (opnd->imm.is_fp == 0)
3065 if (!value_in_range_p (opnd->imm.value, 0, 255))
3071 if (opnd->shifter.kind != AARCH64_MOD_NONE)
3082 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
3085 uvalue = opnd->imm.value;
3086 shift = opnd->shifter.amount;
3132 assert (opnd->imm.is_fp);
3133 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x3f800000)
3142 assert (opnd->imm.is_fp);
3143 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x40000000)
3152 assert (opnd->imm.is_fp);
3153 if (opnd->imm.value != 0 && opnd->imm.value != 0x3f800000)
3164 uint64_t uimm = ~opnd->imm.value;
3177 uint64_t uimm = opnd->imm.value;
3194 assert (opnd->shifter.kind == AARCH64_MOD_MUL);
3195 if (!value_in_range_p (opnd->shifter.amount, 1, 16))
3206 if (!value_in_range_p (opnd->imm.value, 0, 8 * size - 1))
3216 if (!value_in_range_p (opnd->imm.value, 1, size))
3229 if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
3237 if (!value_in_range_p (opnd->imm.value, 0, 56))
3242 if (opnd->imm.value % 8 != 0)
3251 if (!value_in_range_p (opnd->imm.value, 0, 3))
3268 if (aarch64_pstatefields[i].value == opnd->pstatefield)
3280 if (opcode->iclass == ldst_regoff && opnd->prfop->value >= 24)
3303 if (!check_reglane (opnd, mismatch_detail, idx, "v", 0, 31,
3314 if (!value_in_range_p (opnd->reglane.index, 0, num))
3330 && !value_in_range_p (opnd->reglane.regno, 0, 15))
3336 && !value_in_range_p (opnd->reglane.regno, 0, 7))
3348 if (!aarch64_extend_operator_p (opnd->shifter.kind)
3349 && opnd->shifter.kind != AARCH64_MOD_LSL)
3362 if (!opnd->shifter.operator_present)
3368 else if (opnd->shifter.kind == AARCH64_MOD_LSL)
3375 assert (opnd->shifter.operator_present /* Default to LSL. */
3376 || opnd->shifter.kind == AARCH64_MOD_LSL);
3377 if (!value_in_range_p (opnd->shifter.amount, 0, 4))
3388 && opnd->shifter.kind != AARCH64_MOD_LSL
3389 && opnd->shifter.kind != AARCH64_MOD_UXTX
3390 && opnd->shifter.kind != AARCH64_MOD_SXTX)
3400 if (!aarch64_shift_operator_p (opnd->shifter.kind))
3406 if (opnd->shifter.kind == AARCH64_MOD_ROR
3414 if (!value_in_range_p (opnd->shifter.amount, 0, num))
3422 /* We expect here that opnd->shifter.kind != AARCH64_MOD_LSL
3425 if (!value_in_range_p (opnd->shifter.amount, 0, 7))
3670 /* Get the name of the integer offset register in OPND, using the shift type
3674 get_offset_int_reg_name (const aarch64_opnd_info *opnd)
3676 switch (opnd->shifter.kind)
3680 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_W, 0);
3684 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_X, 0);
3691 /* Get the name of the SVE vector offset register in OPND, using the operand
3826 /* Produce the string representation of the register list operand *OPND
3830 print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
3834 const int num_regs = opnd->reglist.num_regs;
3835 const int stride = opnd->reglist.stride;
3836 const int first_reg = opnd->reglist.first_regno;
3838 const char *qlf_name = aarch64_get_qualifier_name (opnd->qualifier);
3841 assert (opnd->type != AARCH64_OPND_LEt || opnd->reglist.has_index);
3845 if (opnd->reglist.has_index)
3848 style_imm (styler, "%" PRIi64, (opnd->reglist.index % 100)));
3856 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3903 /* Print the register+immediate address in OPND to BUF, which has SIZE
3908 const aarch64_opnd_info *opnd,
3912 if (opnd->addr.writeback)
3914 if (opnd->addr.preind)
3916 if (opnd->type == AARCH64_OPND_ADDR_SIMM10 && !opnd->addr.offset.imm)
3921 style_imm (styler, "#%d", opnd->addr.offset.imm));
3926 style_imm (styler, "#%d", opnd->addr.offset.imm));
3930 if (opnd->shifter.operator_present)
3932 assert (opnd->shifter.kind == AARCH64_MOD_MUL_VL);
3935 style_imm (styler, "#%d", opnd->addr.offset.imm),
3938 else if (opnd->addr.offset.imm)
3941 style_imm (styler, "#%d", opnd->addr.offset.imm));
3948 *OPND in the buffer pointed by BUF of size SIZE. BASE and OFFSET are
3952 const aarch64_opnd_info *opnd,
3959 const char *shift_name = aarch64_operand_modifiers[opnd->shifter.kind].name;
3963 if (opnd->type == AARCH64_OPND_SVE_ADDR_ZX && offset != NULL
3973 if (!opnd->shifter.amount && (opnd->qualifier != AARCH64_OPND_QLF_S_B
3974 || !opnd->shifter.amount_present))
3982 if (opnd->shifter.kind == AARCH64_MOD_LSL)
3995 (opnd->shifter.amount % 100)));
4071 const aarch64_opnd_info *opnd = opnds + idx;
4087 switch (opnd->type)
4105 the <ic_op>, therefore we use opnd->present to override the
4107 if (opnd->type == AARCH64_OPND_Rt_SYS)
4109 if (!opnd->present)
4112 else if ((opnd->type == AARCH64_OPND_Rt_IN_SYS_ALIASES)
4113 && (opnd->reg.regno
4118 snprintf (comment, comment_size, "unpredictable encoding (Rt!=31): #%u", opnd->reg.regno);
4123 && (opnd->reg.regno
4126 assert (opnd->qualifier == AARCH64_OPND_QLF_W
4127 || opnd->qualifier == AARCH64_OPND_QLF_X);
4129 style_reg (styler, get_int_reg_name (opnd->reg.regno,
4130 opnd->qualifier, 0)));
4138 assert (opnd->qualifier == AARCH64_OPND_QLF_W
4139 || opnd->qualifier == AARCH64_OPND_QLF_WSP
4140 || opnd->qualifier == AARCH64_OPND_QLF_X
4141 || opnd->qualifier == AARCH64_OPND_QLF_SP);
4143 style_reg (styler, get_int_reg_name (opnd->reg.regno,
4144 opnd->qualifier, 1)));
4148 kind = opnd->shifter.kind;
4152 && ((opnd->qualifier == AARCH64_OPND_QLF_W
4155 || (opnd->qualifier == AARCH64_OPND_QLF_X
4160 if (opnd->shifter.amount == 0)
4165 get_int_reg_name (opnd->reg.regno,
4166 opnd->qualifier, 0)));
4170 if (opnd->shifter.amount)
4172 style_reg (styler, get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0)),
4174 style_imm (styler, "#%" PRIi64, opnd->shifter.amount));
4177 style_reg (styler, get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0)),
4182 assert (opnd->qualifier == AARCH64_OPND_QLF_W
4183 || opnd->qualifier == AARCH64_OPND_QLF_X);
4184 if (opnd->shifter.amount == 0 && opnd->shifter.kind == AARCH64_MOD_LSL)
4186 style_reg (styler, get_int_reg_name (opnd->reg.regno,
4187 opnd->qualifier, 0)));
4190 style_reg (styler, get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0)),
4191 style_sub_mnem (styler, aarch64_operand_modifiers[opnd->shifter.kind].name),
4192 style_imm (styler, "#%" PRIi64, opnd->shifter.amount));
4196 assert (opnd->qualifier == AARCH64_OPND_QLF_X);
4197 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
4198 if (opnd->shifter.amount == 0)
4200 style_reg (styler, get_int_reg_name (opnd->reg.regno,
4201 opnd->qualifier, 0)));
4204 style_reg (styler, get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0)),
4205 style_sub_mnem (styler, aarch64_operand_modifiers[opnd->shifter.kind].name),
4206 style_imm (styler, "#%" PRIi64, opnd->shifter.amount));
4224 aarch64_get_qualifier_name (opnd->qualifier),
4225 opnd->reg.regno));
4233 style_reg (styler, "v%d.%s", opnd->reg.regno,
4234 aarch64_get_qualifier_name (opnd->qualifier)));
4244 style_reg (styler, "v%d.%s", opnd->reglane.regno,
4245 aarch64_get_qualifier_name (opnd->qualifier)),
4246 style_imm (styler, "%" PRIi64, opnd->reglane.index));
4253 style_reg (styler, "v%d", opnd->reglane.regno),
4254 style_imm (styler, "%" PRIi64, opnd->reglane.index));
4260 style_reg (styler, "v%d.d", opnd->reg.regno),
4269 print_register_list (buf, size, opnd, "v", styler);
4281 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
4283 style_reg (styler, "p%d", opnd->reg.regno));
4284 else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z
4285 || opnd->qualifier == AARCH64_OPND_QLF_P_M)
4287 style_reg (styler, "p%d/%s", opnd->reg.regno,
4288 aarch64_get_qualifier_name (opnd->qualifier)));
4291 style_reg (styler, "p%d.%s", opnd->reg.regno,
4292 aarch64_get_qualifier_name (opnd->qualifier)));
4302 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
4304 style_reg (styler, "pn%d", opnd->reg.regno));
4305 else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z
4306 || opnd->qualifier == AARCH64_OPND_QLF_P_M)
4308 style_reg (styler, "pn%d/%s", opnd->reg.regno,
4309 aarch64_get_qualifier_name (opnd->qualifier)));
4312 style_reg (styler, "pn%d.%s", opnd->reg.regno,
4313 aarch64_get_qualifier_name (opnd->qualifier)));
4318 print_register_list (buf, size, opnd, "p", styler);
4324 style_reg (styler, "pn%d", opnd->reglane.regno),
4325 style_imm (styler, "%" PRIi64, opnd->reglane.index));
4336 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
4337 snprintf (buf, size, "%s", style_reg (styler, "z%d", opnd->reg.regno));
4340 style_reg (styler, "z%d.%s", opnd->reg.regno,
4341 aarch64_get_qualifier_name (opnd->qualifier)));
4356 print_register_list (buf, size, opnd, "z", styler);
4389 (opnd->qualifier == AARCH64_OPND_QLF_NIL
4390 ? style_reg (styler, "z%d", opnd->reglane.regno)
4391 : style_reg (styler, "z%d.%s", opnd->reglane.regno,
4392 aarch64_get_qualifier_name (opnd->qualifier))),
4393 style_imm (styler, "%" PRIi64, opnd->reglane.index));
4404 if (opnd->reglane.index == 0)
4405 snprintf (buf, size, "%s", style_reg (styler, "z%d", opnd->reg.regno));
4408 style_reg (styler, "z%d", opnd->reglane.regno),
4409 style_imm (styler, "%" PRIi64, opnd->reglane.index));
4416 style_reg (styler, "za%d.%s", opnd->reg.regno,
4417 aarch64_get_qualifier_name (opnd->qualifier)));
4426 opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "{" : "",
4428 opnd->indexed_za.regno,
4429 opnd->indexed_za.v == 1 ? 'v' : 'h',
4430 aarch64_get_qualifier_name (opnd->qualifier)),
4431 style_reg (styler, "w%d", opnd->indexed_za.index.regno),
4432 style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm),
4433 opnd->indexed_za.index.countm1 ? ":" : "",
4434 (opnd->indexed_za.index.countm1
4436 opnd->indexed_za.index.imm
4437 + opnd->indexed_za.index.countm1)
4439 opnd->indexed_za.group_size ? ", " : "",
4440 opnd->indexed_za.group_size == 2
4442 : opnd->indexed_za.group_size == 4
4444 opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "}" : "");
4448 print_sme_za_list (buf, size, opnd->imm.value, styler);
4460 opnd->qualifier == AARCH64_OPND_QLF_NIL ? "" : ".",
4461 (opnd->qualifier == AARCH64_OPND_QLF_NIL
4463 : aarch64_get_qualifier_name (opnd->qualifier))),
4464 style_reg (styler, "w%d", opnd->indexed_za.index.regno),
4465 style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm),
4466 opnd->indexed_za.index.countm1 ? ":" : "",
4467 (opnd->indexed_za.index.countm1
4469 opnd->indexed_za.index.imm
4470 + opnd->indexed_za.index.countm1)
4472 opnd->indexed_za.group_size ? ", " : "",
4473 opnd->indexed_za.group_size == 2
4475 : opnd->indexed_za.group_size == 4
4490 opnd->indexed_za.regno,
4491 opnd->indexed_za.v ? 'v': 'h',
4492 opnd->qualifier == AARCH64_OPND_QLF_NIL ? "" : ".",
4493 (opnd->qualifier == AARCH64_OPND_QLF_NIL
4495 : aarch64_get_qualifier_name (opnd->qualifier))),
4496 style_reg (styler, "w%d", opnd->indexed_za.index.regno),
4497 style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm),
4498 opnd->indexed_za.index.countm1 ? ":" : "",
4499 opnd->indexed_za.index.countm1 ? style_imm (styler, "%d",
4500 opnd->indexed_za.index.imm
4501 + opnd->indexed_za.index.countm1):"");
4506 style_reg (styler, opnd->reg.regno == 's' ? "sm" : "za"));
4511 style_reg (styler, "p%d.%s", opnd->indexed_za.regno,
4512 aarch64_get_qualifier_name (opnd->qualifier)),
4513 style_reg (styler, "w%d", opnd->indexed_za.index.regno),
4514 style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm));
4519 enum_value = opnd->imm.value;
4526 enum_value = opnd->imm.value;
4535 style_reg (styler, "C%" PRIi64, opnd->imm.value));
4582 style_imm (styler, "#%" PRIi64, opnd->imm.value));
4590 c.i = opnd->imm.value;
4597 && opnd->imm.value == get_optional_operand_default_value (opcode))
4599 enum_value = opnd->imm.value;
4606 style_imm (styler, "#%" PRIi64, opnd->imm.value));
4611 && !opnd->shifter.operator_present
4612 && opnd->imm.value == get_optional_operand_default_value (opcode))
4614 enum_value = opnd->imm.value;
4616 if (aarch64_sve_pattern_array[opnd->imm.value])
4619 aarch64_sve_pattern_array[opnd->imm.value]));
4622 style_imm (styler, "#%" PRIi64, opnd->imm.value));
4623 if (opnd->shifter.operator_present)
4627 = aarch64_operand_modifiers[opnd->shifter.kind].name;
4630 style_imm (styler, "#%" PRIi64, opnd->shifter.amount));
4635 enum_value = opnd->imm.value;
4642 style_imm (styler, "#%" PRIi64, opnd->imm.value));
4650 int imm32 = opnd->imm.value;
4658 opnd->imm.value));
4659 snprintf (comment, comment_size, "#%" PRIi64, opnd->imm.value);
4677 if (opnd->shifter.amount)
4679 style_imm (styler, "#0x%" PRIx64, opnd->imm.value),
4681 style_imm (styler, "#%" PRIi64, opnd->shifter.amount));
4684 style_imm (styler, "#0x%" PRIx64, opnd->imm.value));
4689 if ((! opnd->shifter.amount && opnd->shifter.kind == AARCH64_MOD_LSL)
4690 || opnd->shifter.kind == AARCH64_MOD_NONE)
4692 style_imm (styler, "#0x%" PRIx64, opnd->imm.value));
4695 style_imm (styler, "#0x%" PRIx64, opnd->imm.value),
4696 style_sub_mnem (styler, aarch64_operand_modifiers[opnd->shifter.kind].name),
4697 style_imm (styler, "#%" PRIi64, opnd->shifter.amount));
4702 if (opnd->shifter.amount)
4704 style_imm (styler, "#%" PRIi64, opnd->imm.value),
4706 style_imm (styler, "#%" PRIi64, opnd->shifter.amount));
4709 style_imm (styler, "#%" PRIi64, opnd->imm.value));
4720 c.i = expand_fp_imm (2, opnd->imm.value);
4727 c.i = expand_fp_imm (4, opnd->imm.value);
4734 c.i = expand_fp_imm (8, opnd->imm.value);
4752 && (opnd->imm.value ==
4757 style_imm (styler, "#0x%x", (unsigned int) opnd->imm.value));
4763 style_sub_mnem (styler, opnd->cond->names[0]));
4764 num_conds = ARRAY_SIZE (opnd->cond->names);
4765 for (i = 1; i < num_conds && opnd->cond->names[i]; ++i)
4770 opnd->cond->names[0], opnd->cond->names[i]);
4773 opnd->cond->names[i]);
4779 + opnd->imm.value;
4795 addr = pc + AARCH64_PCREL_OFFSET + opnd->imm.value;
4810 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
4811 if (opnd->type == AARCH64_OPND_SIMD_ADDR_POST)
4813 if (opnd->addr.offset.is_reg)
4816 style_reg (styler, "x%d", opnd->addr.offset.regno));
4820 style_imm (styler, "#%d", opnd->addr.offset.imm));
4839 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
4840 get_offset_int_reg_name (opnd), styler);
4845 (buf, size, opnd,
4846 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
4847 get_64bit_int_reg_name (opnd->addr.offset.regno, 0), styler);
4863 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
4864 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier),
4894 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
4903 (buf, size, opnd,
4904 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
4912 (buf, size, opnd,
4913 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
4914 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier),
4919 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
4920 if (opnd->addr.offset.imm)
4923 style_imm (styler, "#%d", opnd->addr.offset.imm));
4936 || (sr->flags & opnd->sysreg.flags) == opnd->sysreg.flags)
4941 if (aarch64_sys_regs[i].value == opnd->sysreg.value
4970 unsigned int value = opnd->sysreg.value;
4981 if (aarch64_pstatefields[i].value == opnd->pstatefield)
4987 && (PSTATE_DECODE_CRM (opnd->sysreg.flags)
5003 snprintf (buf, size, "%s", style_reg (styler, opnd->sysins_op->name));
5009 if (opnd->barrier->name[0] == '#')
5010 snprintf (buf, size, "%s", style_imm (styler, opnd->barrier->name));
5013 style_sub_mnem (styler, opnd->barrier->name));
5020 || (opnd->barrier->value
5023 style_imm (styler, "#0x%x", opnd->barrier->value));
5027 if (opnd->prfop->name != NULL)
5028 snprintf (buf, size, "%s", style_sub_mnem (styler, opnd->prfop->name));
5031 opnd->prfop->value));
5035 enum_value = opnd->imm.value;
5042 style_imm (styler, "#%" PRIi64, opnd->imm.value));
5059 style_imm (styler, "%d", (int) opnd->imm.value));
5063 style_imm (styler, "%d", (int) opnd->imm.value),
5076 if ((HINT_FLAG (opnd->hint_option->value) & HINT_OPD_F_NOPRINT) == 0)
5078 style_sub_mnem (styler, opnd->hint_option->name));
5085 get_int_reg_name (opnd->reg.regno,
5091 style_reg (styler, get_int_reg_name (opnd->reg.regno,
Indexes created Thu May 07 00:24:58 UTC 2026