Lines Matching refs:given
5049 mve_extract_pred_mask (long given)
5051 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5056 num_instructions_vpt_block (long given)
5058 long mask = mve_extract_pred_mask (given);
5088 mark_inside_vpt_block (long given)
5092 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5094 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5193 arm_decode_shift (long given, fprintf_styled_ftype func, void *stream,
5196 func (stream, dis_style_register, "%s", arm_regnames[given & 0xf]);
5198 if ((given & 0xff0) != 0)
5200 if ((given & 0x10) == 0)
5202 int amount = (given & 0xf80) >> 7;
5203 int shift = (given & 0x60) >> 5;
5229 else if ((given & 0x80) == 0x80)
5236 arm_shift[(given & 0x60) >> 5]);
5238 arm_regnames[(given & 0xf00) >> 8]);
5244 arm_regnames[(given & 0xf00) >> 8]);
5300 is_vpt_instruction (long given)
5304 if ((given & 0x0040e000) == 0)
5308 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5310 || ((given & 0xefb10f50) == 0xee310f40)
5312 || ((given & 0xff811f51) == 0xfe010f00)
5314 || ((given & 0xff811f51) == 0xfe010f01
5315 && ((given & 0x300000) != 0x300000))
5317 || ((given & 0xff811f50) == 0xfe011f00)
5319 || ((given & 0xff811f70) == 0xfe010f40)
5321 || ((given & 0xff811f70) == 0xfe010f60)
5323 || ((given & 0xff811f50) == 0xfe011f40)
5325 || ((given & 0xffbf1fff) == 0xfe310f4d))
5331 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5335 arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5342 return ((given >> start) & ((2ul << bits) - 1));
5345 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5350 arm_decode_field_multiple (unsigned long given, unsigned int start,
5362 value = arm_decode_field (given, start, end);
5365 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5369 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5374 is_mve_encoding_conflict (unsigned long given,
5380 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5386 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5388 if ((arm_decode_field (given, 12, 12) == 0)
5389 && (arm_decode_field (given, 0, 0) == 1))
5394 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5396 if (arm_decode_field (given, 0, 3) == 0xd)
5406 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5408 if (arm_decode_field (given, 20, 21) == 3)
5413 if ((arm_decode_field (given, 12, 12) == 0)
5414 && (arm_decode_field (given, 0, 0) == 1))
5420 if (arm_decode_field (given, 0, 3) == 0xd)
5465 if (arm_decode_field (given, 20, 21) == 3)
5474 if (arm_decode_field (given, 7, 8) == 3)
5481 if ((arm_decode_field (given, 24, 24) == 0)
5482 && (arm_decode_field (given, 21, 21) == 0))
5486 else if ((arm_decode_field (given, 7, 8) == 3))
5497 if ((arm_decode_field (given, 24, 24) == 0)
5498 && (arm_decode_field (given, 21, 21) == 0))
5506 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5511 unsigned long cmode = arm_decode_field (given, 8, 11);
5523 unsigned long cmode = arm_decode_field (given, 8, 11);
5536 if ((arm_decode_field (given, 5, 5) == 1)
5537 && (arm_decode_field (given, 8, 11) != 0xe))
5544 unsigned long size = arm_decode_field (given, 19, 20);
5566 if (arm_decode_field (given, 18, 19) == 3)
5575 if (arm_decode_field (given, 20, 22) == 7)
5581 if ((arm_decode_field (given, 20, 22) & 6) == 6)
5588 if ((arm_decode_field (given, 20, 21) == 3)
5589 || (arm_decode_field (given, 1, 3) == 7))
5596 if (arm_decode_field (given, 16, 18) == 0)
5598 unsigned long sz = arm_decode_field (given, 19, 20);
5615 if (arm_decode_field (given, 19, 21) == 0)
5621 if (arm_decode_field (given, 16, 19) == 0xf)
5637 if (arm_decode_field (given, 9, 11) == 0x7)
5646 rm = arm_decode_field (given, 0, 3);
5647 rn = arm_decode_field (given, 16, 19);
5658 if (arm_decode_field (given, 0, 3) == 0xd)
5662 if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
5677 unsigned long given,
5685 imm = arm_decode_field (given, 0, 6);
5692 gpr = arm_decode_field (given, 16, 18);
5697 gpr = arm_decode_field (given, 16, 18);
5703 gpr = arm_decode_field (given, 16, 19);
5709 gpr = arm_decode_field (given, 16, 19);
5715 gpr = arm_decode_field (given, 16, 19);
5722 p = arm_decode_field (given, 24, 24);
5723 w = arm_decode_field (given, 21, 21);
5725 add = arm_decode_field (given, 23, 23);
5756 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5761 is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5769 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5788 if (arm_decode_field (given, 20, 21) == 3)
5797 if (arm_decode_field (given, 7, 8) == 3)
5806 if (arm_decode_field (given, 7, 8) <= 1)
5815 if ((arm_decode_field (given, 7, 8) == 0))
5824 if ((arm_decode_field (given, 7, 8) <= 1))
5833 if (arm_decode_field (given, 7, 8) == 3)
5838 else if ((arm_decode_field (given, 28, 28) == 0)
5839 && (arm_decode_field (given, 7, 8) == 0))
5848 if (arm_decode_field (given, 7, 8) == 3)
5853 else if ((arm_decode_field (given, 28, 28) == 0)
5854 && (arm_decode_field (given, 7, 8) == 1))
5859 given, 7, 8) == 0)
5868 if (arm_decode_field (given, 7, 8) != 2)
5873 else if (arm_decode_field (given, 28, 28) == 0)
5882 if (arm_decode_field (given, 7, 8) != 3)
5887 else if (arm_decode_field (given, 28, 28) == 0)
5896 if (arm_decode_field (given, 7, 8) == 3)
5906 unsigned long size = arm_decode_field (given, 7, 8);
5922 if (arm_decode_field (given, 7, 8) != 2)
5931 if (arm_decode_field (given, 7, 8) != 3)
5941 unsigned long imm6 = arm_decode_field (given, 16, 21);
5948 if ((arm_decode_field (given, 9, 9) == 0)
5963 unsigned long size = arm_decode_field (given, 18, 19);
5980 unsigned long op1 = arm_decode_field (given, 21, 22);
5981 unsigned long op2 = arm_decode_field (given, 5, 6);
5982 unsigned long u = arm_decode_field (given, 23, 23);
6009 if (arm_decode_field (given, 5, 6) == 2)
6011 unsigned long op1 = arm_decode_field (given, 21, 22);
6024 if ((arm_decode_field (given, 5, 5) == 1)
6025 || (arm_decode_field (given, 22, 22) == 1))
6030 if (arm_decode_field (given, 5, 5) == 0)
6032 unsigned long cmode = arm_decode_field (given, 8, 11);
6047 if (arm_decode_field (given, 18, 19) == 2)
6059 if ((arm_decode_field (given, 28, 28) == 1)
6060 && (arm_decode_field (given, 12, 12) == 1))
6073 unsigned long sz = arm_decode_field (given, 19, 20);
6094 unsigned long sz = arm_decode_field (given, 19, 21);
6110 if (arm_decode_field (given, 19, 20) == 0)
6119 if (arm_decode_field (given, 18, 19) == 3)
6132 if (arm_decode_field (given, 18, 19) == 3)
6141 if (arm_decode_field (given, 18, 19) == 0)
6151 unsigned long size = arm_decode_field (given, 18, 19);
6162 if (arm_decode_field (given, 18, 19) != 3)
6175 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6180 is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6189 if ((arm_decode_field (given, 12, 12) == 0)
6190 && (arm_decode_field (given, 5, 5) == 1))
6204 if (arm_decode_field (given, 0, 3) == 0xd)
6214 unsigned long gpr = arm_decode_field (given, 12, 15);
6256 unsigned long gpr = arm_decode_field (given, 0, 3);
6274 unsigned long rn = arm_decode_field (given, 16, 19);
6276 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6288 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6300 unsigned long rn = arm_decode_field (given, 16, 19);
6302 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6314 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6330 unsigned long rn = arm_decode_field (given, 16, 19);
6332 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6347 if (arm_decode_field (given, 0, 0) == 1)
6359 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6360 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6368 if (arm_decode_field (given, 16, 19) == 0xf)
6380 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6381 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6393 if (arm_decode_field (given, 16, 19) == 0xf)
6398 else if (arm_decode_field (given, 0, 0) == 1)
6409 if (arm_decode_field (given, 16, 19) == 0xf)
6422 unsigned long rt = arm_decode_field (given, 0, 3);
6423 unsigned long rt2 = arm_decode_field (given, 16, 19);
6457 unsigned long rda = arm_decode_field (given, 12, 15);
6478 if (arm_decode_field (given, 20, 21) == 2)
6480 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6481 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6482 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6503 if (arm_decode_field (given, 28, 28) == 1)
6505 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6506 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6507 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6523 unsigned long gpr = arm_decode_field (given, 0, 3);
6535 if (arm_decode_field (given, 28, 28) == 1)
6538 = arm_decode_field_multiple (given, 13, 15, 22, 22);
6539 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6557 if (arm_decode_field (given, 20, 22) == 6)
6567 if (arm_decode_field (given, 1, 3) == 6)
6578 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6579 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6580 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6591 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6592 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6593 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6608 if (arm_decode_field (given, 20, 20) == 1)
6610 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6611 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6612 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6628 if (arm_decode_field (given, 16, 19) == 0xd)
6638 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6639 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6662 unsigned long gpr = arm_decode_field (given, 9, 11);
6684 given)
6686 unsigned long op1 = arm_decode_field (given, 21, 22);
6687 unsigned long op2 = arm_decode_field (given, 5, 6);
6688 unsigned long h = arm_decode_field (given, 16, 16);
6723 print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6727 int cmode = (given >> 8) & 0xf;
6728 int op = (given >> 5) & 0x1;
6738 bits |= ((given >> ibit_loc) & 1) << 7;
6739 bits |= ((given >> 16) & 7) << 4;
6740 bits |= ((given >> 0) & 15) << 0;
7037 unsigned long given,
7043 unsigned long q_reg_start = arm_decode_field_multiple (given,
7087 unsigned long given,
7097 switch (arm_decode_field (given, 8, 9))
7123 switch (arm_decode_field (given, 7, 9))
7163 unsigned long given,
7174 mode = (((given & 0x200) >> 7)
7175 | ((given & 0x10000000) >> 27)
7176 | ((given & 0x100) >> 8));
7219 unsigned long size = arm_decode_field (given, 18, 19);
7220 unsigned long op = arm_decode_field (given, 7, 8);
7272 unsigned long op = arm_decode_field (given, 28, 28);
7282 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7728 print_mve_shift_n (struct disassemble_info *info, long given,
7741 unsigned imm6 = (given & 0x3f0000) >> 16;
7760 print_vec_condition (struct disassemble_info *info, long given,
7771 vec_cond = (((given & 0x1000) >> 10)
7772 | ((given & 1) << 1)
7773 | ((given & 0x0080) >> 7));
7779 vec_cond = (((given & 0x1000) >> 10)
7780 | ((given & 0x0020) >> 4)
7781 | ((given & 0x0080) >> 7));
7787 vec_cond = (given & 0x0080) >> 7;
7793 vec_cond = 2 | ((given & 0x0080) >> 7);
7799 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7805 vec_cond = (given & 0x0080) >> 7;
7811 vec_cond = 2 | ((given & 0x0080) >> 7);
7817 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7833 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7834 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7835 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7836 #define PRE_BIT_SET (given & (1 << P_BIT))
7873 long given,
7925 cp_num = (given >> 8) & 0xf;
7943 if ((given & 0xf0000000) == 0xf0000000)
7950 cond = (given >> 28) & 0xf;
7960 if ((given & mask) != value)
8000 && arm_decode_field (given, 24, 24) == 0
8001 && arm_decode_field (given, 21, 21) == 0)
8037 int rn = (given >> 16) & 0xf;
8038 bfd_vma offset = given & 0xff;
8041 offset = given & 0x7f;
8045 arm_regnames [(given >> 16) & 0xf]);
8125 int regno = ((given >> 12) & 0xf) | ((given
8126 int offset = (given >> 1) & 0x3f;
8150 bool single = ((given >> 8) & 1) == 0;
8152 int Dreg = (given >> 22) & 0x1;
8153 int Vdreg = (given >> 12) & 0xf;
8156 int num = (given >> (single ? 0 : 1)) & 0x7f;
8210 = arm_decode_field_multiple (given, 13, 15, 22, 22);
8245 c = arm_decode_bitfield (c, given, &value, &width);
8267 if (given & (1 << 6))
8330 int from = (given & (1 << 7)) ? 32 : 16;
8415 regno = given & 0x0000000f;
8419 regno += (given >> 5) & 1;
8422 regno += ((given >> 5) & 1) << 4;
8426 regno = (given >> 12) & 0x0000000f;
8430 regno += (given >> 22) & 1;
8433 regno += ((given >> 22) & 1) << 4;
8437 regno = (given >> 16) & 0x0000000f;
8441 regno += (given >> 7) & 1;
8444 regno += ((given >> 7) & 1) << 4;
8449 regno = (given >> 12) & 0x0000000f;
8453 regno += (given >> 22) & 1;
8456 regno += ((given >> 22) & 1) << 4;
8468 int count = given & 0xff;
8493 switch (given & 0x00400100)
8514 /* given (20, 23) | given (0, 3) */
8515 value = ((given >> 16) & 0xf0) | (given & 0xf);
8525 int offset = given & 0xff;
8526 int multiplier = (given & 0x00000100) ? 4 : 1;
8530 arm_regnames [(given >> 16) & 0xf]);
8565 int imm4 = (given >> 4) & 0xf;
8566 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8568 const char *rm = arm_regnames [given & 0xf];
8569 const char *rn = arm_regnames [(given >> 16) & 0xf];
8617 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8654 long given,
8658 pc, info, given, thumb);
8664 long given,
8668 pc, info, given, thumb);
8677 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8683 if (((given & 0x000f0000) == 0x000f0000)
8684 && ((given & 0x02000000) == 0))
8686 offset = given & 0xfff;
8731 arm_regnames[(given >> 16) & 0xf]);
8735 if ((given & 0x02000000) == 0)
8738 offset = given & 0xfff;
8750 arm_decode_shift (given, func, stream, true);
8758 if ((given & 0x02000000) == 0)
8761 offset = given & 0xfff;
8770 arm_decode_shift (given, func, stream, true);
8785 print_insn_cde (struct disassemble_info *info, long given, bool thumb)
8799 given >> insn->coproc_shift) & insn->coproc_mask;
8804 if ((given & insn->mask) == insn->value)
8840 c = arm_decode_bitfield (c, given, &value, &width);
8875 if (given & (1 << 6))
8877 else if (given & (1 << 24))
8901 uint8_t proc_number = (given >> 8) & 0x7;
8909 if (given & (1 << a_offset))
8946 print_insn_neon (struct disassemble_info *info, long given, bool thumb)
8956 if ((given & 0xef000000) == 0xef000000)
8959 unsigned long bit28 = given & (1 << 28);
8961 given &= 0x00ffffff;
8963 given |= 0xf3000000;
8965 given |= 0xf2000000;
8967 else if ((given & 0xff000000) == 0xf9000000)
8968 given ^= 0xf9000000 ^ 0xf4000000;
8970 else if ((given & 0xff000000) == 0xfe000000
8971 || (given & 0xff000000) == 0xfc000000)
8974 else if ((given & 0xff900f5f) != 0xee800b10)
9003 if ((given & 0xf0000000) == 0xf0000000)
9012 cond = (given >> 28) & 0xf;
9018 if ((given & cond_mask) == cond_value)
9075 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9076 int rn = ((given >> 16) & 0xf);
9077 int rm = ((given >> 0) & 0xf);
9078 int align = ((given >> 4) & 0x3);
9079 int type = ((given >> 8) & 0xf);
9125 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9126 int rn = ((given >> 16) & 0xf);
9127 int rm = ((given >> 0) & 0xf);
9128 int idx_align = ((given >> 4) & 0xf);
9130 int size = ((given >> 10) & 0x3);
9132 int length = ((given >> 8) & 3) + 1;
9213 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9214 int rn = ((given >> 16) & 0xf);
9215 int rm = ((given >> 0) & 0xf);
9216 int align = ((given >> 4) & 0x1);
9217 int size = ((given >> 6) & 0x3);
9218 int type = ((given >> 8) & 0x3);
9220 int stride = ((given >> 5) & 0x1);
9278 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
9279 int size = (given >> 20) & 3;
9291 int cmode = (given >> 8) & 0xf;
9292 int op = (given >> 5) & 0x1;
9298 bits |= ((given >> 24) & 1) << 7;
9299 bits |= ((given >> 16) & 7) << 4;
9300 bits |= ((given >> 0) & 15) << 0;
9427 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9428 int num = (given >> 8) & 0x3;
9457 c = arm_decode_bitfield (c, given, &value, &width);
9502 if (given & (1 << 6))
9574 print_insn_mve (struct disassemble_info *info, long given)
9584 if (((given & insn->mask) == insn->value)
9585 && !is_mve_encoding_conflict (given, insn->mve_op))
9601 else if (is_mve_unpredictable (given, insn->mve_op,
9605 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
9611 && (arm_decode_field (given, 1, 3)
9612 == arm_decode_field (given, 17, 19)))
9642 if (arm_decode_field (given, 23, 23) == 0)
9653 print_mve_vld_str_addr (info, given, insn->mve_op);
9658 long mve_mask = mve_extract_pred_mask (given);
9667 imm5 |= arm_decode_field (given, 6, 7);
9668 imm5 |= (arm_decode_field (given, 12, 14) << 2);
9676 (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
9680 print_vec_condition (info, given, insn->mve_op);
9684 if (arm_decode_field (given, 0, 0) == 1)
9687 = arm_decode_field (given, 4, 4)
9688 | (arm_decode_field (given, 6, 6) << 1);
9697 print_mve_rounding_mode (info, given, insn->mve_op);
9701 print_mve_vcvt_size (info, given, insn->mve_op);
9706 unsigned long op1 = arm_decode_field (given, 21, 22);
9711 if (arm_decode_field (given, 23, 23) == 0)
9714 if ((arm_decode_field (given, 5, 6) == 0)
9725 if (arm_decode_field (given, 28, 28) == 0)
9738 if (arm_decode_field (given, 21, 21) == 1)
9743 print_mve_register_blocks (info, given, insn->mve_op);
9749 print_simd_imm8 (info, given, 28, insn);
9753 print_mve_vmov_index (info, given);
9757 if (arm_decode_field (given, 12, 12) == 0)
9764 if (arm_decode_field (given, 12, 12) == 1)
9774 c = arm_decode_bitfield (c, given, &value, &width);
9830 = arm_decode_field (given, 0, 6);
9891 print_mve_shift_n (info, given, insn->mve_op);
9950 && is_vpt_instruction (given))
9951 mark_inside_vpt_block (given);
10033 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
10042 if (print_insn_coprocessor (pc, info, given, false))
10045 if (print_insn_neon (info, given, false))
10048 if (print_insn_generic_coprocessor (pc, info, given, false))
10053 given & insn->mask) != insn->value)
10062 if ((given & 0xF0000000) != 0xF0000000
10100 value_in_comment = print_arm_address (pc, info, given);
10106 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
10125 if ((given & 0x004f0000) == 0x004f0000)
10128 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
10168 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
10172 arm_regnames[(given >> 16) & 0xf]);
10201 arm_regnames[given & 0xf]);
10207 && ((given & 0xf) == ((given >> 12) & 0xf)))
10233 arm_regnames[given & 0xf]);
10238 && (given & 0xf) == ((given >> 12) & 0xf))
10250 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
10259 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
10271 if (((given >> 28) & 0xf) != 0xe)
10273 arm_conditional [(given >> 28) & 0xf]);
10283 if ((given & (1 << reg)) != 0)
10298 arm_decode_shift (given, func, stream, false);
10302 if ((given & 0x02000000) != 0)
10304 unsigned int rotate = (given & 0xf00) >> 7;
10305 unsigned int immed = (given & 0xff);
10327 arm_decode_shift (given, func, stream, true);
10331 if ((given & 0x0000f000) == 0x0000f000)
10335 if ((given & 0x0000f000) == 0x0000f000)
10341 if ((given & 0x01200000) == 0x00200000)
10347 int offset = given & 0xff;
10354 arm_regnames [(given >> 16) & 0xf]);
10396 offset += given & 0x00ffffff;
10400 if (given & 0x01000000)
10414 if ((given & 0x02000200) == 0x200)
10417 unsigned sysm = (given & 0x004f0000) >> 16;
10419 sysm |= (given & 0x300) >> 4;
10431 (given & 0x00400000) ? 'S' : 'C');
10433 if (given & 0x80000)
10435 if (given & 0x40000)
10437 if (given & 0x20000)
10439 if (given & 0x10000)
10445 if ((given & 0xf0) == 0x60)
10447 switch (given & 0xf)
10454 (int) given & 0xf);
10460 const char * opt = data_barrier_option (given & 0xf);
10465 "#%d", (int) given & 0xf);
10475 c = arm_decode_bitfield (c, given, &value, &width);
10530 if ((given & 0x0fffffff) == 0x0FF00000)
10533 else if ((given & 0x0fffffff) == 0x0FF00001)
10567 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
10577 long msb = (given & 0x001f0000) >> 16;
10578 long lsb = (given & 0x00000f80) >> 7;
10597 unsigned sysm = (given & 0x004f0000) >> 16;
10599 sysm |= (given & 0x300) >> 4;
10614 long hi = (given & 0x000f0000) >> 4;
10615 long lo = (given & 0x00000fff);
10651 (unsigned) given);
10658 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
10667 if ((given & insn->mask) == insn->value)
10729 ifthen_next_state = given & 0xff;
10730 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
10732 ((given ^ tmp) & 0x10) ? "e" : "t");
10735 arm_conditional[(given >> 4) & 0xf]);
10756 reg = (given >> 3) & 0x7;
10757 if (given & (1 << 6))
10768 reg = given & 0x7;
10769 if (given & (1 << 7))
10777 if (given & (1 << 8))
10781 if (*c == 'O' && (given & (1 << 8)))
10794 if ((given & (1 << reg)) != 0)
10828 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
10836 + ((given & 0x00f8) >> 2)
10837 + ((given & 0x0200) >> 3));
10851 long imm = (given & 0x07c0) >> 6;
10878 reg = given >> bitstart;
10945 if ((given & (1 << bitstart)) != 0)
10951 if ((given & (1 << bitstart)) != 0)
10976 (unsigned) given);
11035 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
11044 if (print_insn_coprocessor (pc, info, given, true))
11047 if (!is_mve && print_insn_neon (info, given, true))
11050 if (is_mve && print_insn_mve (info, given))
11053 if (print_insn_cde (info, given, true))
11056 if (print_insn_generic_coprocessor (pc, info, given, true))
11060 if ((given & insn->mask) == insn->value)
11123 imm12 |= (given & 0x000000ffu);
11124 imm12 |= (given & 0x00007000u) >> 4;
11125 imm12 |= (given & 0x04000000u) >> 15;
11135 bits |= (given & 0x000000ffu);
11136 bits |= (given & 0x00007000u) >> 4;
11137 bits |= (given & 0x04000000u) >> 15;
11160 imm |= (given & 0x000000ffu);
11161 imm |= (given & 0x00007000u) >> 4;
11162 imm |= (given & 0x04000000u) >> 15;
11163 imm |= (given & 0x000f0000u) >> 4;
11173 imm |= (given & 0x000f0000u) >> 16;
11174 imm |= (given & 0x00000ff0u) >> 0;
11175 imm |= (given & 0x0000000fu) << 12;
11185 imm |= (given & 0x000f0000u) >> 4;
11186 imm |= (given & 0x00000fffu) >> 0;
11196 imm |= (given & 0x00000fffu);
11197 imm |= (given & 0x000f0000u) >> 4;
11205 unsigned int reg = (given & 0x0000000fu);
11206 unsigned int stp = (given & 0x00000030u) >> 4;
11208 imm |= (given & 0x000000c0u) >> 6;
11209 imm |= (given & 0x00007000u) >> 10;
11257 unsigned int Rn = (given & 0x000f0000) >> 16;
11259 unsigned int op = (given & 0x00000f00) >> 8;
11260 unsigned int i12 = (given & 0x00000fff);
11261 unsigned int i8 = (given & 0x000000ff);
11356 unsigned int Rn = (given & 0x000f0000) >> 16;
11357 unsigned int off = (given & 0x000000ff);
11397 unsigned int Sbit = (given & 0x01000000) >> 24;
11398 unsigned int type = (given & 0x00600000) >> 21;
11429 if ((given & (1 << reg)) != 0)
11449 unsigned int msb = (given & 0x0000001f);
11452 lsb |= (given & 0x000000c0u) >> 6;
11453 lsb |= (given & 0x00007000u) >> 10;
11462 unsigned int width = (given & 0x0000001f) + 1;
11465 lsb |= (given & 0x000000c0u) >> 6;
11466 lsb |= (given & 0x00007000u) >> 10;
11475 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
11482 unsigned int immA = (given & 0x001f0000u) >> 16;
11483 unsigned int immB = (given & 0x000007feu) >> 1;
11484 unsigned int immC = (given & 0x00000800u) >> 11;
11499 unsigned int immA = (given & 0x007f0000u) >> 16;
11500 unsigned int immB = (given & 0x000007feu) >> 1;
11501 unsigned int immC = (given & 0x00000800u) >> 11;
11516 unsigned int immA = (given & 0x00010000u) >> 16;
11517 unsigned int immB = (given & 0x000007feu) >> 1;
11518 unsigned int immC = (given & 0x00000800u) >> 11;
11529 unsigned int T = (given & 0x00020000u) >> 17;
11530 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
11540 unsigned int immh = (given & 0x000007feu) >> 1;
11541 unsigned int imml = (given & 0x00000800u) >> 11;
11553 unsigned int immh = (given & 0x000007feu) >> 1;
11554 unsigned int imml = (given & 0x00000800u) >> 11;
11566 unsigned int S = (given & 0x04000000u) >> 26;
11567 unsigned int J1 = (given & 0x00002000u) >> 13;
11568 unsigned int J2 = (given & 0x00000800u) >> 11;
11574 offset |= (given & 0x003f0000) >> 4;
11575 offset |= (given & 0x000007ff) << 1;
11590 unsigned int S = (given & 0x04000000u) >> 26;
11591 unsigned int I1 = (given & 0x00002000u) >> 13;
11592 unsigned int I2 = (given & 0x00000800u) >> 11;
11598 offset |= (given & 0x03ff0000u) >> 4;
11599 offset |= (given & 0x000007ffu) << 1;
11604 if ((given & 0x00001000u) == 0)
11620 shift |= (given & 0x000000c0u) >> 6;
11621 shift |= (given & 0x00007000u) >> 10;
11640 unsigned int rot = (given & 0x00000030) >> 4;
11652 if ((given & 0xf0) == 0x60)
11654 switch (given & 0xf)
11661 (int) given & 0xf);
11667 const char * opt = data_barrier_option (given & 0xf);
11672 (int) given & 0xf);
11677 if ((given & 0xff) == 0)
11680 (given & 0x100000) ? 'S' : 'C');
11682 if (given & 0x800)
11684 if (given & 0x400)
11686 if (given & 0x200)
11688 if (given & 0x100)
11693 psr_name (given & 0xff));
11695 else if ((given & 0x20) == 0x20)
11698 unsigned sysm = (given & 0xf00) >> 8;
11700 sysm |= (given & 0x30);
11701 sysm |= (given & 0x00100000) >> 14;
11713 psr_name (given & 0xff));
11720 psr_name (given & 0xff));
11721 else if (((given & 0xff) == 0)
11722 || ((given & 0x20) == 0x20))
11725 unsigned sm = (given & 0xf0000) >> 16;
11727 sm |= (given & 0x30);
11728 sm |= (given & 0x00100000) >> 14;
11739 psr_name (given & 0xff));
11748 c = arm_decode_bitfield (c, given, &val, &width);
11825 if (((given >> 16) & 0xf) == 0xf)
11827 bfd_vma offset = (given & 0xff) * 4;
11829 if ((given & (1 << 23)) == 0)
11853 (unsigned) given);
11862 long given)
11871 func (info->stream, dis_style_immediate, "0x%02lx", given);
11876 func (info->stream, dis_style_immediate, "0x%04lx", given);
11881 func (info->stream, dis_style_immediate, "0x%08lx", given);
12270 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
12348 and thus on bfd_mach_arm_XXX value. Therefore for a given
12361 unsigned long given;
12537 given = 0;
12540 given = b[i] | (given << 8);
12543 given = b[i] | (given << 8);
12555 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24);
12557 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24);
12571 given = (b[0]) | (b[1] << 8);
12573 given = (b[1]) | (b[0] << 8);
12579 if ((given & 0xF800) == 0xF800
12580 || (given & 0xF800) == 0xF000
12581 || (given & 0xF800) == 0xE800)
12585 given = (b[0]) | (b[1] << 8) | (given << 16);
12587 given = (b[1]) | (b[0] << 8) | (given << 16);
12620 printer (pc, info, given);
Indexes created Sun May 31 00:26:10 UTC 2026