Cross Reference: /src/external/gpl3/gdb.old/dist/opcodes/ppc-opc.c

Lines Matching refs:RA
149 /* The BA and BB fields in an XL form instruction or the RA and RB fields or
695    between R's value and the RA value (ie, they cannot both be non zero).  */
704   int64_t ra = (insn >> 16) & 0x1f;
705   if (ra != 0 && value != 0)
725   int64_t ra = (insn >> 16) & 0x1f;
727   if (ra != 0 && pcrel != 0)
1500 /* The RA field in a D or X form instruction which is an updating
1501    load, which means that the RA field may not be zero and may not
1529 /* The RA field in an lmw instruction, which has special value
1556 /* The RA field in the DQ form lq or an lswx instruction, which have special
1588 /* The RA field in a D or X form instruction which is an updating
1589    store or an updating floating point load, which means that the RA
2835   /* The RA and RB fields in a VX form instruction when they must be the same.
3319   /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
3320 #define RA NSISIGNOPT + 1
3324   /* As above, but 0 in the RA field means zero, not r0.  */
3325 #define RA0 RA + 1
3332   /* The RA field in the DQ form lq or an lswx instruction, which have
3351   /* The RA field in a D or X form instruction which is an updating
3352      load, which means that the RA field may not be zero and may not
3357   /* The RA field in an lmw instruction, which has special value
3362   /* The RA field in a D or X form instruction which is an updating
3364      which means that the RA field may not be zero.  */
3368   /* The RA field of the tlbwe, dccci and iccci instructions,
4008 /* The same as P_D_MASK, but with the RA and PCREL fields specified.  */
4182 /* The main opcode mask with the RA field clear.  */
4493 /* An X form instruction with the RA bits specified as two ops.  */
4551 /* An X_MASK with an accumulator register and the RA and RB fields fixed.  */
4584 /* An X_MASK with the RA/VA field fixed.  */
4604 /* An X_MASK with the RA and RB fields fixed.  */
4607 /* An XBF_MASK with the RA and RB fields fixed.  */
4616 /* An X_MASK with the RT and RA fields fixed.  */
4625 /* An X_MASK with the RT, RA and RB fields fixed.  */
4667 /* An X form instruction with RT and RA fields specified */
4668 #define XRTRA(op, xop, rt, ra)			\
4671    | ((((uint64_t)(ra)) & 0x1f) << 16))
4742 /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear.  */
5046 {"tdlgti",	OPTO(2,TOLGT),	OPTO_MASK,   PPC64,	PPCVLE|EXT,	{RA, SI}},
5047 {"tdllti",	OPTO(2,TOLLT),	OPTO_MASK,   PPC64,	PPCVLE|EXT,	{RA, SI}},
5048 {"tdeqi",	OPTO(2,TOEQ),	OPTO_MASK,   PPC64,	PPCVLE|EXT,	{RA, SI}},
5049 {"tdlgei",	OPTO(2,TOLGE),	OPTO_MASK,   PPC64,	PPCVLE|EXT,	{RA, SI}},
5050 {"tdlnli",	OPTO(2,TOLNL),	OPTO_MASK,   PPC64,	PPCVLE|EXT,	{RA, SI}},
5051 {"tdllei",	OPTO(2,TOLLE),	OPTO_MASK,   PPC64,	PPCVLE|EXT,	{RA, SI}},
5052 {"tdlngi",	OPTO(2,TOLNG),	OPTO_MASK,   PPC64,	PPCVLE|EXT,	{RA, SI}},
5053 {"tdgti",	OPTO(2,TOGT),	OPTO_MASK,   PPC64,	PPCVLE|EXT,	{RA, SI}},
5054 {"tdgei",	OPTO(2,TOGE),	OPTO_MASK,   PPC64,	PPCVLE|EXT,	{RA, SI}},
5055 {"tdnli",	OPTO(2,TONL),	OPTO_MASK,   PPC64,	PPCVLE|EXT,	{RA, SI}},
5056 {"tdlti",	OPTO(2,TOLT),	OPTO_MASK,   PPC64,	PPCVLE|EXT,	{RA, SI}},
5057 {"tdlei",	OPTO(2,TOLE),	OPTO_MASK,   PPC64,	PPCVLE|EXT,	{RA, SI}},
5058 {"tdngi",	OPTO(2,TONG),	OPTO_MASK,   PPC64,	PPCVLE|EXT,	{RA, SI}},
5059 {"tdnei",	OPTO(2,TONE),	OPTO_MASK,   PPC64,	PPCVLE|EXT,	{RA, SI}},
5060 {"tdui",	OPTO(2,TOU),	OPTO_MASK,   PPC64,	PPCVLE|EXT,	{RA, SI}},
5061 {"tdi",		OP(2),		OP_MASK,     PPC64,	PPCVLE,		{TO, RA, SI}},
5063 {"twlgti",	OPTO(3,TOLGT),	OPTO_MASK,   PPCCOM,	PPCVLE|EXT,	{RA, SI}},
5064 {"tlgti",	OPTO(3,TOLGT),	OPTO_MASK,   PWRCOM,	PPCVLE|EXT,	{RA, SI}},
5065 {"twllti",	OPTO(3,TOLLT),	OPTO_MASK,   PPCCOM,	PPCVLE|EXT,	{RA, SI}},
5066 {"tllti",	OPTO(3,TOLLT),	OPTO_MASK,   PWRCOM,	PPCVLE|EXT,	{RA, SI}},
5067 {"tweqi",	OPTO(3,TOEQ),	OPTO_MASK,   PPCCOM,	PPCVLE|EXT,	{RA, SI}},
5068 {"teqi",	OPTO(3,TOEQ),	OPTO_MASK,   PWRCOM,	PPCVLE|EXT,	{RA, SI}},
5069 {"twlgei",	OPTO(3,TOLGE),	OPTO_MASK,   PPCCOM,	PPCVLE|EXT,	{RA, SI}},
5070 {"tlgei",	OPTO(3,TOLGE),	OPTO_MASK,   PWRCOM,	PPCVLE|EXT,	{RA, SI}},
5071 {"twlnli",	OPTO(3,TOLNL),	OPTO_MASK,   PPCCOM,	PPCVLE|EXT,	{RA, SI}},
5072 {"tlnli",	OPTO(3,TOLNL),	OPTO_MASK,   PWRCOM,	PPCVLE|EXT,	{RA, SI}},
5073 {"twllei",	OPTO(3,TOLLE),	OPTO_MASK,   PPCCOM,	PPCVLE|EXT,	{RA, SI}},
5074 {"tllei",	OPTO(3,TOLLE),	OPTO_MASK,   PWRCOM,	PPCVLE|EXT,	{RA, SI}},
5075 {"twlngi",	OPTO(3,TOLNG),	OPTO_MASK,   PPCCOM,	PPCVLE|EXT,	{RA, SI}},
5076 {"tlngi",	OPTO(3,TOLNG),	OPTO_MASK,   PWRCOM,	PPCVLE|EXT,	{RA, SI}},
5077 {"twgti",	OPTO(3,TOGT),	OPTO_MASK,   PPCCOM,	PPCVLE|EXT,	{RA, SI}},
5078 {"tgti",	OPTO(3,TOGT),	OPTO_MASK,   PWRCOM,	PPCVLE|EXT,	{RA, SI}},
5079 {"twgei",	OPTO(3,TOGE),	OPTO_MASK,   PPCCOM,	PPCVLE|EXT,	{RA, SI}},
5080 {"tgei",	OPTO(3,TOGE),	OPTO_MASK,   PWRCOM,	PPCVLE|EXT,	{RA, SI}},
5081 {"twnli",	OPTO(3,TONL),	OPTO_MASK,   PPCCOM,	PPCVLE|EXT,	{RA, SI}},
5082 {"tnli",	OPTO(3,TONL),	OPTO_MASK,   PWRCOM,	PPCVLE|EXT,	{RA, SI}},
5083 {"twlti",	OPTO(3,TOLT),	OPTO_MASK,   PPCCOM,	PPCVLE|EXT,	{RA, SI}},
5084 {"tlti",	OPTO(3,TOLT),	OPTO_MASK,   PWRCOM,	PPCVLE|EXT,	{RA, SI}},
5085 {"twlei",	OPTO(3,TOLE),	OPTO_MASK,   PPCCOM,	PPCVLE|EXT,	{RA, SI}},
5086 {"tlei",	OPTO(3,TOLE),	OPTO_MASK,   PWRCOM,	PPCVLE|EXT,	{RA, SI}},
5087 {"twngi",	OPTO(3,TONG),	OPTO_MASK,   PPCCOM,	PPCVLE|EXT,	{RA, SI}},
5088 {"tngi",	OPTO(3,TONG),	OPTO_MASK,   PWRCOM,	PPCVLE|EXT,	{RA, SI}},
5089 {"twnei",	OPTO(3,TONE),	OPTO_MASK,   PPCCOM,	PPCVLE|EXT,	{RA, SI}},
5090 {"tnei",	OPTO(3,TONE),	OPTO_MASK,   PWRCOM,	PPCVLE|EXT,	{RA, SI}},
5091 {"twui",	OPTO(3,TOU),	OPTO_MASK,   PPCCOM,	PPCVLE|EXT,	{RA, SI}},
5092 {"tui",		OPTO(3,TOU),	OPTO_MASK,   PWRCOM,	PPCVLE|EXT,	{RA, SI}},
5093 {"twi",		OP(3),		OP_MASK,     PPCCOM,	PPCVLE,		{TO, RA, SI}},
5094 {"ti",		OP(3),		OP_MASK,     PWRCOM,	PPCVLE,		{TO, RA, SI}},
5107 {"psq_lx",	XW (4,	 6,0),	XW_MASK,     PPCPS,	0,		{FRT,RA,RB,PSWM,PSQM}},
5113 {"psq_stx",	XW (4,	 7,0),	XW_MASK,     PPCPS,	0,		{FRS,RA,RB,PSWM,PSQM}},
5115 {"vinsbvlx",	VX (4,  15),	VX_MASK,     POWER10,	0,		{VD, RA, VB}},
5116 {"mulhhwu",	XRC(4,	 8,0),	X_MASK,	     MULHW,	0,		{RT, RA, RB}},
5117 {"mulhhwu.",	XRC(4,	 8,1),	X_MASK,	     MULHW,	0,		{RT, RA, RB}},
5126 {"machhwu",	XO (4,	12,0,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5129 {"machhwu.",	XO (4,	12,0,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5168 {"maddhd",	VXA(4,	48),	VXA_MASK,    POWER9,	0,		{RT, RA, RB, RC}},
5170 {"maddhdu",	VXA(4,	49),	VXA_MASK,    POWER9,	0,		{RT, RA, RB, RC}},
5173 {"maddld",	VXA(4,	51),	VXA_MASK,    POWER9,	0,		{RT, RA, RB, RC}},
5199 {"psq_lux",	XW (4,	38,0),	XW_MASK,     PPCPS,	0,		{FRT,RA,RB,PSWM,PSQM}},
5201 {"psq_stux",	XW (4,	39,0),	XW_MASK,     PPCPS,	0,		{FRS,RA,RB,PSWM,PSQM}},
5203 {"vinshvlx",	VX (4,  79),	VX_MASK,     POWER10,	0,		{VD, RA, VB}},
5205 {"mulhhw",	XRC(4,	40,0),	X_MASK,	     MULHW,	0,		{RT, RA, RB}},
5207 {"mulhhw.",	XRC(4,	40,1),	X_MASK,	     MULHW,	0,		{RT, RA, RB}},
5208 {"machhw",	XO (4,	44,0,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5209 {"machhw.",	XO (4,	44,0,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5210 {"nmachhw",	XO (4,	46,0,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5211 {"nmachhw.",	XO (4,	46,0,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5224 {"vinswvlx",	VX (4,  143),	VX_MASK,     POWER10,	0,		{VD, RA, VB}},
5227 {"machhwsu",	XO (4,	76,0,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5228 {"machhwsu.",	XO (4,	76,0,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5240 {"machhws",	XO (4, 108,0,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5241 {"machhws.",	XO (4, 108,0,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5242 {"nmachhws",	XO (4, 110,0,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5243 {"nmachhws.",	XO (4, 110,0,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5255 {"vinsbvrx",	VX (4, 271),	VX_MASK,     POWER10,	0,		{VD, RA, VB}},
5257 {"mulchwu",	XRC(4, 136,0),	X_MASK,	     MULHW,	0,		{RT, RA, RB}},
5259 {"mulchwu.",	XRC(4, 136,1),	X_MASK,	     MULHW,	0,		{RT, RA, RB}},
5260 {"macchwu",	XO (4, 140,0,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5261 {"macchwu.",	XO (4, 140,0,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5272 {"vinshvrx",	VX (4, 335),	VX_MASK,     POWER10,	0,		{VD, RA, VB}},
5273 {"mulchw",	XRC(4, 168,0),	X_MASK,	     MULHW,	0,		{RT, RA, RB}},
5274 {"mulchw.",	XRC(4, 168,1),	X_MASK,	     MULHW,	0,		{RT, RA, RB}},
5275 {"macchw",	XO (4, 172,0,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5276 {"macchw.",	XO (4, 172,0,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5277 {"nmacchw",	XO (4, 174,0,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5278 {"nmacchw.",	XO (4, 174,0,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5290 {"vinswvrx",	VX (4, 399),	VX_MASK,     POWER10,	0,		{VD, RA, VB}},
5291 {"macchwsu",	XO (4, 204,0,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5292 {"macchwsu.",	XO (4, 204,0,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5305 {"macchws",	XO (4, 236,0,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5306 {"macchws.",	XO (4, 236,0,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5307 {"nmacchws",	XO (4, 238,0,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5308 {"nmacchws.",	XO (4, 238,0,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5309 {"evaddw",	VX (4, 512),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5314 {"evsubw",	VX (4, 516),	VX_MASK,     PPCSPE,	EXT,		{RS, RB, RA}},
5315 {"evsubfw",	VX (4, 516),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5321 {"evabs",	VX (4, 520),	VX_MASK,     PPCSPE,	0,		{RS, RA}},
5323 {"evneg",	VX (4, 521),	VX_MASK,     PPCSPE,	0,		{RS, RA}},
5324 {"evextsb",	VX (4, 522),	VX_MASK,     PPCSPE,	0,		{RS, RA}},
5327 {"evextsh",	VX (4, 523),	VX_MASK,     PPCSPE,	0,		{RS, RA}},
5328 {"evrndw",	VX (4, 524),	VX_MASK,     PPCSPE,	0,		{RS, RA}},
5331 {"evcntlzw",	VX (4, 525),	VX_MASK,     PPCSPE,	0,		{RS, RA}},
5332 {"evcntlsw",	VX (4, 526),	VX_MASK,     PPCSPE,	0,		{RS, RA}},
5334 {"vinsblx",	VX (4, 527),	VX_MASK,     POWER10,	0,		{VD, RA, RB}},
5335 {"brinc",	VX (4, 527),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5338 {"evand",	VX (4, 529),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5339 {"evandc",	VX (4, 530),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5341 {"evxor",	VX (4, 534),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5343 {"evor",	VX (4, 535),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5345 {"evnor",	VX (4, 536),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5347 {"eveqv",	VX (4, 537),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5348 {"evorc",	VX (4, 539),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5349 {"evnand",	VX (4, 542),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5350 {"evsrwu",	VX (4, 544),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5351 {"evsrws",	VX (4, 545),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5352 {"evsrwiu",	VX (4, 546),	VX_MASK,     PPCSPE,	0,		{RS, RA, EVUIMM}},
5353 {"evsrwis",	VX (4, 547),	VX_MASK,     PPCSPE,	0,		{RS, RA, EVUIMM}},
5354 {"evslw",	VX (4, 548),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5355 {"evslwi",	VX (4, 550),	VX_MASK,     PPCSPE,	0,		{RS, RA, EVUIMM}},
5356 {"evrlw",	VX (4, 552),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5358 {"evrlwi",	VX (4, 554),	VX_MASK,     PPCSPE,	0,		{RS, RA, EVUIMM}},
5360 {"evmergehi",	VX (4, 556),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5361 {"evmergelo",	VX (4, 557),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5362 {"evmergehilo",	VX (4, 558),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5363 {"evmergelohi",	VX (4, 559),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5364 {"evcmpgtu",	VX (4, 560),	VX_MASK,     PPCSPE,	0,		{CRFD, RA, RB}},
5365 {"evcmpgts",	VX (4, 561),	VX_MASK,     PPCSPE,	0,		{CRFD, RA, RB}},
5366 {"evcmpltu",	VX (4, 562),	VX_MASK,     PPCSPE,	0,		{CRFD, RA, RB}},
5367 {"evcmplts",	VX (4, 563),	VX_MASK,     PPCSPE,	0,		{CRFD, RA, RB}},
5368 {"evcmpeq",	VX (4, 564),	VX_MASK,     PPCSPE,	0,		{CRFD, RA, RB}},
5380 {"vinshlx",	VX (4, 591),	VX_MASK,     POWER10,	0,		{VD, RA, RB}},
5382 {"evsel",	EVSEL(4,79),	EVSEL_MASK,  PPCSPE,	0,		{RS, RA, RB, CRFS}},
5384 {"evfsadd",	VX (4, 640),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5386 {"evfssub",	VX (4, 641),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5387 {"evfsmadd",	VX (4, 642),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5389 {"evfsmsub",	VX (4, 643),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5390 {"evfsabs",	VX (4, 644),	VX_MASK,     PPCSPE,	0,		{RS, RA}},
5392 {"evfsnabs",	VX (4, 645),	VX_MASK,     PPCSPE,	0,		{RS, RA}},
5393 {"evfsneg",	VX (4, 646),	VX_MASK,     PPCSPE,	0,		{RS, RA}},
5396 {"evfssqrt",	VX_RB_CONST(4, 647, 0),  VX_RB_CONST_MASK,	PPCEFS2,	0,		{RD, RA}},
5398 {"evfsmul",	VX (4, 648),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5400 {"evfsdiv",	VX (4, 649),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5401 {"evfsnmadd",	VX (4, 650),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5404 {"evfsnmsub",	VX (4, 651),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5405 {"evfscmpgt",	VX (4, 652),	VX_MASK,     PPCSPE,	0,		{CRFD, RA, RB}},
5408 {"evfscmplt",	VX (4, 653),	VX_MASK,     PPCSPE,	0,		{CRFD, RA, RB}},
5409 {"evfscmpeq",	VX (4, 654),	VX_MASK,     PPCSPE,	0,		{CRFD, RA, RB}},
5411 {"vinswlx",	VX (4, 655),	VX_MASK,     POWER10,	0,		{VD, RA, RB}},
5423 {"put",		APU(4, 332,0),	APU_RT_MASK, PPC405,	0,		{RA, FSL}},
5425 {"evfststgt",	VX (4, 668),	VX_MASK,     PPCSPE,	0,		{CRFD, RA, RB}},
5426 {"evfststlt",	VX (4, 669),	VX_MASK,     PPCSPE,	0,		{CRFD, RA, RB}},
5427 {"evfststeq",	VX (4, 670),	VX_MASK,     PPCSPE,	0,		{CRFD, RA, RB}},
5428 {"evfsmax",	VX (4, 672),	VX_MASK,     PPCEFS2,	0,		{RD, RA, RB}},
5429 {"evfsmin",	VX (4, 673),	VX_MASK,     PPCEFS2,	0,		{RD, RA, RB}},
5430 {"evfsaddsub",	VX (4, 674),	VX_MASK,     PPCEFS2,	0,		{RD, RA, RB}},
5431 {"evfssubadd",	VX (4, 675),	VX_MASK,     PPCEFS2,	0,		{RD, RA, RB}},
5432 RA, RB}},
5433 {"evfsdiff",	VX (4, 677),	VX_MASK,     PPCEFS2,	0,		{RD, RA, RB}},
5434 {"evfssumdiff",	VX (4, 678),	VX_MASK,     PPCEFS2,	0,		{RD, RA, RB}},
5435 {"evfsdiffsum",	VX (4, 679),	VX_MASK,     PPCEFS2,	0,		{RD, RA, RB}},
5436 {"evfsaddx",	VX (4, 680),	VX_MASK,     PPCEFS2,	0,		{RD, RA, RB}},
5437 {"evfssubx",	VX (4, 681),	VX_MASK,     PPCEFS2,	0,		{RD, RA, RB}},
5438 {"evfsaddsubx",	VX (4, 682),	VX_MASK,     PPCEFS2,	0,		{RD, RA, RB}},
5439 {"evfssubaddx",	VX (4, 683),	VX_MASK,     PPCEFS2,	0,		{RD, RA, RB}},
5440 {"evfsmulx",	VX (4, 684),	VX_MASK,     PPCEFS2,	0,		{RD, RA, RB}},
5441 {"evfsmule",	VX (4, 686),	VX_MASK,     PPCEFS2,	0,		{RD, RA, RB}},
5442 {"evfsmulo",	VX (4, 687),	VX_MASK,     PPCEFS2,	0,		{RD, RA, RB}},
5443 {"efsmax",	VX (4, 688),	VX_MASK,     PPCEFS2,	0,		{RD, RA, RB}},
5444 {"efsmin",	VX (4, 689),	VX_MASK,     PPCEFS2,	0,		{RD, RA, RB}},
5445 {"efdmax",	VX (4, 696),	VX_MASK,     PPCEFS2,	0,		{RD, RA, RB}},
5446 {"cput",	APU(4, 348,0),	APU_RT_MASK, PPC405,	0,		{RA, FSL}},
5447 {"efdmin",	VX (4, 697),	VX_MASK,     PPCEFS2,	0,		{RD, RA, RB}},
5448 {"efsadd",	VX (4, 704),	VX_MASK,     PPCEFS,	0,		{RS, RA, RB}},
5449 {"evsadd",	VX (4, 704),	VX_MASK,     PPCEFS,	0,		{RS, RA, RB}},
5450 {"efssub",	VX (4, 705),	VX_MASK,     PPCEFS,	0,		{RS, RA, RB}},
5451 {"evssub",	VX (4, 705),	VX_MASK,     PPCEFS,	0,		{RS, RA, RB}},
5452 {"efsmadd",	VX (4, 706),	VX_MASK,     PPCEFS2,	0,		{RS, RA, RB}},
5454 {"efsmsub",	VX (4, 707),	VX_MASK,     PPCEFS2,	0,		{RS, RA, RB}},
5455 {"efsabs",	VX (4, 708),	VX_MASK,     PPCEFS,	0,		{RS, RA}},
5456 {"evsabs",	VX (4, 708),	VX_MASK,     PPCEFS,	0,		{RS, RA}},
5458 {"efsnabs",	VX (4, 709),	VX_MASK,     PPCEFS,	0,		{RS, RA}},
5459 {"evsnabs",	VX (4, 709),	VX_MASK,     PPCEFS,	0,		{RS, RA}},
5460 {"efsneg",	VX (4, 710),	VX_MASK,     PPCEFS,	0,		{RS, RA}},
5461 {"evsneg",	VX (4, 710),	VX_MASK,     PPCEFS,	0,		{RS, RA}},
5463 {"efssqrt",	VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK,PPCEFS2, 0,	{RD, RA}},
5466 {"efsmul",	VX (4, 712),	VX_MASK,     PPCEFS,	0,		{RS, RA, RB}},
5467 {"evsmul",	VX (4, 712),	VX_MASK,     PPCEFS,	0,		{RS, RA, RB}},
5469 {"efsdiv",	VX (4, 713),	VX_MASK,     PPCEFS,	0,		{RS, RA, RB}},
5470 {"evsdiv",	VX (4, 713),	VX_MASK,     PPCEFS,	0,		{RS, RA, RB}},
5471 {"efsnmadd",	VX (4, 714),	VX_MASK,     PPCEFS2,	0,		{RS, RA, RB}},
5474 {"efsnmsub",	VX (4, 715),	VX_MASK,     PPCEFS2,	0,		{RS, RA, RB}},
5475 {"efscmpgt",	VX (4, 716),	VX_MASK,     PPCEFS,	0,		{CRFD, RA, RB}},
5476 {"evscmpgt",	VX (4, 716),	VX_MASK,     PPCEFS,	0,		{CRFD, RA, RB}},
5478 {"efscmplt",	VX (4, 717),	VX_MASK,     PPCEFS,	0,		{CRFD, RA, RB}},
5479 {"evsgmplt",	VX (4, 717),	VX_MASK,     PPCEFS,	0,		{CRFD, RA, RB}},
5480 {"efscmpeq",	VX (4, 718),	VX_MASK,     PPCEFS,	0,		{CRFD, RA, RB}},
5481 {"evsgmpeq",	VX (4, 718),	VX_MASK,     PPCEFS,	0,		{CRFD, RA, RB}},
5483 {"vinsdlx",	VX (4, 719),	VX_MASK,     POWER10,	0,		{VD, RA, RB}},
5505 {"nput",	APU(4, 364,0),	APU_RT_MASK, PPC405,	0,		{RA, FSL}},
5508 {"efststgt",	VX (4, 732),	VX_MASK,     PPCEFS,	0,		{CRFD, RA, RB}},
5509 {"evststgt",	VX (4, 732),	VX_MASK,     PPCEFS,	0,		{CRFD, RA, RB}},
5510 {"efststlt",	VX (4, 733),	VX_MASK,     PPCEFS,	0,		{CRFD, RA, RB}},
5511 {"evststlt",	VX (4, 733),	VX_MASK,     PPCEFS,	0,		{CRFD, RA, RB}},
5512 {"efststeq",	VX (4, 734),	VX_MASK,     PPCEFS,	0,		{CRFD, RA, RB}},
5513 {"evststeq",	VX (4, 734),	VX_MASK,     PPCEFS,	0,		{CRFD, RA, RB}},
5514 {"efdadd",	VX (4, 736),	VX_MASK,     PPCEFS,	0,		{RS, RA, RB}},
5515 {"efdsub",	VX (4, 737),	VX_MASK,     PPCEFS,	0,		{RS, RA, RB}},
5516 {"efdmadd",	VX (4, 738),	VX_MASK,     PPCEFS2, 	E500|E500MC,	{RD, RA, RB}},
5518 {"efdmsub",	VX (4, 739),	VX_MASK,     PPCEFS2, 	E500|E500MC,	{RD, RA, RB}},
5520 {"efdabs",	VX (4, 740),	VX_MASK,     PPCEFS,	0,		{RS, RA}},
5521 {"efdnabs",	VX (4, 741),	VX_MASK,     PPCEFS,	0,		{RS, RA}},
5522 {"efdneg",	VX (4, 742),	VX_MASK,     PPCEFS,	0,		{RS, RA}},
5523 {"efdsqrt",	VX_RB_CONST(4, 743, 0), VX_RB_CONST_MASK, PPCEFS2, 0,	{RD, RA}},
5524 {"efdmul",	VX (4, 744),	VX_MASK,     PPCEFS,	0,		{RS, RA, RB}},
5525 {"efddiv",	VX (4, 745),	VX_MASK,     PPCEFS,	0,		{RS, RA, RB}},
5526 {"efdnmadd",	VX (4, 746),	VX_MASK,     PPCEFS2, 	E500|E500MC,	{RD, RA, RB}},
5528 {"efdnmsub",	VX (4, 747),	VX_MASK,     PPCEFS2, 	E500|E500MC,	{RD, RA, RB}},
5530 {"efdcmpgt",	VX (4, 748),	VX_MASK,     PPCEFS,	0,		{CRFD, RA, RB}},
5531 {"efdcmplt",	VX (4, 749),	VX_MASK,     PPCEFS,	0,		{CRFD, RA, RB}},
5532 {"efdcmpeq",	VX (4, 750),	VX_MASK,     PPCEFS,	0,		{CRFD, RA, RB}},
5548 {"ncput",	APU(4, 380,0),	APU_RT_MASK, PPC405,	0,		{RA, FSL}},
5551 {"efdtstgt",	VX (4, 764),	VX_MASK,     PPCEFS,	0,		{CRFD, RA, RB}},
5552 {"efdtstlt",	VX (4, 765),	VX_MASK,     PPCEFS,	0,		{CRFD, RA, RB}},
5553 {"efdtsteq",	VX (4, 766),	VX_MASK,     PPCEFS,	0,		{CRFD, RA, RB}},
5554 {"evlddx",	VX (4, 768),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5556 {"evldd",	VX (4, 769),	VX_MASK,     PPCSPE,	0,		{RS, EVUIMM_8, RA}},
5557 {"evldwx",	VX (4, 770),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5559 {"evldw",	VX (4, 771),	VX_MASK,     PPCSPE,	0,		{RS, EVUIMM_8, RA}},
5560 {"evldhx",	VX (4, 772),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5563 {"evldh",	VX (4, 773),	VX_MASK,     PPCSPE,	0,		{RS, EVUIMM_8, RA}},
5565 {"evlhhesplatx",VX (4, 776),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5567 {"evlhhesplat",	VX (4, 777),	VX_MASK,     PPCSPE,	0,		{RS, EVUIMM_2, RA}},
5571 {"evlhhousplatx",VX(4, 780),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5574 {"evlhhousplat",VX (4, 781),	VX_MASK,     PPCSPE,	0,		{RS, EVUIMM_2, RA}},
5575 {"evlhhossplatx",VX(4, 782),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5577 {"vinsbrx",	VX (4, 783),	VX_MASK,     POWER10,	0,		{VD, RA, RB}},
5578 {"evlhhossplat",VX (4, 783),	VX_MASK,     PPCSPE,	0,		{RS, EVUIMM_2, RA}},
5579 {"mullhwu",	XRC(4, 392,0),	X_MASK,	     MULHW,	0,		{RT, RA, RB}},
5580 {"evlwhex",	VX (4, 784),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5581 {"mullhwu.",	XRC(4, 392,1),	X_MASK,	     MULHW,	0,		{RT, RA, RB}},
5582 {"evlwhe",	VX (4, 785),	VX_MASK,     PPCSPE,	0,		{RS, EVUIMM_4, RA}},
5583 {"evlwhoux",	VX (4, 788),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5584 {"evlwhou",	VX (4, 789),	VX_MASK,     PPCSPE,	0,		{RS, EVUIMM_4, RA}},
5585 {"evlwhosx",	VX (4, 790),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5586 {"evlwhos",	VX (4, 791),	VX_MASK,     PPCSPE,	0,		{RS, EVUIMM_4, RA}},
5587 {"maclhwu",	XO (4, 396,0,0),XO_MASK,     MULHW,	0,		{RT, RA, RB}},
5588 {"evlwwsplatx",	VX (4, 792),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5589 {"maclhwu.",	XO (4, 396,0,1),XO_MASK,     MULHW,	0,		{RT, RA, RB}},
5590 {"evlwwsplat",	VX (4, 793),	VX_MASK,     PPCSPE,	0,		{RS, EVUIMM_4, RA}},
5591 {"evlwhsplatx",	VX (4, 796),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5592 {"evlwhsplat",	VX (4, 797),	VX_MASK,     PPCSPE,	0,		{RS, EVUIMM_4, RA}},
5593 {"evstddx",	VX (4, 800),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5594 {"evstdd",	VX (4, 801),	VX_MASK,     PPCSPE,	0,		{RS, EVUIMM_8, RA}},
5595 {"evstdwx",	VX (4, 802),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5596 {"evstdw",	VX (4, 803),	VX_MASK,     PPCSPE,	0,		{RS, EVUIMM_8, RA}},
5597 {"evstdhx",	VX (4, 804),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5598 {"evstdh",	VX (4, 805),	VX_MASK,     PPCSPE,	0,		{RS, EVUIMM_8, RA}},
5599 {"evstwhex",	VX (4, 816),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5600 {"evstwhe",	VX (4, 817),	VX_MASK,     PPCSPE,	0,		{RS, EVUIMM_4, RA}},
5601 {"evstwhox",	VX (4, 820),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5602 {"evstwho",	VX (4, 821),	VX_MASK,     PPCSPE,	0,		{RS, EVUIMM_4, RA}},
5603 {"evstwwex",	VX (4, 824),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5604 {"evstwwe",	VX (4, 825),	VX_MASK,     PPCSPE,	0,		{RS, EVUIMM_4, RA}},
5605 {"evstwwox",	VX (4, 828),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5606 {"evstwwo",	VX (4, 829),	VX_MASK,     PPCSPE,	0,		{RS, EVUIMM_4, RA}},
5618 {"vinshrx",	VX (4, 847),	VX_MASK,     POWER10,	0,		{VD, RA, RB}},
5619 {"mullhw",	XRC(4, 424,0),	X_MASK,	     MULHW,	0,		{RT, RA, RB}},
5620 {"mullhw.",	XRC(4, 424,1),	X_MASK,	     MULHW,	0,		{RT, RA, RB}},
5621 {"maclhw",	XO (4, 428,0,0),XO_MASK,     MULHW,	0,		{RT, RA, RB}},
5622 {"maclhw.",	XO (4, 428,0,1),XO_MASK,     MULHW,	0,		{RT, RA, RB}},
5623 {"nmaclhw",	XO (4, 430,0,0),XO_MASK,     MULHW,	0,		{RT, RA, RB}},
5624 {"nmaclhw.",	XO (4, 430,0,1),XO_MASK,     MULHW,	0,		{RT, RA, RB}},
5637 {"vinswrx",	VX (4, 911),	VX_MASK,     POWER10,	0,		{VD, RA, RB}},
5638 {"maclhwsu",	XO (4, 460,0,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5639 {"maclhwsu.",	XO (4, 460,0,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5651 {"vinsdrx",	VX (4, 975),	VX_MASK,     POWER10,	0,		{VD, RA, RB}},
5652 {"maclhws",	XO (4, 492,0,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5653 {"maclhws.",	XO (4, 492,0,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5654 {"nmaclhws",	XO (4, 494,0,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5655 {"nmaclhws.",	XO (4, 494,0,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5660 {"evmhessf",	VX (4,1027),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5666 {"evmhossf",	VX (4,1031),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5668 {"evmheumi",	VX (4,1032),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5669 {"evmhesmi",	VX (4,1033),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5671 {"evmhesmf",	VX (4,1035),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5672 {"evmhoumi",	VX (4,1036),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5678 {"evmhosmi",	VX (4,1037),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5679 {"evmhosmf",	VX (4,1039),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5680 {"machhwuo",	XO (4,	12,1,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5681 {"machhwuo.",	XO (4,	12,1,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5684 {"evmhessfa",	VX (4,1059),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5685 {"evmhossfa",	VX (4,1063),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5686 {"evmheumia",	VX (4,1064),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5687 {"evmhesmia",	VX (4,1065),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5688 {"evmhesmfa",	VX (4,1067),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5689 {"evmhoumia",	VX (4,1068),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5690 {"evmhosmia",	VX (4,1069),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5691 {"evmhosmfa",	VX (4,1071),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5695 {"evmwlssf",	VX (4,1091),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5702 {"evmwhssf",	VX (4,1095),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5704 {"evmwlumi",	VX (4,1096),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5706 {"evmwlsmf",	VX (4,1099),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5707 {"evmwhumi",	VX (4,1100),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5709 {"evmwhsmi",	VX (4,1101),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5711 {"evmwhsmf",	VX (4,1103),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5712 {"evmwssf",	VX (4,1107),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5713 {"machhwo",	XO (4,	44,1,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5714 {"evmwumi",	VX (4,1112),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5715 {"machhwo.",	XO (4,	44,1,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5716 {"evmwsmi",	VX (4,1113),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5717 {"evmwsmf",	VX (4,1115),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5718 {"nmachhwo",	XO (4,	46,1,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5719 {"nmachhwo.",	XO (4,	46,1,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5722 {"evmwlssfa",	VX (4,1123),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5723 {"evmwhssfa",	VX (4,1127),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5724 {"evmwlumia",	VX (4,1128),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5725 {"evmwlsmfa",	VX (4,1131),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5726 {"evmwhumia",	VX (4,1132),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5727 {"evmwhsmia",	VX (4,1133),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5728 {"evmwhsmfa",	VX (4,1135),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5729 {"evmwssfa",	VX (4,1139),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5730 {"evmwumia",	VX (4,1144),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5731 {"evmwsmia",	VX (4,1145),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5732 {"evmwsmfa",	VX (4,1147),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5744 {"machhwsuo",	XO (4,	76,1,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5745 {"machhwsuo.",	XO (4,	76,1,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5749 {"evaddusiaaw",	VX (4,1216),	VX_MASK,     PPCSPE,	0,		{RS, RA}},
5751 {"evaddssiaaw",	VX (4,1217),	VX_MASK,     PPCSPE,	0,		{RS, RA}},
5752 {"evsubfusiaaw",VX (4,1218),	VX_MASK,     PPCSPE,	0,		{RS, RA}},
5753 {"evsubfssiaaw",VX (4,1219),	VX_MASK,     PPCSPE,	0,		{RS, RA}},
5754 {"evmra",	VX (4,1220),	VX_MASK,     PPCSPE,	0,		{RS, RA}},
5756 {"evdivws",	VX (4,1222),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5761 {"evdivwu",	VX (4,1223),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5763 {"evaddumiaaw",	VX (4,1224),	VX_MASK,     PPCSPE,	0,		{RS, RA}},
5764 {"evaddsmiaaw",	VX (4,1225),	VX_MASK,     PPCSPE,	0,		{RS, RA}},
5765 {"evsubfumiaaw",VX (4,1226),	VX_MASK,     PPCSPE,	0,		{RS, RA}},
5766 {"evsubfsmiaaw",VX (4,1227),	VX_MASK,     PPCSPE,	0,		{RS, RA}},
5769 {"machhwso",	XO (4, 108,1,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5770 {"machhwso.",	XO (4, 108,1,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5771 {"nmachhwso",	XO (4, 110,1,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5772 {"nmachhwso.",	XO (4, 110,1,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5776 {"evmheusiaaw",	VX (4,1280),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5778 {"evmhessiaaw",	VX (4,1281),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5780 {"evmhessfaaw",	VX (4,1283),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5781 {"evmhousiaaw",	VX (4,1284),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5784 {"evmhossiaaw",	VX (4,1285),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5788 {"evmhossfaaw",	VX (4,1287),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5789 {"evmheumiaaw",	VX (4,1288),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5792 {"evmhesmiaaw",	VX (4,1289),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5793 {"evmhesmfaaw",	VX (4,1291),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5795 {"evmhoumiaaw",	VX (4,1292),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5796 {"evmhosmiaaw",	VX (4,1293),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5797 {"evmhosmfaaw",	VX (4,1295),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5798 {"macchwuo",	XO (4, 140,1,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5799 {"macchwuo.",	XO (4, 140,1,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5800 {"evmhegumiaa",	VX (4,1320),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5801 {"evmhegsmiaa",	VX (4,1321),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5802 {"evmhegsmfaa",	VX (4,1323),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5803 {"evmhogumiaa",	VX (4,1324),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5804 {"evmhogsmiaa",	VX (4,1325),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5805 {"evmhogsmfaa",	VX (4,1327),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5807 {"evmwlusiaaw",	VX (4,1344),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5809 {"evmwlssiaaw",	VX (4,1345),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5811 {"evmwlssfaaw",	VX (4,1347),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5812 {"evmwhusiaa",	VX (4,1348),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5814 {"evmwhssmaa",	VX (4,1349),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5818 {"evmwhssfaa",	VX (4,1351),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5820 {"evmwlumiaaw",	VX (4,1352),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5822 {"evmwlsmiaaw",	VX (4,1353),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5823 {"evmwlsmfaaw",	VX (4,1355),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5824 {"evmwhumiaa",	VX (4,1356),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5827 {"evmwhsmiaa",	VX (4,1357),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5829 {"evmwhsmfaa",	VX (4,1359),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5830 {"evmwssfaa",	VX (4,1363),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5831 {"macchwo",	XO (4, 172,1,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5832 {"evmwumiaa",	VX (4,1368),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5833 {"macchwo.",	XO (4, 172,1,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5834 {"evmwsmiaa",	VX (4,1369),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5835 {"evmwsmfaa",	VX (4,1371),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5836 {"nmacchwo",	XO (4, 174,1,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5837 {"nmacchwo.",	XO (4, 174,1,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5838 {"evmwhgumiaa",	VX (4,1380),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5839 {"evmwhgsmiaa",	VX (4,1381),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5840 {"evmwhgssfaa",	VX (4,1383),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5841 {"evmwhgsmfaa",	VX (4,1391),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5842 {"evmheusianw",	VX (4,1408),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5844 {"evmhessianw",	VX (4,1409),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5853 {"evmhessfanw",	VX (4,1411),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5855 {"evmhousianw",	VX (4,1412),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5856 {"evmhossianw",	VX (4,1413),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5860 {"evmhossfanw",	VX (4,1415),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5861 {"evmheumianw",	VX (4,1416),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5862 {"evmhesmianw",	VX (4,1417),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5863 {"evmhesmfanw",	VX (4,1419),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5864 {"evmhoumianw",	VX (4,1420),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5866 {"evmhosmianw",	VX (4,1421),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5867 {"evmhosmfanw",	VX (4,1423),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5868 {"macchwsuo",	XO (4, 204,1,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5869 {"macchwsuo.",	XO (4, 204,1,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5870 {"evmhegumian",	VX (4,1448),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5871 {"evmhegsmian",	VX (4,1449),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5872 {"evmhegsmfan",	VX (4,1451),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5873 {"evmhogumian",	VX (4,1452),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5874 {"evmhogsmian",	VX (4,1453),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5875 {"evmhogsmfan",	VX (4,1455),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5876 {"evmwlusianw",	VX (4,1472),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5878 {"evmwlssianw",	VX (4,1473),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5879 {"evmwlssfanw",	VX (4,1475),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5880 {"evmwhusian",	VX (4,1476),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5882 {"evmwhssian",	VX (4,1477),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5887 {"evmwhssfan",	VX (4,1479),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5889 {"evmwlumianw",	VX (4,1480),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5890 {"evmwlsmianw",	VX (4,1481),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5891 {"evmwlsmfanw",	VX (4,1483),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5892 {"evmwhumian",	VX (4,1484),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5895 {"evmwhsmian",	VX (4,1485),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5897 {"evmwhsmfan",	VX (4,1487),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5898 {"evmwssfan",	VX (4,1491),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5899 {"macchwso",	XO (4, 236,1,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5900 {"evmwumian",	VX (4,1496),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5901 {"macchwso.",	XO (4, 236,1,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5902 {"evmwsmian",	VX (4,1497),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5903 {"evmwsmfan",	VX (4,1499),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
5904 {"evmwhgumian",	VX (4,1508),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5905 {"evmwhgsmian",	VX (4,1509),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5906 {"evmwhgssfan",	VX (4,1511),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5907 {"evmwhgsmfan",	VX (4,1519),	VX_MASK,     PPCSPE,	0,		{RD, RA, RB}},
5908 {"nmacchwso",	XO (4, 238,1,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5909 {"nmacchwso.",	XO (4, 238,1,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5934 {"vextublx",	VX (4,1549),	VX_MASK,     PPCVEC3,	0,		{RT, RA, VB}},
5962 {"vextuhlx",	VX (4,1613),	VX_MASK,     PPCVEC3,	0,		{RT, RA, VB}},
5974 {"vextuwlx",	VX (4,1677),	VX_MASK,     PPCVEC3,	0,		{RT, RA, VB}},
5992 {"vextubrx",	VX (4,1805),	VX_MASK,     PPCVEC3,	0,		{RT, RA, VB}},
5993 {"maclhwuo",	XO (4, 396,1,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
5994 {"maclhwuo.",	XO (4, 396,1,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
6000 {"vextuhrx",	VX (4,1869),	VX_MASK,     PPCVEC3,	0,		{RT, RA, VB}},
6003 {"maclhwo",	XO (4, 428,1,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
6004 {"maclhwo.",	XO (4, 428,1,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
6005 {"nmaclhwo",	XO (4, 430,1,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
6006 {"nmaclhwo.",	XO (4, 430,1,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
6018 {"vextuwrx",	VX (4,1933),	VX_MASK,     PPCVEC3,	0,		{RT, RA, VB}},
6019 {"maclhwsuo",	XO (4, 460,1,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
6020 {"maclhwsuo.",	XO (4, 460,1,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
6029 {"maclhwso",	XO (4, 492,1,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
6030 {"maclhwso.",	XO (4, 492,1,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
6031 {"nmaclhwso",	XO (4, 494,1,0), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
6032 {"nmaclhwso.",	XO (4, 494,1,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
6033 {"dcbz_l",	X  (4,1014),	XRT_MASK,    PPCPS,	0,		{RA, RB}},
6038 {"mulli",	OP(7),		OP_MASK,     PPCCOM,	PPCVLE,		{RT, RA, SI}},
6039 {"muli",	OP(7),		OP_MASK,     PWRCOM,	PPCVLE,		{RT, RA, SI}},
6041 {"subfic",	OP(8),		OP_MASK,     PPCCOM,	PPCVLE,		{RT, RA, SI}},
6042 {"sfi",		OP(8),		OP_MASK,     PWRCOM,	PPCVLE,		{RT, RA, SI}},
6044 {"dozi",	OP(9),		OP_MASK,     M601,	PPCVLE,		{RT, RA, SI}},
6046 {"cmplwi",	OPL(10,0),	OPL_MASK,    PPCCOM,	PPCVLE|EXT,	{OBF, RA, UISIGNOPT}},
6047 {"cmpldi",	OPL(10,1),	OPL_MASK,    PPC64,	PPCVLE|EXT,	{OBF, RA, UISIGNOPT}},
6048 {"cmpli",	OP(10),		OP_MASK,     PPC,	PPCVLE,		{BF, L32OPT, RA, UISIGNOPT}},
6049 {"cmpli",	OP(10),		OP_MASK,     PWRCOM,	PPC|PPCVLE,	{BF, RA, UISIGNOPT}},
6051 {"cmpwi",	OPL(11,0),	OPL_MASK,    PPCCOM,	PPCVLE|EXT,	{OBF, RA, SI}},
6052 {"cmpdi",	OPL(11,1),	OPL_MASK,    PPC64,	PPCVLE|EXT,	{OBF, RA, SI}},
6053 {"cmpi",	OP(11),		OP_MASK,     PPC,	PPCVLE,		{BF, L32OPT, RA, SI}},
6054 {"cmpi",	OP(11),		OP_MASK,     PWRCOM,	PPC|PPCVLE,	{BF, RA, SI}},
6056 {"addic",	OP(12),		OP_MASK,     PPCCOM,	PPCVLE,		{RT, RA, SI}},
6057 {"ai",		OP(12),		OP_MASK,     PWRCOM,	PPCVLE,		{RT, RA, SI}},
6058 {"subic",	OP(12),		OP_MASK,     PPCCOM,	PPCVLE|EXT,	{RT, RA, NSI}},
6060 {"addic.",	OP(13),		OP_MASK,     PPCCOM,	PPCVLE,		{RT, RA, SI}},
6061 {"ai.",		OP(13),		OP_MASK,     PWRCOM,	PPCVLE,		{RT, RA, SI}},
6062 {"subic.",	OP(13),		OP_MASK,     PPCCOM,	PPCVLE|EXT,	{RT, RA, NSI}},
6914 {"rlwimi",	M(20,0),	M_MASK,	     PPCCOM,	PPCVLE,		{RA, RS, SH, MBE, ME}},
6915 {"inslwi",	M(20,0),	M_MASK,	     PPCCOM,	PPCVLE|EXT,	{RA, RS, ILWn, ILWb}},
6916 {"insrwi",	M(20,0),	M_MASK,	     PPCCOM,	PPCVLE|EXT,	{RA, RS, IRWn, IRWb}},
6917 {"rlimi",	M(20,0),	M_MASK,	     PWRCOM,	PPCVLE,		{RA, RS, SH, MBE, ME}},
6919 {"rlwimi.",	M(20,1),	M_MASK,	     PPCCOM,	PPCVLE,		{RA, RS, SH, MBE, ME}},
6920 {"inslwi.",	M(20,1),	M_MASK,	     PPCCOM,	PPCVLE|EXT,	{RA, RS, ILWn, ILWb}},
6921 {"insrwi.",	M(20,1),	M_MASK,	     PPCCOM,	PPCVLE|EXT,	{RA, RS, IRWn, IRWb}},
6922 {"rlimi.",	M(20,1),	M_MASK,	     PWRCOM,	PPCVLE,		{RA, RS, SH, MBE, ME}},
6924 {"rotlwi",	MME(21,31,0),	MMBME_MASK,  PPCCOM,	PPCVLE|EXT,	{RA, RS, SH}},
6925 {"rotrwi",	MME(21,31,0),	MMBME_MASK,  PPCCOM,	PPCVLE|EXT,	{RA, RS, RRWn}},
6926 {"clrlwi",	MME(21,31,0),	MSHME_MASK,  PPCCOM,	PPCVLE|EXT,	{RA, RS, MB}},
6927 {"clrrwi",	M(21,0),	MSHMB_MASK,  PPCCOM,	PPCVLE|EXT,	{RA, RS, CRWn}},
6928 {"slwi",	M(21,0),	MMB_MASK,    PPCCOM,	PPCVLE|EXT,	{RA, RS, SLWn}},
6929 {"srwi",	MME(21,31,0),	MME_MASK,    PPCCOM,	PPCVLE|EXT,	{RA, RS, SRWn}},
6930 {"rlwinm",	M(21,0),	M_MASK,	     PPCCOM,	PPCVLE,		{RA, RS, SH, MBE, ME}},
6931 {"extlwi",	M(21,0),	MMB_MASK,    PPCCOM,	PPCVLE|EXT,	{RA, RS, ELWn, SH}},
6932 {"extrwi",	MME(21,31,0),	MME_MASK,    PPCCOM,	PPCVLE|EXT,	{RA, RS, ERWn, ERWb}},
6933 {"clrlslwi",	M(21,0),	M_MASK,	     PPCCOM,	PPCVLE|EXT,	{RA, RS, CSLWb, CSLWn}},
6934 {"sli",		M(21,0),	MMB_MASK,    PWRCOM,	PPCVLE|EXT,	{RA, RS, SLWn}},
6935 {"sri",		MME(21,31,0),	MME_MASK,    PWRCOM,	PPCVLE|EXT,	{RA, RS, SRWn}},
6936 {"rlinm",	M(21,0),	M_MASK,	     PWRCOM,	PPCVLE,		{RA, RS, SH, MBE, ME}},
6937 {"rotlwi.",	MME(21,31,1),	MMBME_MASK,  PPCCOM,	PPCVLE|EXT,	{RA, RS, SH}},
6938 {"rotrwi.",	MME(21,31,1),	MMBME_MASK,  PPCCOM,	PPCVLE|EXT,	{RA, RS, RRWn}},
6939 {"clrlwi.",	MME(21,31,1),	MSHME_MASK,  PPCCOM,	PPCVLE|EXT,	{RA, RS, MB}},
6940 {"clrrwi.",	M(21,1),	MSHMB_MASK,  PPCCOM,	PPCVLE|EXT,	{RA, RS, CRWn}},
6941 {"slwi.",	M(21,1),	MMB_MASK,    PPCCOM,	PPCVLE|EXT,	{RA, RS, SLWn}},
6942 {"srwi.",	MME(21,31,1),	MME_MASK,    PPCCOM,	PPCVLE|EXT,	{RA, RS, SRWn}},
6943 {"rlwinm.",	M(21,1),	M_MASK,	     PPCCOM,	PPCVLE,		{RA, RS, SH, MBE, ME}},
6944 {"extlwi.",	M(21,1),	MMB_MASK,    PPCCOM,	PPCVLE|EXT,	{RA, RS, ELWn, SH}},
6945 {"extrwi.",	MME(21,31,1),	MME_MASK,    PPCCOM,	PPCVLE|EXT,	{RA, RS, ERWn, ERWb}},
6946 {"clrlslwi.",	M(21,1),	M_MASK,	     PPCCOM,	PPCVLE|EXT,	{RA, RS, CSLWb, CSLWn}},
6947 {"sli.",	M(21,1),	MMB_MASK,    PWRCOM,	PPCVLE|EXT,	{RA, RS, SLWn}},
6948 {"sri.",	MME(21,31,1),	MME_MASK,    PWRCOM,	PPCVLE|EXT,	{RA, RS, SRWn}},
6949 {"rlinm.",	M(21,1),	M_MASK,	     PWRCOM,	PPCVLE,		{RA, RS, SH, MBE, ME}},
6951 {"rlmi",	M(22,0),	M_MASK,	     M601,	PPCVLE,		{RA, RS, RB, MBE, ME}},
6952 {"rlmi.",	M(22,1),	M_MASK,	     M601,	PPCVLE,		{RA, RS, RB, MBE, ME}},
6959 {"setvl",	SVL(22,27,0),	SVL_MASK,	SVP64,	PPCVLE,	{RT, RA, SVi, vf, vs, ms}},
6960 {"setvl.",	SVL(22,27,1),	SVL_MASK,	SVP64,	PPCVLE,	{RT, RA, SVi, vf, vs, ms}},
6966 {"rotlw",	MME(23,31,0),	MMBME_MASK,  PPCCOM,	PPCVLE|EXT,	{RA, RS, RB}},
6967 {"rlwnm",	M(23,0),	M_MASK,	     PPCCOM,	PPCVLE,		{RA, RS, RB, MBE, ME}},
6968 {"rlnm",	M(23,0),	M_MASK,	     PWRCOM,	PPCVLE,		{RA, RS, RB, MBE, ME}},
6969 {"rotlw.",	MME(23,31,1),	MMBME_MASK,  PPCCOM,	PPCVLE|EXT,	{RA, RS, RB}},
6970 {"rlwnm.",	M(23,1),	M_MASK,	     PPCCOM,	PPCVLE,		{RA, RS, RB, MBE, ME}},
6971 {"rlnm.",	M(23,1),	M_MASK,	     PWRCOM,	PPCVLE,		{RA, RS, RB, MBE, ME}},
6975 {"ori",		OP(24),		OP_MASK,     PPCCOM,	PPCVLE,		{RA, RS, UI}},
6976 {"oril",	OP(24),		OP_MASK,     PWRCOM,	PPCVLE,		{RA, RS, UI}},
6978 {"oris",	OP(25),		OP_MASK,     PPCCOM,	PPCVLE,		{RA, RS, UI}},
6979 {"oriu",	OP(25),		OP_MASK,     PWRCOM,	PPCVLE,		{RA, RS, UI}},
6982 {"xori",	OP(26),		OP_MASK,     PPCCOM,	PPCVLE,		{RA, RS, UI}},
6983 {"xoril",	OP(26),		OP_MASK,     PWRCOM,	PPCVLE,		{RA, RS, UI}},
6985 {"xoris",	OP(27),		OP_MASK,     PPCCOM,	PPCVLE,		{RA, RS, UI}},
6986 {"xoriu",	OP(27),		OP_MASK,     PWRCOM,	PPCVLE,		{RA, RS, UI}},
6988 {"andi.",	OP(28),		OP_MASK,     PPCCOM,	PPCVLE,		{RA, RS, UI}},
6989 {"andil.",	OP(28),		OP_MASK,     PWRCOM,	PPCVLE,		{RA, RS, UI}},
6991 {"andis.",	OP(29),		OP_MASK,     PPCCOM,	PPCVLE,		{RA, RS, UI}},
6992 {"andiu.",	OP(29),		OP_MASK,     PWRCOM,	PPCVLE,		{RA, RS, UI}},
6994 {"rotldi",	MD(30,0,0),	MDMB_MASK,   PPC64,	PPCVLE|EXT,	{RA, RS, SH6}},
6995 {"rotrdi",	MD(30,0,0),	MDMB_MASK,   PPC64,	PPCVLE|EXT,	{RA, RS, RRDn}},
6996 {"clrldi",	MD(30,0,0),	MDSH_MASK,   PPC64,	PPCVLE|EXT,	{RA, RS, MB6}},
6997 {"srdi",	MD(30,0,0),	MD_MASK,     PPC64,	PPCVLE|EXT,	{RA, RS, SRDn}},
6998 {"rldicl",	MD(30,0,0),	MD_MASK,     PPC64,	PPCVLE,		{RA, RS, SH6, MB6}},
6999 {"extrdi",	MD(30,0,0),	MD_MASK,     PPC64,	PPCVLE|EXT,	{RA, RS, ERDn, ERDb}},
7000 {"rotldi.",	MD(30,0,1),	MDMB_MASK,   PPC64,	PPCVLE|EXT,	{RA, RS, SH6}},
7001 {"rotrdi.",	MD(30,0,1),	MDMB_MASK,   PPC64,	PPCVLE|EXT,	{RA, RS, RRDn}},
7002 {"clrldi.",	MD(30,0,1),	MDSH_MASK,   PPC64,	PPCVLE|EXT,	{RA, RS, MB6}},
7003 {"srdi.",	MD(30,0,1),	MD_MASK,     PPC64,	PPCVLE|EXT,	{RA, RS, SRDn}},
7004 {"rldicl.",	MD(30,0,1),	MD_MASK,     PPC64,	PPCVLE,		{RA, RS, SH6, MB6}},
7005 {"extrdi.",	MD(30,0,1),	MD_MASK,     PPC64,	PPCVLE|EXT,	{RA, RS, ERDn, ERDb}},
7007 {"clrrdi",	MD(30,1,0),	MDSH_MASK,   PPC64,	PPCVLE|EXT,	{RA, RS, CRDn}},
7008 {"sldi",	MD(30,1,0),	MD_MASK,     PPC64,	PPCVLE|EXT,	{RA, RS, SLDn}},
7009 {"rldicr",	MD(30,1,0),	MD_MASK,     PPC64,	PPCVLE,		{RA, RS, SH6, ME6}},
7010 {"extldi",	MD(30,1,0),	MD_MASK,     PPC64,	PPCVLE,		{RA, RS, ELDn, SH6}},
7011 {"clrrdi.",	MD(30,1,1),	MDSH_MASK,   PPC64,	PPCVLE|EXT,	{RA, RS, CRDn}},
7012 {"sldi.",	MD(30,1,1),	MD_MASK,     PPC64,	PPCVLE|EXT,	{RA, RS, SLDn}},
7013 RA, RS, SH6, ME6}},
7014 {"extldi.",	MD(30,1,1),	MD_MASK,     PPC64,	PPCVLE,		{RA, RS, ELDn, SH6}},
7016 {"rldic",	MD(30,2,0),	MD_MASK,     PPC64,	PPCVLE,		{RA, RS, SH6, MB6}},
7017 {"clrlsldi",	MD(30,2,0),	MD_MASK,     PPC64,	PPCVLE|EXT,	{RA, RS, CSLDb, CSLDn}},
7018 {"rldic.",	MD(30,2,1),	MD_MASK,     PPC64,	PPCVLE,		{RA, RS, SH6, MB6}},
7019 {"clrlsldi.",	MD(30,2,1),	MD_MASK,     PPC64,	PPCVLE|EXT,	{RA, RS, CSLDb, CSLDn}},
7021 {"rldimi",	MD(30,3,0),	MD_MASK,     PPC64,	PPCVLE,		{RA, RS, SH6, MB6}},
7022 {"insrdi",	MD(30,3,0),	MD_MASK,     PPC64,	PPCVLE|EXT,	{RA, RS, IRDn, IRDb}},
7023 {"rldimi.",	MD(30,3,1),	MD_MASK,     PPC64,	PPCVLE,		{RA, RS, SH6, MB6}},
7024 {"insrdi.",	MD(30,3,1),	MD_MASK,     PPC64,	PPCVLE|EXT,	{RA, RS, IRDn, IRDb}},
7026 {"rotld",	MDS(30,8,0),	MDSMB_MASK,  PPC64,	PPCVLE|EXT,	{RA, RS, RB}},
7027 {"rldcl",	MDS(30,8,0),	MDS_MASK,    PPC64,	PPCVLE,		{RA, RS, RB, MB6}},
7028 {"rotld.",	MDS(30,8,1),	MDSMB_MASK,  PPC64,	PPCVLE|EXT,	{RA, RS, RB}},
7029 {"rldcl.",	MDS(30,8,1),	MDS_MASK,    PPC64,	PPCVLE,		{RA, RS, RB, MB6}},
7031 {"rldcr",	MDS(30,9,0),	MDS_MASK,    PPC64,	PPCVLE,		{RA, RS, RB, ME6}},
7032 {"rldcr.",	MDS(30,9,1),	MDS_MASK,    PPC64,	PPCVLE,		{RA, RS, RB, ME6}},
7034 {"cmpw",	XOPL(31,0,0),	XCMPL_MASK,  PPCCOM,	EXT,		{OBF, RA, RB}},
7035 {"cmpd",	XOPL(31,0,1),	XCMPL_MASK,  PPC64,	EXT,		{OBF, RA, RB}},
7036 {"cmp",		X(31,0),	XCMP_MASK,   PPC,	0,		{BF, L32OPT, RA, RB}},
7037 {"cmp",		X(31,0),	XCMPL_MASK,  PWRCOM,	PPC,		{BF, RA, RB}},
7039 {"twlgt",	XTO(31,4,TOLGT), XTO_MASK,   PPCCOM,	EXT,		{RA, RB}},
7040 {"tlgt",	XTO(31,4,TOLGT), XTO_MASK,   PWRCOM,	EXT,		{RA, RB}},
7041 {"twllt",	XTO(31,4,TOLLT), XTO_MASK,   PPCCOM,	EXT,		{RA, RB}},
7042 {"tllt",	XTO(31,4,TOLLT), XTO_MASK,   PWRCOM,	EXT,		{RA, RB}},
7043 {"tweq",	XTO(31,4,TOEQ),	 XTO_MASK,   PPCCOM,	EXT,		{RA, RB}},
7044 {"teq",		XTO(31,4,TOEQ),	 XTO_MASK,   PWRCOM,	EXT,		{RA, RB}},
7045 {"twlge",	XTO(31,4,TOLGE), XTO_MASK,   PPCCOM,	EXT,		{RA, RB}},
7046 {"tlge",	XTO(31,4,TOLGE), XTO_MASK,   PWRCOM,	EXT,		{RA, RB}},
7047 {"twlnl",	XTO(31,4,TOLNL), XTO_MASK,   PPCCOM,	EXT,		{RA, RB}},
7048 {"tlnl",	XTO(31,4,TOLNL), XTO_MASK,   PWRCOM,	EXT,		{RA, RB}},
7049 {"twlle",	XTO(31,4,TOLLE), XTO_MASK,   PPCCOM,	EXT,		{RA, RB}},
7050 {"tlle",	XTO(31,4,TOLLE), XTO_MASK,   PWRCOM,	EXT,		{RA, RB}},
7051 {"twlng",	XTO(31,4,TOLNG), XTO_MASK,   PPCCOM,	EXT,		{RA, RB}},
7052 {"tlng",	XTO(31,4,TOLNG), XTO_MASK,   PWRCOM,	EXT,		{RA, RB}},
7053 {"twgt",	XTO(31,4,TOGT),	 XTO_MASK,   PPCCOM,	EXT,		{RA, RB}},
7054 {"tgt",		XTO(31,4,TOGT),	 XTO_MASK,   PWRCOM,	EXT,		{RA, RB}},
7055 {"twge",	XTO(31,4,TOGE),	 XTO_MASK,   PPCCOM,	EXT,		{RA, RB}},
7056 {"tge",		XTO(31,4,TOGE),	 XTO_MASK,   PWRCOM,	EXT,		{RA, RB}},
7057 {"twnl",	XTO(31,4,TONL),	 XTO_MASK,   PPCCOM,	EXT,		{RA, RB}},
7058 {"tnl",		XTO(31,4,TONL),	 XTO_MASK,   PWRCOM,	EXT,		{RA, RB}},
7059 {"twlt",	XTO(31,4,TOLT),	 XTO_MASK,   PPCCOM,	EXT,		{RA, RB}},
7060 {"tlt",		XTO(31,4,TOLT),	 XTO_MASK,   PWRCOM,	EXT,		{RA, RB}},
7061 {"twle",	XTO(31,4,TOLE),	 XTO_MASK,   PPCCOM,	EXT,		{RA, RB}},
7062 {"tle",		XTO(31,4,TOLE),	 XTO_MASK,   PWRCOM,	EXT,		{RA, RB}},
7063 {"twng",	XTO(31,4,TONG),	 XTO_MASK,   PPCCOM,	EXT,		{RA, RB}},
7064 {"tng",		XTO(31,4,TONG),	 XTO_MASK,   PWRCOM,	EXT,		{RA, RB}},
7065 {"twne",	XTO(31,4,TONE),	 XTO_MASK,   PPCCOM,	EXT,		{RA, RB}},
7066 {"tne",		XTO(31,4,TONE),	 XTO_MASK,   PWRCOM,	EXT,		{RA, RB}},
7068 {"twu",		XTO(31,4,TOU),	 XTO_MASK,   PPCCOM,	EXT,		{RA, RB}},
7069 {"tu",		XTO(31,4,TOU),	 XTO_MASK,   PWRCOM,	EXT,		{RA, RB}},
7070 {"tw",		X(31,4),	 X_MASK,     PPCCOM,	0,		{TO, RA, RB}},
7071 {"t",		X(31,4),	 X_MASK,     PWRCOM,	0,		{TO, RA, RB}},
7075 {"lbfcmx",	APU(31,7,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
7077 {"subfc",	XO(31,8,0,0),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
7078 {"sf",		XO(31,8,0,0),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
7079 {"subc",	XO(31,8,0,0),	XO_MASK,     PPCCOM,	EXT,		{RT, RB, RA}},
7080 {"subfc.",	XO(31,8,0,1),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
7081 {"sf.",		XO(31,8,0,1),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
7082 {"subc.",	XO(31,8,0,1),	XO_MASK,     PPCCOM,	EXT,		{RT, RB, RA}},
7084 {"mulhdu",	XO(31,9,0,0),	XO_MASK,     PPC64,	0,		{RT, RA, RB}},
7085 {"mulhdu.",	XO(31,9,0,1),	XO_MASK,     PPC64,	0,		{RT, RA, RB}},
7087 {"addc",	XO(31,10,0,0),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
7088 {"a",		XO(31,10,0,0),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
7089 {"addc.",	XO(31,10,0,1),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
7090 {"a.",		XO(31,10,0,1),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
7092 {"mulhwu",	XO(31,11,0,0),	XO_MASK,     PPC,	0,		{RT, RA, RB}},
7093 {"mulhwu.",	XO(31,11,0,1),	XO_MASK,     PPC,	0,		{RT, RA, RB}},
7119 {"lx",		X(31,23),	X_MASK,	     PWRCOM,	0,		{RT, RA, RB}},
7121 {"slw",		XRC(31,24,0),	X_MASK,	     PPCCOM,	0,		{RA, RS, RB}},
7122 {"sl",		XRC(31,24,0),	X_MASK,	     PWRCOM,	0,		{RA, RS, RB}},
7123 {"slw.",	XRC(31,24,1),	X_MASK,	     PPCCOM,	0,		{RA, RS, RB}},
7124 {"sl.",		XRC(31,24,1),	X_MASK,	     PWRCOM,	0,		{RA, RS, RB}},
7126 {"cntlzw",	XRC(31,26,0),	XRB_MASK,    PPCCOM,	0,		{RA, RS}},
7127 {"cntlz",	XRC(31,26,0),	XRB_MASK,    PWRCOM,	0,		{RA, RS}},
7128 {"cntlzw.",	XRC(31,26,1),	XRB_MASK,    PPCCOM,	0,		{RA, RS}},
7129 {"cntlz.",	XRC(31,26,1),	XRB_MASK,    PWRCOM,	0,		{RA, RS}},
7131 {"sld",		XRC(31,27,0),	X_MASK,	     PPC64,	0,		{RA, RS, RB}},
7132 {"sld.",	XRC(31,27,1),	X_MASK,	     PPC64,	0,		{RA, RS, RB}},
7134 {"and",		XRC(31,28,0),	X_MASK,	     COM,	0,		{RA, RS, RB}},
7135 {"and.",	XRC(31,28,1),	X_MASK,	     COM,	0,		{RA, RS, RB}},
7137 {"maskg",	XRC(31,29,0),	X_MASK,	     M601,	PPCA2,		{RA, RS, RB}},
7138 {"maskg.",	XRC(31,29,1),	X_MASK,	     M601,	PPCA2,		{RA, RS, RB}},
7150 {"cmplw",	XOPL(31,32,0),	XCMPL_MASK,  PPCCOM,	EXT,		{OBF, RA, RB}},
7151 {"cmpld",	XOPL(31,32,1),	XCMPL_MASK,  PPC64,	EXT,		{OBF, RA, RB}},
7152 {"cmpl",	X(31,32),	XCMP_MASK,   PPC,	0,		{BF, L32OPT, RA, RB}},
7153 {"cmpl",	X(31,32),	XCMPL_MASK,  PWRCOM,	PPC,		{BF, RA, RB}},
7157 {"lhfcmx",	APU(31,39,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
7161 {"mviwsplt",	X(31,46),	X_MASK,	     E6500,	0,		{VD, RA, RB}},
7165 {"addg6s",	XO(31,74,0,0),	XO_MASK,     POWER6,	0,		{RT, RA, RB}},
7171 {"subf",	XO(31,40,0,0),	XO_MASK,     PPC,	0,		{RT, RA, RB}},
7172 {"sub",		XO(31,40,0,0),	XO_MASK,     PPC,	EXT,		{RT, RB, RA}},
7173 {"subf.",	XO(31,40,0,1),	XO_MASK,     PPC,	0,		{RT, RA, RB}},
7174 {"sub.",	XO(31,40,0,1),	XO_MASK,     PPC,	EXT,		{RT, RB, RA}},
7176 {"mffprd",	X(31,51),	XX1RB_MASK|1, PPCVSX2,	EXT,		{RA, FRS}},
7177 {"mfvrd",	X(31,51)|1,	XX1RB_MASK|1, PPCVSX2,	EXT,		{RA, VS}},
7178 {"mfvsrd",	X(31,51),	XX1RB_MASK,   PPCVSX2,	0,		{RA, XS6}},
7179 {"eratilx",	X(31,51),	X_MASK,	     PPCA2,	0,		{ERAT_T, RA, RB}},
7188 {"lux",		X(31,55),	X_MASK,	     PWRCOM,	0,		{RT, RA, RB}},
7190 {"cntlzd",	XRC(31,58,0),	XRB_MASK,    PPC64,	0,		{RA, RS}},
7191 {"cntlzd.",	XRC(31,58,1),	XRB_MASK,    PPC64,	0,		{RA, RS}},
7193 {"cntlzdm",	X(31,59),	X_MASK,	     POWER10,	0,		{RA, RS, RB}},
7195 {"andc",	XRC(31,60,0),	X_MASK,	     COM,	0,		{RA, RS, RB}},
7196 {"andc.",	XRC(31,60,1),	X_MASK,	     COM,	0,		{RA, RS, RB}},
7204 {"tdlgt",	XTO(31,68,TOLGT), XTO_MASK,  PPC64,	EXT,		{RA, RB}},
7205 {"tdllt",	XTO(31,68,TOLLT), XTO_MASK,  PPC64,	EXT,		{RA, RB}},
7206 {"tdeq",	XTO(31,68,TOEQ),  XTO_MASK,  PPC64,	EXT,		{RA, RB}},
7207 {"tdlge",	XTO(31,68,TOLGE), XTO_MASK,  PPC64,	EXT,		{RA, RB}},
7208 {"tdlnl",	XTO(31,68,TOLNL), XTO_MASK,  PPC64,	EXT,		{RA, RB}},
7209 {"tdlle",	XTO(31,68,TOLLE), XTO_MASK,  PPC64,	EXT,		{RA, RB}},
7210 {"tdlng",	XTO(31,68,TOLNG), XTO_MASK,  PPC64,	EXT,		{RA, RB}},
7211 {"tdgt",	XTO(31,68,TOGT),  XTO_MASK,  PPC64,	EXT,		{RA, RB}},
7212 {"tdge",	XTO(31,68,TOGE),  XTO_MASK,  PPC64,	EXT,		{RA, RB}},
7213 {"tdnl",	XTO(31,68,TONL),  XTO_MASK,  PPC64,	EXT,		{RA, RB}},
7214 {"tdlt",	XTO(31,68,TOLT),  XTO_MASK,  PPC64,	EXT,		{RA, RB}},
7215 {"tdle",	XTO(31,68,TOLE),  XTO_MASK,  PPC64,	EXT,		{RA, RB}},
7216 {"tdng",	XTO(31,68,TONG),  XTO_MASK,  PPC64,	EXT,		{RA, RB}},
7217 {"tdne",	XTO(31,68,TONE),  XTO_MASK,  PPC64,	EXT,		{RA, RB}},
7218 {"tdu",		XTO(31,68,TOU),	  XTO_MASK,  PPC64,	EXT,		{RA, RB}},
7219 {"td",		X(31,68),	X_MASK,	     PPC64,	0,		{TO, RA, RB}},
7221 {"lwfcmx",	APU(31,71,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
7222 {"subwus",	XO(31,72,0,0),	XO_MASK,     FUTURE,	EXT,		{RT, RB, RA}},
7223 {"subwus.",	XO(31,72,0,1),	XO_MASK,     FUTURE,	EXT,		{RT, RB, RA}},
7224 {"subdus",	XO(31,72,1,0),	XO_MASK,     FUTURE,	EXT,		{RT, RB, RA}},
7225 {"subdus.",	XO(31,72,1,1),	XO_MASK,     FUTURE,	EXT,		{RT, RB, RA}},
7226 {"subfus",	XO(31,72,0,0),	XOL_MASK,    FUTURE,	0,		{RT, XOL, RA, RB}},
7227 {"subfus.",	XO(31,72,0,1),	XOL_MASK,    FUTURE,	0,		{RT, XOL, RA, RB}},
7228 {"mulhd",	XO(31,73,0,0),	XO_MASK,     PPC64,	0,		{RT, RA, RB}},
7229 {"mulhd.",	XO(31,73,0,1),	XO_MASK,     PPC64,	0,		{RT, RA, RB}},
7231 {"mulhw",	XO(31,75,0,0),	XO_MASK,     PPC,	0,		{RT, RA, RB}},
7232 {"mulhw.",	XO(31,75,0,1),	XO_MASK,     PPC,	0,		{RT, RA, RB}},
7235 {"dlmzb",	XRC(31,78,0), X_MASK, PPC403|PPC440|PPC476|TITAN, 0,	{RA, RS, RB}},
7236 {"dlmzb.",	XRC(31,78,1), X_MASK, PPC403|PPC440|PPC476|TITAN, 0,	{RA, RS, RB}},
7258 {"lqfcmx",	APU(31,103,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
7260 {"neg",		XO(31,104,0,0),	XORB_MASK,   COM,	0,		{RT, RA}},
7261 {"neg.",	XO(31,104,0,1),	XORB_MASK,   COM,	0,		{RT, RA}},
7263 {"mul",		XO(31,107,0,0),	XO_MASK,     M601,	0,		{RT, RA, RB}},
7264 {"mul.",	XO(31,107,0,1),	XO_MASK,     M601,	0,		{RT, RA, RB}},
7269 {"mvidsplt",	X(31,110),	X_MASK,	     E6500,	0,		{VD, RA, RB}},
7273 {"mffprwz",	X(31,115),	XX1RB_MASK|1, PPCVSX2,	EXT,		{RA, FRS}},
7274 {"mfvrwz",	X(31,115)|1,	XX1RB_MASK|1, PPCVSX2,	EXT,		{RA, VS}},
7275 {"mfvsrwz",	X(31,115),	XX1RB_MASK,   PPCVSX2,	0,		{RA, XS6}},
7279 {"clf",		X(31,118),	XTO_MASK,    POWER,	0,		{RA, RB}},
7283 {"popcntb",	X(31,122),	XRB_MASK,    POWER5,	0,		{RA, RS}},
7285 {"not",		XRC(31,124,0),	X_MASK,	     COM,	EXT,		{RA, RSB}},
7286 {"nor",		XRC(31,124,0),	X_MASK,	     COM,	0,		{RA, RS, RB}},
7287 {"not.",	XRC(31,124,1),	X_MASK,	     COM,	EXT,		{RA, RSB}},
7288 {"nor.",	XRC(31,124,1),	X_MASK,	     COM,	0,		{RA, RS, RB}},
7299 {"stbfcmx",	APU(31,135,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
7301 {"subfe",	XO(31,136,0,0),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
7302 {"sfe",		XO(31,136,0,0),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
7303 {"subfe.",	XO(31,136,0,1),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
7304 {"sfe.",	XO(31,136,0,1),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
7306 {"adde",	XO(31,138,0,0),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
7307 {"ae",		XO(31,138,0,0),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
7308 {"adde.",	XO(31,138,0,1),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
7309 {"ae.",		XO(31,138,0,1),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
7333 {"stx",		X(31,151),	X_MASK,	     PWRCOM,	0,		{RS, RA, RB}},
7335 {"slq",		XRC(31,152,0),	X_MASK,	     M601,	0,		{RA, RS, RB}},
7336 {"slq.",	XRC(31,152,1),	X_MASK,	     M601,	0,		{RA, RS, RB}},
7338 {"sle",		XRC(31,153,0),	X_MASK,	     M601,	0,		{RA, RS, RB}},
7339 {"sle.",	XRC(31,153,1),	X_MASK,	     M601,	0,		{RA, RS, RB}},
7341 {"prtyw",	X(31,154),    XRB_MASK, POWER6|PPCA2|PPC476, 0,		{RA, RS}},
7343 {"brw",		X(31,155),	XRB_MASK,    POWER10,	0,		{RA, RS}},
7344 {"pdepd",	X(31,156),	X_MASK,	     POWER10,	0,		{RA, RS, RB}},
7355 {"sthfcmx",	APU(31,167,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
7357 {"addex",	ZRC(31,170,0),	Z2_MASK,     POWER9,	0,		{RT, RA, RB, CY}},
7376 {"mtfprd",	X(31,179),	XX1RB_MASK|1, PPCVSX2,	EXT,		{FRT, RA}},
7377 {"mtvrd",	X(31,179)|1,	XX1RB_MASK|1, PPCVSX2,	EXT,		{VD, RA}},
7378 {"mtvsrd",	X(31,179),	XX1RB_MASK,   PPCVSX2,	0,		{XT6, RA}},
7379 {"eratre",	X(31,179),	X_MASK,	     PPCA2,	0,		{RT, RA, WS}},
7389 {"sliq",	XRC(31,184,0),	X_MASK,	     M601,	0,		{RA, RS, SH}},
7390 {"sliq.",	XRC(31,184,1),	X_MASK,	     M601,	0,		{RA, RS, SH}},
7392 {"prtyd",	X(31,186),	XRB_MASK, POWER6|PPCA2,	0,		{RA, RS}},
7394 {"brd",		X(31,187),	XRB_MASK,    POWER10,	0,		{RA, RS}},
7395 {"pextd",	X(31,188),	X_MASK,	     POWER10,	0,		{RA, RS, RB}},
7397 {"cmprb",	X(31,192),	XCMP_MASK,   POWER9,	0,		{BF, L, RA, RB}},
7402 {"stwfcmx",	APU(31,199,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
7404 {"subfze",	XO(31,200,0,0),	XORB_MASK,   PPCCOM,	0,		{RT, RA}},
7405 {"sfze",	XO(31,200,0,0),	XORB_MASK,   PWRCOM,	0,		{RT, RA}},
7406 {"subfze.",	XO(31,200,0,1),	XORB_MASK,   PPCCOM,	0,		{RT, RA}},
7407 {"sfze.",	XO(31,200,0,1),	XORB_MASK,   PWRCOM,	0,		{RT, RA}},
7409 {"addze",	XO(31,202,0,0),	XORB_MASK,   PPCCOM,	0,		{RT, RA}},
7410 {"aze",		XO(31,202,0,0),	XORB_MASK,   PWRCOM,	0,		{RT, RA}},
7411 {"addze.",	XO(31,202,0,1),	XORB_MASK,   PPCCOM,	0,		{RT, RA}},
7412 {"aze.",	XO(31,202,0,1),	XORB_MASK,   PWRCOM,	0,		{RT, RA}},
7420 {"mtfprwa",	X(31,211),	XX1RB_MASK|1, PPCVSX2,	EXT,		{FRT, RA}},
7421 {"mtvrwa",	X(31,211)|1,	XX1RB_MASK|1, PPCVSX2,	EXT,		{VD, RA}},
7422 {"mtvsrwa",	X(31,211),	XX1RB_MASK,   PPCVSX2,	0,		{XT6, RA}},
7423 {"eratwe",	X(31,211),	X_MASK,	     PPCA2,	0,		{RS, RA, WS}},
7431 {"sllq",	XRC(31,216,0),	X_MASK,	     M601,	0,		{RA, RS, RB}},
7432 {"sllq.",	XRC(31,216,1),	X_MASK,	     M601,	0,		{RA, RS, RB}},
7434 {"sleq",	XRC(31,217,0),	X_MASK,	     M601,	0,		{RA, RS, RB}},
7435 {"sleq.",	XRC(31,217,1),	X_MASK,	     M601,	0,		{RA, RS, RB}},
7437 {"brh",		X(31,219),	XRB_MASK,    POWER10,	0,		{RA, RS}},
7438 {"cfuged",	X(31,220),	X_MASK,	     POWER10,	0,		{RA, RS, RB}},
7442 {"cmpeqb",	X(31,224),	XCMPL_MASK,  POWER9,	0,		{BF, RA, RB}},
7447 {"stqfcmx",	APU(31,231,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
7449 {"subfme",	XO(31,232,0,0),	XORB_MASK,   PPCCOM,	0,		{RT, RA}},
7450 {"sfme",	XO(31,232,0,0),	XORB_MASK,   PWRCOM,	0,		{RT, RA}},
7451 {"subfme.",	XO(31,232,0,1),	XORB_MASK,   PPCCOM,	0,		{RT, RA}},
7452 {"sfme.",	XO(31,232,0,1),	XORB_MASK,   PWRCOM,	0,		{RT, RA}},
7454 {"mulld",	XO(31,233,0,0),	XO_MASK,     PPC64,	0,		{RT, RA, RB}},
7455 {"mulld.",	XO(31,233,0,1),	XO_MASK,     PPC64,	0,		{RT, RA, RB}},
7457 {"addme",	XO(31,234,0,0),	XORB_MASK,   PPCCOM,	0,		{RT, RA}},
7458 {"ame",		XO(31,234,0,0),	XORB_MASK,   PWRCOM,	0,		{RT, RA}},
7459 {"addme.",	XO(31,234,0,1),	XORB_MASK,   PPCCOM,	0,		{RT, RA}},
7460 {"ame.",	XO(31,234,0,1),	XORB_MASK,   PWRCOM,	0,		{RT, RA}},
7462 {"mullw",	XO(31,235,0,0),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
7463 {"muls",	XO(31,235,0,0),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
7464 {"mullw.",	XO(31,235,0,1),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
7465 {"muls.",	XO(31,235,0,1),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
7469 {"icblce",	X(31,238),	X_MASK,	     PPCCHLK,	E500MC|PPCA2,	{CT, RA, RB}},
7474 {"mtfprwz",	X(31,243),	XX1RB_MASK|1, PPCVSX2,	EXT,		{FRT, RA}},
7475 {"mtvrwz",	X(31,243)|1,	XX1RB_MASK|1, PPCVSX2,	EXT,		{VD, RA}},
7476 {"mtvsrwz",	X(31,243),	XX1RB_MASK,   PPCVSX2,	0,		{XT6, RA}},
7487 {"slliq",	XRC(31,248,0),	X_MASK,	     M601,	0,		{RA, RS, SH}},
7488 {"slliq.",	XRC(31,248,1),	X_MASK,	     M601,	0,		{RA, RS, SH}},
7490 {"bpermd",	X(31,252),	X_MASK,	  POWER7|PPCA2,	0,		{RA, RS, RB}},
7494 {"mfdcrx",	X(31,259),	X_MASK, BOOKE|PPCA2|PPC476, TITAN,	{RS, RA}},
7495 {"mfdcrx.",	XRC(31,259,1),	X_MASK,	     PPCA2,	0,		{RS, RA}},
7499 {"icbt",	X(31,262),	XRT_MASK,    PPC403,	0,		{RA, RB}},
7502 {"ldfcmx",	APU(31,263,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
7504 {"doz",		XO(31,264,0,0),	XO_MASK,     M601,	0,		{RT, RA, RB}},
7505 {"doz.",	XO(31,264,0,1),	XO_MASK,     M601,	0,		{RT, RA, RB}},
7507 {"modud",	X(31,265),	X_MASK,	     POWER9,	0,		{RT, RA, RB}},
7509 {"add",		XO(31,266,0,0),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
7510 {"cax",		XO(31,266,0,0),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
7511 {"add.",	XO(31,266,0,1),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
7512 {"cax.",	XO(31,266,0,1),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
7514 {"moduw",	X(31,267),	X_MASK,	     POWER9,	0,		{RT, RA, RB}},
7524 {"mfapidi",	X(31,275),	X_MASK,	     BOOKE,	E500|TITAN,	{RT, RA}},
7528 {"lscbx",	XRC(31,277,0),	X_MASK,	     M601,	0,		{RT, RA, RB}},
7529 {"lscbx.",	XRC(31,277,1),	X_MASK,	     M601,	0,		{RT, RA, RB}},
7541 {"cdtbcd",	X(31,282),	XRB_MASK,    POWER6,	0,		{RA, RS}},
7543 {"eqv",		XRC(31,284,0),	X_MASK,	     COM,	0,		{RA, RS, RB}},
7544 {"eqv.",	XRC(31,284,1),	X_MASK,	     COM,	0,		{RA, RS, RB}},
7548 {"mfdcrux",	X(31,291),	X_MASK,	 PPC464|PPC476,	0,		{RS, RA}},
7562 {"mfvsrld",	X(31,307),	XX1RB_MASK,  PPCVSX3,	0,		{RA, XS6}},
7568 {"cbcdtd",	X(31,314),	XRB_MASK,    POWER6,	0,		{RA, RS}},
7570 {"xor",		XRC(31,316,0),	X_MASK,	     COM,	0,		{RA, RS, RB}},
7571 {"xor.",	XRC(31,316,1),	X_MASK,	     COM,	0,		{RA, RS, RB}},
7616 {"div",		XO(31,331,0,0),	XO_MASK,     M601,	0,		{RT, RA, RB}},
7617 {"div.",	XO(31,331,0,1),	XO_MASK,     M601,	0,		{RT, RA, RB}},
7930 {"dst",		XDSS(31,342,0),	XDSS_MASK,   PPCVEC,	0,		{RA, RB, STRM}},
7931 {"dstt",	XDSS(31,342,1),	XDSS_MASK,   PPCVEC,	0,		{RA, RB, STRM}},
7937 {"abs",		XO(31,360,0,0),	XORB_MASK,   M601,	0,		{RT, RA}},
7938 {"abs.",	XO(31,360,0,1),	XORB_MASK,   M601,	0,		{RT, RA}},
7940 {"divs",	XO(31,363,0,0),	XO_MASK,     M601,	0,		{RT, RA, RB}},
7941 {"divs.",	XO(31,363,0,1),	XO_MASK,     M601,	0,		{RT, RA, RB}},
7953 {"dstst",	XDSS(31,374,0),	XDSS_MASK,   PPCVEC,	0,		{RA, RB, STRM}},
7954 {"dststt",	XDSS(31,374,1),	XDSS_MASK,   PPCVEC,	0,		{RA, RB, STRM}},
7958 {"popcntw",	X(31,378),	XRB_MASK,    POWER7|PPCA2, 0,		{RA, RS}},
7962 {"mtdcrx",	X(31,387),	X_MASK,	     BOOKE|PPCA2|PPC476, TITAN,	{RA, RS}},
7963 {"mtdcrx.",	XRC(31,387,1),	X_MASK,	     PPCA2,	0,		{RA, RS}},
7968 {"stdfcmx",	APU(31,391,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
7970 {"divdeu",	XO(31,393,0,0),	XO_MASK,     POWER7|PPCA2, 0,		{RT, RA, RB}},
7971 {"divdeu.",	XO(31,393,0,1),	XO_MASK,     POWER7|PPCA2, 0,		{RT, RA, RB}},
7972 {"divweu",	XO(31,395,0,0),	XO_MASK,     POWER7|PPCA2, 0,		{RT, RA, RB}},
7973 {"divweu.",	XO(31,395,0,1),	XO_MASK,     POWER7|PPCA2, 0,		{RT, RA, RB}},
7978 {"dcblce",	X(31,398),	X_MASK,	     PPCCHLK,	E500MC,		{CT, RA, RB}},
7982 {"mtvsrws",	X(31,403),	XX1RB_MASK,  PPCVSX3,	0,		{XT6, RA}},
7986 {"icswx",	XRC(31,406,0),	X_MASK,	  POWER7|PPCA2,	0,		{RS, RA, RB}},
7987 {"icswx.",	XRC(31,406,1),	X_MASK,	  POWER7|PPCA2,	0,		{RS, RA, RB}},
7991 {"orc",		XRC(31,412,0),	X_MASK,	     COM,	0,		{RA, RS, RB}},
7992 {"orc.",	XRC(31,412,1),	X_MASK,	     COM,	0,		{RA, RS, RB}},
7998 {"mtdcrux",	X(31,419),	X_MASK,	 PPC464|PPC476,	0,		{RA, RS}},
8004 {"divde",	XO(31,425,0,0),	XO_MASK,  POWER7|PPCA2,	0,		{RT, RA, RB}},
8005 {"divde.",	XO(31,425,0,1),	XO_MASK,  POWER7|PPCA2,	0,		{RT, RA, RB}},
8006 {"divwe",	XO(31,427,0,0),	XO_MASK,  POWER7|PPCA2,	0,		{RT, RA, RB}},
8007 {"divwe.",	XO(31,427,0,1),	XO_MASK,  POWER7|PPCA2,	0,		{RT, RA, RB}},
8043 {"mr",		XRC(31,444,0),	X_MASK,	     COM,	EXT,		{RA, RSB}},
8044 {"or",		XRC(31,444,0),	X_MASK,	     COM,	0,		{RA, RS, RB}},
8045 {"mr.",		XRC(31,444,1),	X_MASK,	     COM,	EXT,		{RA, RSB}},
8046 {"or.",		XRC(31,444,1),	X_MASK,	     COM,	0,		{RA, RS, RB}},
8092 {"divdu",	XO(31,457,0,0),	XO_MASK,     PPC64,	0,		{RT, RA, RB}},
8093 {"divdu.",	XO(31,457,0,1),	XO_MASK,     PPC64,	0,		{RT, RA, RB}},
8095 {"divwu",	XO(31,459,0,0),	XO_MASK,     PPC,	0,		{RT, RA, RB}},
8096 {"divwu.",	XO(31,459,0,1),	XO_MASK,     PPC,	0,		{RT, RA, RB}},
8366 {"nand",	XRC(31,476,0),	X_MASK,	     COM,	0,		{RA, RS, RB}},
8367 {"nand.",	XRC(31,476,1),	X_MASK,	     COM,	0,		{RA, RS, RB}},
8371 {"dsn",		X(31,483),	XRT_MASK,    E500MC,	0,		{RA, RB}},
8379 {"nabs",	XO(31,488,0,0),	XORB_MASK,   M601,	0,		{RT, RA}},
8380 {"nabs.",	XO(31,488,0,1),	XORB_MASK,   M601,	0,		{RT, RA}},
8382 {"divd",	XO(31,489,0,0),	XO_MASK,     PPC64,	0,		{RT, RA, RB}},
8383 {"divd.",	XO(31,489,0,1),	XO_MASK,     PPC64,	0,		{RT, RA, RB}},
8385 {"divw",	XO(31,491,0,0),	XO_MASK,     PPC,	0,		{RT, RA, RB}},
8386 {"divw.",	XO(31,491,0,1),	XO_MASK,     PPC,	0,		{RT, RA, RB}},
8388 {"icbtlse",	X(31,494),	X_MASK,	     PPCCHLK,	E500MC,		{CT, RA, RB}},
8393 {"cli",		X(31,502),	XRB_MASK,    POWER,	0,		{RT, RA}},
8395 {"popcntd",	X(31,506),	XRB_MASK, POWER7|PPCA2,	0,		{RA, RS}},
8397 {"cmpb",	X(31,508),	X_MASK, POWER6|PPCA2|PPC476, 0,		{RA, RS, RB}},
8401 {"lbdcbx",	X(31,514),	X_MASK,      E200Z4,	0,		{RT, RA, RB}},
8402 {"lbdx",	X(31,515),	X_MASK,	 E500MC|E200Z4,	0,		{RT, RA, RB}},
8407 {"lbfcmux",	APU(31,519,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
8409 {"subfco",	XO(31,8,1,0),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
8410 {"sfo",		XO(31,8,1,0),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
8411 {"subco",	XO(31,8,1,0),	XO_MASK,     PPCCOM,	EXT,		{RT, RB, RA}},
8412 {"subfco.",	XO(31,8,1,1),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
8413 {"sfo.",	XO(31,8,1,1),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
8414 {"subco.",	XO(31,8,1,1),	XO_MASK,     PPCCOM,	EXT,		{RT, RB, RA}},
8416 {"addco",	XO(31,10,1,0),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
8417 {"ao",		XO(31,10,1,0),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
8418 {"addco.",	XO(31,10,1,1),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
8419 {"ao.",		XO(31,10,1,1),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
8424 {"clcs",	X(31,531),	XRB_MASK,    M601,	0,		{RT, RA}},
8429 {"lsx",		X(31,533),	X_MASK,	     PWRCOM,	0,		{RT, RA, RB}},
8432 {"lbrx",	X(31,534),	X_MASK,	     PWRCOM,	0,		{RT, RA, RB}},
8436 {"srw",		XRC(31,536,0),	X_MASK,	     PPCCOM,	0,		{RA, RS, RB}},
8437 {"sr",		XRC(31,536,0),	X_MASK,	     PWRCOM,	0,		{RA, RS, RB}},
8438 {"srw.",	XRC(31,536,1),	X_MASK,	     PPCCOM,	0,		{RA, RS, RB}},
8439 {"sr.",		XRC(31,536,1),	X_MASK,	     PWRCOM,	0,		{RA, RS, RB}},
8441 {"rrib",	XRC(31,537,0),	X_MASK,	     M601,	0,		{RA, RS, RB}},
8442 {"rrib.",	XRC(31,537,1),	X_MASK,	     M601,	0,		{RA, RS, RB}},
8444 {"cnttzw",	XRC(31,538,0),	XRB_MASK,    POWER9,	0,		{RA, RS}},
8445 {"cnttzw.",	XRC(31,538,1),	XRB_MASK,    POWER9,	0,		{RA, RS}},
8447 {"srd",		XRC(31,539,0),	X_MASK,	     PPC64,	0,		{RA, RS, RB}},
8448 {"srd.",	XRC(31,539,1),	X_MASK,	     PPC64,	0,		{RA, RS, RB}},
8450 {"maskir",	XRC(31,541,0),	X_MASK,	     M601,	0,		{RA, RS, RB}},
8451 {"maskir.",	XRC(31,541,1),	X_MASK,	     M601,	0,		{RA, RS, RB}},
8453 {"lhdcbx",	X(31,546),	X_MASK,      E200Z4,	0,		{RT, RA, RB}},
8454 {"lhdx",	X(31,547),	X_MASK,	 E500MC|E200Z4,	0,		{RT, RA, RB}},
8461 {"lhfcmux",	APU(31,551,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
8463 {"subfo",	XO(31,40,1,0),	XO_MASK,     PPC,	0,		{RT, RA, RB}},
8464 {"subo",	XO(31,40,1,0),	XO_MASK,     PPC,	EXT,		{RT, RB, RA}},
8465 {"subfo.",	XO(31,40,1,1),	XO_MASK,     PPC,	0,		{RT, RA, RB}},
8466 {"subo.",	XO(31,40,1,1),	XO_MASK,     PPC,	EXT,		{RT, RB, RA}},
8474 {"cnttzd",	XRC(31,570,0),	XRB_MASK,    POWER9,	0,		{RA, RS}},
8475 {"cnttzd.",	XRC(31,570,1),	XRB_MASK,    POWER9,	0,		{RA, RS}},
8477 {"cnttzdm",	X(31,571),	X_MASK,	     POWER10,	0,		{RA, RS, RB}},
8481 {"lwdcbx",	X(31,578),	X_MASK,      E200Z4,	0,		{RT, RA, RB}},
8482 {"lwdx",	X(31,579),	X_MASK,	 E500MC|E200Z4,	0,		{RT, RA, RB}},
8488 {"lwfcmux",	APU(31,583,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
8519 {"lddx",	X(31,611),	X_MASK,	     E500MC,	0,		{RT, RA, RB}},
8525 {"lqfcmux",	APU(31,615,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
8527 {"nego",	XO(31,104,1,0),	XORB_MASK,   COM,	0,		{RT, RA}},
8528 {"nego.",	XO(31,104,1,1),	XORB_MASK,   COM,	0,		{RT, RA}},
8530 {"mulo",	XO(31,107,1,0),	XO_MASK,     M601,	0,		{RT, RA, RB}},
8531 {"mulo.",	XO(31,107,1,1),	XO_MASK,     M601,	0,		{RT, RA, RB}},
8535 {"mfsri",	X(31,627),	X_MASK,	     M601,	0,		{RT, RA, RB}},
8537 {"dclst",	X(31,630),	XRB_MASK,    M601,	0,		{RS, RA}},
8541 {"stbdcbx",	X(31,642),	X_MASK,      E200Z4,	0,		{RS, RA, RB}},
8542 {"stbdx",	X(31,643),	X_MASK,	 E500MC|E200Z4,	0,		{RS, RA, RB}},
8545 {"stbfcmux",	APU(31,647,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
8552 {"subfeo",	XO(31,136,1,0),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
8553 {"sfeo",	XO(31,136,1,0),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
8554 {"subfeo.",	XO(31,136,1,1),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
8555 {"sfeo.",	XO(31,136,1,1),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
8557 {"addeo",	XO(31,138,1,0),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
8558 {"aeo",		XO(31,138,1,0),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
8559 {"addeo.",	XO(31,138,1,1),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
8560 {"aeo.",	XO(31,138,1,1),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
8576 {"srq",		XRC(31,664,0),	X_MASK,	     M601,	0,		{RA, RS, RB}},
8577 {"srq.",	XRC(31,664,1),	X_MASK,	     M601,	0,		{RA, RS, RB}},
8579 {"sre",		XRC(31,665,0),	X_MASK,	     M601,	0,		{RA, RS, RB}},
8580 {"sre.",	XRC(31,665,1),	X_MASK,	     M601,	0,		{RA, RS, RB}},
8582 {"sthdcbx",	X(31,674),	X_MASK,      E200Z4,	0,		{RS, RA, RB}},
8583 {"sthdx",	X(31,675),	X_MASK,	 E500MC|E200Z4,	0,		{RS, RA, RB}},
8588 {"sthfcmux",	APU(31,679,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
8601 {"sriq",	XRC(31,696,0),	X_MASK,	     M601,	0,		{RA, RS, SH}},
8602 {"sriq.",	XRC(31,696,1),	X_MASK,	     M601,	0,		{RA, RS, SH}},
8604 {"stwdcbx",	X(31,706),	X_MASK,	     E200Z4,	0,		{RS, RA, RB}},
8605 {"stwdx",	X(31,707),	X_MASK,	 E500MC|E200Z4,	0,		{RS, RA, RB}},
8611 {"stwfcmux",	APU(31,711,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
8618 {"subfzeo",	XO(31,200,1,0),	XORB_MASK,   PPCCOM,	0,		{RT, RA}},
8619 {"sfzeo",	XO(31,200,1,0),	XORB_MASK,   PWRCOM,	0,		{RT, RA}},
8620 {"subfzeo.",	XO(31,200,1,1),	XORB_MASK,   PPCCOM,	0,		{RT, RA}},
8621 {"sfzeo.",	XO(31,200,1,1),	XORB_MASK,   PWRCOM,	0,		{RT, RA}},
8623 {"addzeo",	XO(31,202,1,0),	XORB_MASK,   PPCCOM,	0,		{RT, RA}},
8624 {"azeo",	XO(31,202,1,0),	XORB_MASK,   PWRCOM,	0,		{RT, RA}},
8625 {"addzeo.",	XO(31,202,1,1),	XORB_MASK,   PPCCOM,	0,		{RT, RA}},
8626 {"azeo.",	XO(31,202,1,1),	XORB_MASK,   PWRCOM,	0,		{RT, RA}},
8637 {"srlq",	XRC(31,728,0),	X_MASK,	     M601,	0,		{RA, RS, RB}},
8638 {"srlq.",	XRC(31,728,1),	X_MASK,	     M601,	0,		{RA, RS, RB}},
8640 {"sreq",	XRC(31,729,0),	X_MASK,	     M601,	0,		{RA, RS, RB}},
8641 {"sreq.",	XRC(31,729,1),	X_MASK,	     M601,	0,		{RA, RS, RB}},
8646 RA, RB}},
8652 {"stqfcmux",	APU(31,743,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
8654 {"subfmeo",	XO(31,232,1,0),	XORB_MASK,   PPCCOM,	0,		{RT, RA}},
8655 {"sfmeo",	XO(31,232,1,0),	XORB_MASK,   PWRCOM,	0,		{RT, RA}},
8656 {"subfmeo.",	XO(31,232,1,1),	XORB_MASK,   PPCCOM,	0,		{RT, RA}},
8657 {"sfmeo.",	XO(31,232,1,1),	XORB_MASK,   PWRCOM,	0,		{RT, RA}},
8659 {"mulldo",	XO(31,233,1,0),	XO_MASK,     PPC64,	0,		{RT, RA, RB}},
8660 {"mulldo.",	XO(31,233,1,1),	XO_MASK,     PPC64,	0,		{RT, RA, RB}},
8662 {"addmeo",	XO(31,234,1,0),	XORB_MASK,   PPCCOM,	0,		{RT, RA}},
8663 {"ameo",	XO(31,234,1,0),	XORB_MASK,   PWRCOM,	0,		{RT, RA}},
8664 {"addmeo.",	XO(31,234,1,1),	XORB_MASK,   PPCCOM,	0,		{RT, RA}},
8665 {"ameo.",	XO(31,234,1,1),	XORB_MASK,   PWRCOM,	0,		{RT, RA}},
8667 {"mullwo",	XO(31,235,1,0),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
8668 {"mulso",	XO(31,235,1,0),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
8669 {"mullwo.",	XO(31,235,1,1),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
8670 {"mulso.",	XO(31,235,1,1),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
8687 {"srliq",	XRC(31,760,0),	X_MASK,	     M601,	0,		{RA, RS, SH}},
8688 {"srliq.",	XRC(31,760,1),	X_MASK,	     M601,	0,		{RA, RS, SH}},
8696 {"ldfcmux",	APU(31,775,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
8698 {"dozo",	XO(31,264,1,0),	XO_MASK,     M601,	0,		{RT, RA, RB}},
8699 {"dozo.",	XO(31,264,1,1),	XO_MASK,     M601,	0,		{RT, RA, RB}},
8701 {"addo",	XO(31,266,1,0),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
8702 {"caxo",	XO(31,266,1,0),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
8703 {"addo.",	XO(31,266,1,1),	XO_MASK,     PPCCOM,	0,		{RT, RA, RB}},
8704 {"caxo.",	XO(31,266,1,1),	XO_MASK,     PWRCOM,	0,		{RT, RA, RB}},
8706 {"modsd",	X(31,777),	X_MASK,	     POWER9,	0,		{RT, RA, RB}},
8707 {"modsw",	X(31,779),	X_MASK,	     POWER9,	0,		{RT, RA, RB}},
8712 {"tabortwc.",	XRC(31,782,1),	X_MASK,	     PPCHTM,	0,		{TO, RA, RB}},
8721 {"lfqx",	X(31,791),	X_MASK,	     POWER2,	0,		{FRT, RA, RB}},
8723 {"sraw",	XRC(31,792,0),	X_MASK,	     PPCCOM,	0,		{RA, RS, RB}},
8724 {"sra",		XRC(31,792,0),	X_MASK,	     PWRCOM,	0,		{RA, RS, RB}},
8725 {"sraw.",	XRC(31,792,1),	X_MASK,	     PPCCOM,	0,		{RA, RS, RB}},
8726 {"sra.",	XRC(31,792,1),	X_MASK,	     PWRCOM,	0,		{RA, RS, RB}},
8728 {"srad",	XRC(31,794,0),	X_MASK,	     PPC64,	0,		{RA, RS, RB}},
8729 {"srad.",	XRC(31,794,1),	X_MASK,	     PPC64,	0,		{RA, RS, RB}},
8731 {"evlddepx",    VX (31, 1598),	VX_MASK,     PPCSPE,	0,		{RT, RA, RB}},
8732 {"lfddx",	X(31,803),	X_MASK,	     E500MC,	0,		{FRT, RA, RB}},
8741 {"tabortdc.",	XRC(31,814,1),	X_MASK,	     PPCHTM,	0,		{TO, RA, RB}},
8743 {"rac",		X(31,818),	X_MASK,	     M601,	0,		{RT, RA, RB}},
8752 {"lfqux",	X(31,823),	X_MASK,	     POWER2,	0,		{FRT, RA, RB}},
8754 {"srawi",	XRC(31,824,0),	X_MASK,	     PPCCOM,	0,		{RA, RS, SH}},
8755 {"srai",	XRC(31,824,0),	X_MASK,	     PWRCOM,	0,		{RA, RS, SH}},
8756 {"srawi.",	XRC(31,824,1),	X_MASK,	     PPCCOM,	0,		{RA, RS, SH}},
8757 {"srai.",	XRC(31,824,1),	X_MASK,	     PWRCOM,	0,		{RA, RS, SH}},
8759 {"sradi",	XS(31,413,0),	XS_MASK,     PPC64,	0,		{RA, RS, SH6}},
8760 {"sradi.",	XS(31,413,1),	XS_MASK,     PPC64,	0,		{RA, RS, SH6}},
8766 {"divo",	XO(31,331,1,0),	XO_MASK,     M601,	0,		{RT, RA, RB}},
8767 {"divo.",	XO(31,331,1,1),	XO_MASK,     M601,	0,		{RT, RA, RB}},
8772 {"tabortwci.",	XRC(31,846,1),	X_MASK,	     PPCHTM,	0,		{TO, RA, HTM_SI}},
8793 {"abso",	XO(31,360,1,0),	XORB_MASK,   M601,	0,		{RT, RA}},
8794 {"abso.",	XO(31,360,1,1),	XORB_MASK,   M601,	0,		{RT, RA}},
8796 {"divso",	XO(31,363,1,0),	XO_MASK,     M601,	0,		{RT, RA, RB}},
8797 {"divso.",	XO(31,363,1,1),	XO_MASK,     M601,	0,		{RT, RA, RB}},
8801 {"tabortdci.",	XRC(31,878,1),	X_MASK,	     PPCHTM,	0,		{TO, RA, HTM_SI}},
8811 {"extswsli",	XS(31,445,0),	XS_MASK,     POWER9,	0,		{RA, RS, SH6}},
8812 {"extswsli.",	XS(31,445,1),	XS_MASK,     POWER9,	0,		{RA, RS, SH6}},
8818 {"stdfcmux",	APU(31,903,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
8820 {"divdeuo",	XO(31,393,1,0),	XO_MASK,  POWER7|PPCA2,	0,		{RT, RA, RB}},
8821 {"divdeuo.",	XO(31,393,1,1),	XO_MASK,  POWER7|PPCA2,	0,		{RT, RA, RB}},
8822 {"divweuo",	XO(31,395,1,0),	XO_MASK,  POWER7|PPCA2,	0,		{RT, RA, RB}},
8823 {"divweuo.",	XO(31,395,1,1),	XO_MASK,  POWER7|PPCA2,	0,		{RT, RA, RB}},
8828 {"tabort.",	XRC(31,910,1),	XRTRB_MASK,  PPCHTM,	0,		{RA}},
8843 {"sraq",	XRC(31,920,0),	X_MASK,	     M601,	0,		{RA, RS, RB}},
8844 {"sraq.",	XRC(31,920,1),	X_MASK,	     M601,	0,		{RA, RS, RB}},
8846 {"srea",	XRC(31,921,0),	X_MASK,	     M601,	0,		{RA, RS, RB}},
8847 {"srea.",	XRC(31,921,1),	X_MASK,	     M601,	0,		{RA, RS, RB}},
8849 {"extsh",	XRC(31,922,0),	XRB_MASK,    PPCCOM,	0,		{RA, RS}},
8850 {"exts",	XRC(31,922,0),	XRB_MASK,    PWRCOM,	0,		{RA, RS}},
8851 {"extsh.",	XRC(31,922,1),	XRB_MASK,    PPCCOM,	0,		{RA, RS}},
8852 {"exts.",	XRC(31,922,1),	XRB_MASK,    PWRCOM,	0,		{RA, RS}},
8854 {"evstddepx",	VX (31, 1854),	VX_MASK,     PPCSPE,	0,		{RT, RA, RB}},
8855 {"stfddx",	X(31,931),	X_MASK,	     E500MC,	0,		{FRS, RA, RB}},
8865 {"divdeo",	XO(31,425,1,0),	XO_MASK,  POWER7|PPCA2,	0,		{RT, RA, RB}},
8866 {"divdeo.",	XO(31,425,1,1),	XO_MASK,  POWER7|PPCA2,	0,		{RT, RA, RB}},
8867 {"divweo",	XO(31,427,1,0),	XO_MASK,  POWER7|PPCA2,	0,		{RT, RA, RB}},
8868 {"divweo.",	XO(31,427,1,1),	XO_MASK,  POWER7|PPCA2,	0,		{RT, RA, RB}},
8873 {"treclaim.",	XRC(31,942,1),	XRTRB_MASK,  PPCHTM,	0,		{RA}},
8875 {"tlbrehi",	XTLB(31,946,0),	XTLB_MASK,   PPC403,	PPCA2|EXT,	{RT, RA}},
8876 {"tlbrelo",	XTLB(31,946,1),	XTLB_MASK,   PPC403,	PPCA2|EXT,	{RT, RA}},
8881 {"icswepx",	XRC(31,950,0),	X_MASK,	     PPCA2,	0,		{RS, RA, RB}},
8882 {"icswepx.",	XRC(31,950,1),	X_MASK,	     PPCA2,	0,		{RS, RA, RB}},
8884 {"stfqux",	X(31,951),	X_MASK,	     POWER2,	0,		{FRS, RA, RB}},
8886 {"sraiq",	XRC(31,952,0),	X_MASK,	     M601,	0,		{RA, RS, SH}},
8887 {"sraiq.",	XRC(31,952,1),	X_MASK,	     M601,	0,		{RA, RS, SH}},
8889 {"extsb",	XRC(31,954,0),	XRB_MASK,    PPC,	0,		{RA, RS}},
8890 {"extsb.",	XRC(31,954,1),	XRB_MASK,    PPC,	0,		{RA, RS}},
8897 {"divduo",	XO(31,457,1,0),	XO_MASK,     PPC64,	0,		{RT, RA, RB}},
8898 {"divduo.",	XO(31,457,1,1),	XO_MASK,     PPC64,	0,		{RT, RA, RB}},
8900 {"divwuo",	XO(31,459,1,0),	XO_MASK,     PPC,	0,		{RT, RA, RB}},
8901 {"divwuo.",	XO(31,459,1,1),	XO_MASK,     PPC,	0,		{RT, RA, RB}},
8907 {"tlbwehi",	XTLB(31,978,0),	XTLB_MASK,   PPC403,	EXT,		{RT, RA}},
8908 {"tlbwelo",	XTLB(31,978,1),	XTLB_MASK,   PPC403,	EXT,		{RT, RA}},
8919 {"extsw",	XRC(31,986,0),	XRB_MASK,    PPC64,	0,		{RA, RS}},
8920 {"extsw.",	XRC(31,986,1),	XRB_MASK,    PPC64,	0,		{RA, RS}},
8928 {"nabso",	XO(31,488,1,0),	XORB_MASK,   M601,	0,		{RT, RA}},
8929 {"nabso.",	XO(31,488,1,1),	XORB_MASK,   M601,	0,		{RT, RA}},
8931 {"divdo",	XO(31,489,1,0),	XO_MASK,     PPC64,	0,		{RT, RA, RB}},
8932 {"divdo.",	XO(31,489,1,1),	XO_MASK,     PPC64,	0,		{RT, RA, RB}},
8934 {"divwo",	XO(31,491,1,0),	XO_MASK,     PPC,	0,		{RT, RA, RB}},
8935 {"divwo.",	XO(31,491,1,1),	XO_MASK,     PPC,	0,		{RT, RA, RB}},
9006 {"psq_l",	OP(56),		OP_MASK,     PPCPS,	PPCVLE,		{FRT,PSD,RA,PSW,PSQ}},
9012 {"psq_lu",	OP(57),		OP_MASK,     PPCPS,	PPCVLE,		{FRT,PSD,RA,PSW,PSQ}},
9419 {"xsiexpdp",	X(60,918),	XX1_MASK,    PPCVSX3,	PPCVLE,		{XT6, RA, RB}},
9453 {"psq_st",	OP(60),		OP_MASK,     PPCPS,	PPCVLE,		{FRS,PSD,RA,PSW,PSQ}},
9454 {"stfq",	OP(60),		OP_MASK,     POWER2,	PPCVLE,		{FRS, D, RA}},
9461 {"psq_stu",	OP(61),		OP_MASK,     PPCPS,	PPCVLE,		{FRS,PSD,RA,PSW,PSQ}},
9462 {"stfqu",	OP(61),		OP_MASK,     POWER2,	PPCVLE,		{FRS, D, RA}},
9946 {"e_cmpi",	SCI8BF(6,0,21),	SCI8BF_MASK,	PPCVLE,	0,		{CRD32, RA, SCLSCI8}},
9947 {"e_cmpwi",	SCI8BF(6,0,21),	SCI8BF_MASK,	PPCVLE,	0,		{CRD32, RA, SCLSCI8}},
9948 {"e_cmpli",	SCI8BF(6,1,21),	SCI8BF_MASK,	PPCVLE,	0,		{CRD32, RA, SCLSCI8}},
9949 {"e_cmplwi",	SCI8BF(6,1,21),	SCI8BF_MASK,	PPCVLE,	0,		{CRD32, RA, SCLSCI8}},
9950 {"e_addi",	SCI8(6,16),	SCI8_MASK,	PPCVLE,	0,		{RT, RA, SCLSCI8}},
9951 {"e_subi",	SCI8(6,16),	SCI8_MASK,	PPCVLE,	0,		{RT, RA, SCLSCI8N}},
9952 {"e_addi.",	SCI8(6,17),	SCI8_MASK,	PPCVLE,	0,		{RT, RA, SCLSCI8}},
9953 {"e_addic",	SCI8(6,18),	SCI8_MASK,	PPCVLE,	0,		{RT, RA, SCLSCI8}},
9954 {"e_subic",	SCI8(6,18),	SCI8_MASK,	PPCVLE,	EXT,		{RT, RA, SCLSCI8N}},
9955 {"e_addic.",	SCI8(6,19),	SCI8_MASK,	PPCVLE,	0,		{RT, RA, SCLSCI8}},
9956 {"e_subic.",	SCI8(6,19),	SCI8_MASK,	PPCVLE,	EXT,		{RT, RA, SCLSCI8N}},
9957 {"e_mulli",	SCI8(6,20),	SCI8_MASK,	PPCVLE,	0,		{RT, RA, SCLSCI8}},
9958 {"e_subfic",	SCI8(6,22),	SCI8_MASK,	PPCVLE,	0,		{RT, RA, SCLSCI8}},
9959 {"e_subfic.",	SCI8(6,23),	SCI8_MASK,	PPCVLE,	0,		{RT, RA, SCLSCI8}},
9960 {"e_andi",	SCI8(6,24),	SCI8_MASK,	PPCVLE,	0,		{RA, RS, SCLSCI8}},
9961 {"e_andi.",	SCI8(6,25),	SCI8_MASK,	PPCVLE,	0,		{RA, RS, SCLSCI8}},
9963 {"e_ori",	SCI8(6,26),	SCI8_MASK,	PPCVLE,	0,		{RA, RS, SCLSCI8}},
9964 {"e_ori.",	SCI8(6,27),	SCI8_MASK,	PPCVLE,	0,		{RA, RS, SCLSCI8}},
9965 {"e_xori",	SCI8(6,28),	SCI8_MASK,	PPCVLE,	0,		{RA, RS, SCLSCI8}},
9966 {"e_xori.",	SCI8(6,29),	SCI8_MASK,	PPCVLE,	0,		{RA, RS, SCLSCI8}},
9993 {"e_add16i",	OP(7),		OP_MASK,	PPCVLE,	0,		{RT, RA, SI}},
9995 {"e_sub16i",	OP(7),		OP_MASK,	PPCVLE,	EXT,		{RT, RA, NSI}},
10037 {"e_cmphl16i",	IA16(28,23),	IA16_MASK,	PPCVLE,	0,		{RA, VLEUIMM}},
10038 {"e_cmph16i",	IA16(28,22),	IA16_MASK,	PPCVLE,	0,		{RA, VLESIMM}},
10039 {"e_cmpl16i",	I16A(28,21),	I16A_MASK,	PPCVLE,	0,		{RA, VLEUIMM}},
10040 {"e_mull2i",	I16A(28,20),	I16A_MASK,	PPCVLE,	0,		{RA, VLESIMM}},
10041 {"e_cmp16i",	IA16(28,19),	IA16_MASK,	PPCVLE,	0,		{RA, VLESIMM}},
10042 {"e_sub2is",	I16A(28,18),	I16A_MASK,	PPCVLE,	EXT,		{RA, VLENSIMM}},
10043 {"e_add2is",	I16A(28,18),	I16A_MASK,	PPCVLE,	0,		{RA, VLESIMM}},
10044 {"e_sub2i.",	I16A(28,17),	I16A_MASK,	PPCVLE,	EXT,		{RA, VLENSIMM}},
10045 {"e_add2i.",	I16A(28,17),	I16A_MASK,	PPCVLE,	0,		{RA, VLESIMM}},
10047 {"e_rlwimi",	M(29,0),	M_MASK,		PPCVLE,	0,		{RA, RS, SH, MB, ME}},
10048 {"e_inslwi",	M(29,0),	M_MASK,		PPCVLE, EXT,		{RA, RS, ILWn, ILWb}},
10049 {"e_insrwi",	M(29,0),	M_MASK,		PPCVLE, EXT,		{RA, RS, IRWn, IRWb}},
10050 {"e_rotlwi",	MME(29,31,1),	MMBME_MASK,	PPCVLE, EXT,		{RA, RS, SH}},
10051 {"e_rotrwi",	MME(29,31,1),	MMBME_MASK,	PPCVLE, EXT,		{RA, RS, RRWn}},
10052 {"e_clrlwi",	MME(29,31,1),	MSHME_MASK,	PPCVLE, EXT,		{RA, RS, MB}},
10053 {"e_clrrwi",	M(29,1),	MSHMB_MASK,	PPCVLE, EXT,		{RA, RS, CRWn}},
10054 {"e_rlwinm",	M(29,1),	M_MASK,		PPCVLE,	0,		{RA, RS, SH, MBE, ME}},
10055 {"e_extlwi",	M(29,1),	MMB_MASK,	PPCVLE, EXT,		{RA, RS, ELWn, SH}},
10056 {"e_extrwi",	MME(29,31,1),	MME_MASK,	PPCVLE, EXT,		{RA, RS, ERWn, ERWb}},
10057 {"e_clrlslwi",	M(29,1),	M_MASK,		PPCVLE, EXT,		{RA, RS, CSLWb, CSLWn}},
10096 {"e_cmph",	X(31,14),	X_MASK,		PPCVLE,	0,		{CRD, RA, RB}},
10098 {"e_cmphl",	X(31,46),	X_MASK,		PPCVLE,	0,		{CRD, RA, RB}},
10106 {"e_slwi",	EX(31,112),	EX_MASK,	PPCVLE,	0,		{RA, RS, SH}},
10107 {"e_slwi.",	EX(31,113),	EX_MASK,	PPCVLE,	0,		{RA, RS, SH}},
10111 {"e_rlw",	EX(31,560),	EX_MASK,	PPCVLE,	0,		{RA, RS, RB}},
10112 {"e_rlw.",	EX(31,561),	EX_MASK,	PPCVLE,	0,		{RA, RS, RB}},
10117 {"e_rlwi",	EX(31,624),	EX_MASK,	PPCVLE,	0,		{RA, RS, SH}},
10118 {"e_rlwi.",	EX(31,625),	EX_MASK,	PPCVLE,	0,		{RA, RS, SH}},
10127 {"e_srwi",	EX(31,1136),	EX_MASK,	PPCVLE,	0,		{RA, RS, SH}},
10128 {"e_srwi.",	EX(31,1137),	EX_MASK,	PPCVLE,	0,		{RA, RS, SH}},
10164 {"zvaddih",	      VX(4, 0x200), VX_MASK,	PPCLSP, 0,		{RD, RA, EVUIMM}},
10165 {"zvsubifh",	      VX(4, 0x201), VX_MASK,	PPCLSP, 0,		{RD, RA, EVUIMM}},
10166 {"zvaddh",	      VX(4, 0x204), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10167 {"zvsubfh",	      VX(4, 0x205), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10168 {"zvaddsubfh",	      VX(4, 0x206), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10169 {"zvsubfaddh",	      VX(4, 0x207), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10170 {"zvaddhx",	      VX(4, 0x20C), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10171 {"zvsubfhx",	      VX(4, 0x20D), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10172 {"zvaddsubfhx",	      VX(4, 0x20E), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10173 {"zvsubfaddhx",	      VX(4, 0x20F), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10174 {"zaddwus",	      VX(4, 0x210), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10175 {"zsubfwus",	      VX(4, 0x211), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10176 {"zaddwss",	      VX(4, 0x212), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10177 {"zsubfwss",	      VX(4, 0x213), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10178 {"zvaddhus",	      VX(4, 0x214), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10179 {"zvsubfhus",	      VX(4, 0x215), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10180 {"zvaddhss",	      VX(4, 0x216), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10181 {"zvsubfhss",	      VX(4, 0x217), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10182 {"zvaddsubfhss",      VX(4, 0x21A), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10183 {"zvsubfaddhss",      VX(4, 0x21B), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10184 {"zvaddhxss",	      VX(4, 0x21C), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10185 {"zvsubfhxss",	      VX(4, 0x21D), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10186 {"zvaddsubfhxss",     VX(4, 0x21E), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10187 {"zvsubfaddhxss",     VX(4, 0x21F), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10188 {"zaddheuw",	      VX(4, 0x220), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10189 {"zsubfheuw",	      VX(4, 0x221), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10190 {"zaddhesw",	      VX(4, 0x222), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10191 {"zsubfhesw",	      VX(4, 0x223), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10192 {"zaddhouw",	      VX(4, 0x224), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10193 {"zsubfhouw",	      VX(4, 0x225), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10194 {"zaddhosw",	      VX(4, 0x226), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10195 {"zsubfhosw",	      VX(4, 0x227), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10196 {"zvmergehih",	      VX(4, 0x22C), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10197 {"zvmergeloh",	      VX(4, 0x22D), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10198 {"zvmergehiloh",      VX(4, 0x22E), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10199 {"zvmergelohih",      VX(4, 0x22F), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10200 {"zvcmpgthu",	      VX(4, 0x230), VX_MASK,	PPCLSP, 0,		{CRFD, RA, RB}},
10201 {"zvcmpgths",	      VX(4, 0x230), VX_MASK,	PPCLSP, 0,		{CRFD, RA, RB}},
10202 {"zvcmplthu",	      VX(4, 0x231), VX_MASK,	PPCLSP, 0,		{CRFD, RA, RB}},
10203 {"zvcmplths",	      VX(4, 0x231), VX_MASK,	PPCLSP, 0,		{CRFD, RA, RB}},
10204 {"zvcmpeqh",	      VX(4, 0x232), VX_MASK,	PPCLSP, 0,		{CRFD, RA, RB}},
10205 {"zpkswgshfrs",	      VX(4, 0x238), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10206 {"zpkswgswfrs",	      VX(4, 0x239), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10207 {"zvpkshgwshfrs",     VX(4, 0x23A), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10208 {"zvpkswshfrs",	      VX(4, 0x23B), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10209 {"zvpkswuhs",	      VX(4, 0x23C), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10210 {"zvpkswshs",	      VX(4, 0x23D), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10211 {"zvpkuwuhs",	      VX(4, 0x23E), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10214 {"zcntlsw",	      VX_LSP(4, 0x2A3F), VX_LSP_MASK, PPCLSP, 0,	{RD, RA}},
10215 {"zvcntlzh",	      VX_LSP(4, 0x323F), VX_LSP_MASK, PPCLSP, 0,	{RD, RA}},
10216 {"zvcntlsh",	      VX_LSP(4, 0x3A3F), VX_LSP_MASK, PPCLSP, 0,	{RD, RA}},
10217 {"znegws",	      VX_LSP(4, 0x4A3F), VX_LSP_MASK, PPCLSP, 0,	{RD, RA}},
10218 {"zvnegh",	      VX_LSP(4, 0x523F), VX_LSP_MASK, PPCLSP, 0,	{RD, RA}},
10219 {"zvneghs",	      VX_LSP(4, 0x5A3F), VX_LSP_MASK, PPCLSP, 0,	{RD, RA}},
10220 {"zvnegho",	      VX_LSP(4, 0x623F), VX_LSP_MASK, PPCLSP, 0,	{RD, RA}},
10221 {"zvneghos",	      VX_LSP(4, 0x6A3F), VX_LSP_MASK, PPCLSP, 0,	{RD, RA}},
10222 {"zrndwh",	      VX_LSP(4, 0x823F), VX_LSP_MASK, PPCLSP, 0,	{RD, RA}},
10223 {"zrndwhss",	      VX_LSP(4, 0x8A3F), VX_LSP_MASK, PPCLSP, 0,	{RD, RA}},
10224 {"zvabsh",	      VX_LSP(4, 0xA23F), VX_LSP_MASK, PPCLSP, 0,	{RD, RA}},
10225 {"zvabshs",	      VX_LSP(4, 0xAA3F), VX_LSP_MASK, PPCLSP, 0,	{RD, RA}},
10226 {"zabsw",	      VX_LSP(4, 0xB23F), VX_LSP_MASK, PPCLSP, 0,	{RD, RA}},
10227 {"zabsws",	      VX_LSP(4, 0xBA3F), VX_LSP_MASK, PPCLSP, 0,	{RD, RA}},
10228 {"zsatswuw",	      VX_LSP(4, 0xC23F), VX_LSP_MASK, PPCLSP, 0,	{RD, RA}},
10229 {"zsatuwsw",	      VX_LSP(4, 0xCA3F), VX_LSP_MASK, PPCLSP, 0,	{RD, RA}},
10230 {"zsatswuh",	      VX_LSP(4, 0xD23F), VX_LSP_MASK, PPCLSP, 0,	{RD, RA}},
10231 {"zsatswsh",	      VX_LSP(4, 0xDA3F), VX_LSP_MASK, PPCLSP, 0,	{RD, RA}},
10232 {"zvsatshuh",	      VX_LSP(4, 0xE23F), VX_LSP_MASK, PPCLSP, 0,	{RD, RA}},
10233 {"zvsatuhsh",	      VX_LSP(4, 0xEA3F), VX_LSP_MASK, PPCLSP, 0,	{RD, RA}},
10234 {"zsatuwuh",	      VX_LSP(4, 0xF23F), VX_LSP_MASK, PPCLSP, 0,	{RD, RA}},
10235 {"zsatuwsh",	      VX_LSP(4, 0xFA3F), VX_LSP_MASK, PPCLSP, 0,	{RD, RA}},
10236 {"zsatsduw",	      VX(4, 0x260), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10237 {"zsatsdsw",	      VX(4, 0x261), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10238 {"zsatuduw",	      VX(4, 0x262), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10239 {"zvselh",	      VX(4, 0x264), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10240 {"zxtrw",	      VX(4, 0x264), VX_LSP_OFF_MASK, PPCLSP, 0,		{RD, RA, RB, VX_OFF}},
10241 {"zbrminc",	      VX(4, 0x268), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10242 {"zcircinc",	      VX(4, 0x269), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10243 {"zdivwsf",	      VX(4, 0x26B), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10244 {"zvsrhu",	      VX(4, 0x270), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10245 {"zvsrhs",	      VX(4, 0x271), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10246 {"zvsrhiu",	      VX(4, 0x272), VX_MASK,	PPCLSP, 0,		{RD, RA, EVUIMM_LT16}},
10247 {"zvsrhis",	      VX(4, 0x273), VX_MASK,	PPCLSP, 0,		{RD, RA, EVUIMM_LT16}},
10248 {"zvslh",	      VX(4, 0x274), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10249 {"zvrlh",	      VX(4, 0x275), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10250 {"zvslhi",	      VX(4, 0x276), VX_MASK,	PPCLSP, 0,		{RD, RA, EVUIMM_LT16}},
10251 {"zvrlhi",	      VX(4, 0x277), VX_MASK,	PPCLSP, 0,		{RD, RA, EVUIMM_LT16}},
10252 {"zvslhus",	      VX(4, 0x278), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10253 {"zvslhss",	      VX(4, 0x279), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10254 {"zvslhius",	      VX(4, 0x27A), VX_MASK,	PPCLSP, 0,		{RD, RA, EVUIMM_LT16}},
10255 {"zvslhiss",	      VX(4, 0x27B), VX_MASK,	PPCLSP, 0,		{RD, RA, EVUIMM_LT16}},
10256 {"zslwus",	      VX(4, 0x27C), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10257 {"zslwss",	      VX(4, 0x27D), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10258 {"zslwius",	      VX(4, 0x27E), VX_MASK,	PPCLSP, 0,		{RD, RA, EVUIMM}},
10259 {"zslwiss",	      VX(4, 0x27F), VX_MASK,	PPCLSP, 0,		{RD, RA, EVUIMM}},
10260 {"zlddx",	      VX(4, 0x300), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10261 {"zldd",	      VX(4, 0x301), VX_MASK,	PPCLSP, 0,		{RD_EVEN, EVUIMM_8, RA}},
10262 {"zldwx",	      VX(4, 0x302), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10263 {"zldw",	      VX(4, 0x303), VX_MASK,	PPCLSP, 0,		{RD_EVEN, EVUIMM_8, RA}},
10264 {"zldhx",	      VX(4, 0x304), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10265 {"zldh",	      VX(4, 0x305), VX_MASK,	PPCLSP, 0,		{RD_EVEN, EVUIMM_8, RA}},
10266 {"zlwgsfdx",	      VX(4, 0x308), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10267 {"zlwgsfd",	      VX(4, 0x309), VX_MASK,	PPCLSP, 0,		{RD_EVEN, EVUIMM_4, RA}},
10268 {"zlwwosdx",	      VX(4, 0x30A), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10269 {"zlwwosd",	      VX(4, 0x30B), VX_MASK,	PPCLSP, 0,		{RD_EVEN, EVUIMM_4, RA}},
10270 {"zlwhsplatwdx",      VX(4, 0x30C), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10271 {"zlwhsplatwd",	      VX(4, 0x30D), VX_MASK,	PPCLSP, 0,		{RD_EVEN, EVUIMM_4, RA}},
10272 {"zlwhsplatdx",	      VX(4, 0x30E), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10273 {"zlwhsplatd",	      VX(4, 0x30F), VX_MASK,	PPCLSP, 0,		{RD_EVEN, EVUIMM_4, RA}},
10274 {"zlwhgwsfdx",	      VX(4, 0x310), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10275 {"zlwhgwsfd",	      VX(4, 0x311), VX_MASK,	PPCLSP, 0,		{RD_EVEN, EVUIMM_4, RA}},
10276 {"zlwhedx",	      VX(4, 0x312), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10277 {"zlwhed",	      VX(4, 0x313), VX_MASK,	PPCLSP, 0,		{RD_EVEN, EVUIMM_4, RA}},
10278 {"zlwhosdx",	      VX(4, 0x314), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10279 {"zlwhosd",	      VX(4, 0x315), VX_MASK,	PPCLSP, 0,		{RD_EVEN, EVUIMM_4, RA}},
10280 {"zlwhoudx",	      VX(4, 0x316), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10281 {"zlwhoud",	      VX(4, 0x317), VX_MASK,	PPCLSP, 0,		{RD_EVEN, EVUIMM_4, RA}},
10282 {"zlwhx",	      VX(4, 0x318), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10283 {"zlwh",	      VX(4, 0x319), VX_MASK,	PPCLSP, 0,		{RD, EVUIMM_4, RA}},
10284 {"zlwwx",	      VX(4, 0x31A), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10285 {"zlww",	      VX(4, 0x31B), VX_MASK,	PPCLSP, 0,		{RD, EVUIMM_4, RA}},
10286 {"zlhgwsfx",	      VX(4, 0x31C), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10287 {"zlhgwsf",	      VX(4, 0x31D), VX_MASK,	PPCLSP, 0,		{RD, EVUIMM_2, RA}},
10288 {"zlhhsplatx",	      VX(4, 0x31E), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10289 {"zlhhsplat",	      VX(4, 0x31F), VX_MASK,	PPCLSP, 0,		{RD, EVUIMM_2, RA}},
10290 {"zstddx",	      VX(4, 0x320), VX_MASK,	PPCLSP, 0,		{RS_EVEN, RA, RB}},
10291 {"zstdd",	      VX(4, 0x321), VX_MASK,	PPCLSP, 0,		{RS_EVEN, EVUIMM_8, RA}},
10292 {"zstdwx",	      VX(4, 0x322), VX_MASK,	PPCLSP, 0,		{RS_EVEN, RA, RB}},
10293 {"zstdw",	      VX(4, 0x323), VX_MASK,	PPCLSP, 0,		{RS_EVEN, EVUIMM_8, RA}},
10294 {"zstdhx",	      VX(4, 0x324), VX_MASK,	PPCLSP, 0,		{RS_EVEN, RA, RB}},
10295 {"zstdh",	      VX(4, 0x325), VX_MASK,	PPCLSP, 0,		{RS_EVEN, EVUIMM_8, RA}},
10296 {"zstwhedx",	      VX(4, 0x328), VX_MASK,	PPCLSP, 0,		{RS_EVEN, RA, RB}},
10297 {"zstwhed",	      VX(4, 0x329), VX_MASK,	PPCLSP, 0,		{RS_EVEN, EVUIMM_4, RA}},
10298 {"zstwhodx",	      VX(4, 0x32A), VX_MASK,	PPCLSP, 0,		{RS_EVEN, RA, RB}},
10299 {"zstwhod",	      VX(4, 0x32B), VX_MASK,	PPCLSP, 0,		{RS_EVEN, EVUIMM_4, RA}},
10300 {"zlhhex",	      VX(4, 0x330), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10301 {"zlhhe",	      VX(4, 0x331), VX_MASK,	PPCLSP, 0,		{RD, EVUIMM_2, RA}},
10302 {"zlhhosx",	      VX(4, 0x332), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10303 {"zlhhos",	      VX(4, 0x333), VX_MASK,	PPCLSP, 0,		{RD, EVUIMM_2, RA}},
10304 {"zlhhoux",	      VX(4, 0x334), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10305 {"zlhhou",	      VX(4, 0x335), VX_MASK,	PPCLSP, 0,		{RD, EVUIMM_2, RA}},
10306 {"zsthex",	      VX(4, 0x338), VX_MASK,	PPCLSP, 0,		{RS, RA, RB}},
10307 {"zsthe",	      VX(4, 0x339), VX_MASK,	PPCLSP, 0,		{RS, EVUIMM_2, RA}},
10308 {"zsthox",	      VX(4, 0x33A), VX_MASK,	PPCLSP, 0,		{RS, RA, RB}},
10309 {"zstho",	      VX(4, 0x33B), VX_MASK,	PPCLSP, 0,		{RS, EVUIMM_2, RA}},
10310 {"zstwhx",	      VX(4, 0x33C), VX_MASK,	PPCLSP, 0,		{RS, RA, RB}},
10311 {"zstwh",	      VX(4, 0x33D), VX_MASK,	PPCLSP, 0,		{RS, EVUIMM_4, RA}},
10312 {"zstwwx",	      VX(4, 0x33E), VX_MASK,	PPCLSP, 0,		{RS, RA, RB}},
10313 {"zstww",	      VX(4, 0x33F), VX_MASK,	PPCLSP, 0,		{RS, EVUIMM_4, RA}},
10314 {"zlddmx",	      VX(4, 0x340), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10315 {"zlddu",	      VX(4, 0x341), VX_MASK,	PPCLSP, 0,		{RD_EVEN, EVUIMM_8_EX0, RA}},
10316 {"zldwmx",	      VX(4, 0x342), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10317 {"zldwu",	      VX(4, 0x343), VX_MASK,	PPCLSP, 0,		{RD_EVEN, EVUIMM_8_EX0, RA}},
10318 {"zldhmx",	      VX(4, 0x344), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10319 {"zldhu",	      VX(4, 0x345), VX_MASK,	PPCLSP, 0,		{RD_EVEN, EVUIMM_8_EX0, RA}},
10320 {"zlwgsfdmx",	      VX(4, 0x348), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10321 {"zlwgsfdu",	      VX(4, 0x349), VX_MASK,	PPCLSP, 0,		{RD_EVEN, EVUIMM_4_EX0, RA}},
10322 {"zlwwosdmx",	      VX(4, 0x34A), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10323 {"zlwwosdu",	      VX(4, 0x34B), VX_MASK,	PPCLSP, 0,		{RD_EVEN, EVUIMM_4_EX0, RA}},
10324 {"zlwhsplatwdmx",     VX(4, 0x34C), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10325 {"zlwhsplatwdu",      VX(4, 0x34D), VX_MASK,	PPCLSP, 0,		{RD_EVEN, EVUIMM_4_EX0, RA}},
10326 {"zlwhsplatdmx",      VX(4, 0x34E), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10327 {"zlwhsplatdu",	      VX(4, 0x34F), VX_MASK,	PPCLSP, 0,		{RD_EVEN, EVUIMM_4_EX0, RA}},
10328 {"zlwhgwsfdmx",	      VX(4, 0x350), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10329 {"zlwhgwsfdu",	      VX(4, 0x351), VX_MASK,	PPCLSP, 0,		{RD_EVEN, EVUIMM_4_EX0, RA}},
10330 {"zlwhedmx",	      VX(4, 0x352), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10331 {"zlwhedu",	      VX(4, 0x353), VX_MASK,	PPCLSP, 0,		{RD_EVEN, EVUIMM_4_EX0, RA}},
10332 {"zlwhosdmx",	      VX(4, 0x354), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10333 {"zlwhosdu",	      VX(4, 0x355), VX_MASK,	PPCLSP, 0,		{RD_EVEN, EVUIMM_4_EX0, RA}},
10334 {"zlwhoudmx",	      VX(4, 0x356), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10335 {"zlwhoudu",	      VX(4, 0x357), VX_MASK,	PPCLSP, 0,		{RD_EVEN, EVUIMM_4_EX0, RA}},
10336 {"zlwhmx",	      VX(4, 0x358), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10337 {"zlwhu",	      VX(4, 0x359), VX_MASK,	PPCLSP, 0,		{RD, EVUIMM_4_EX0, RA}},
10338 {"zlwwmx",	      VX(4, 0x35A), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10339 {"zlwwu",	      VX(4, 0x35B), VX_MASK,	PPCLSP, 0,		{RD, EVUIMM_4_EX0, RA}},
10340 {"zlhgwsfmx",	      VX(4, 0x35C), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10341 {"zlhgwsfu",	      VX(4, 0x35D), VX_MASK,	PPCLSP, 0,		{RD, EVUIMM_2_EX0, RA}},
10342 {"zlhhsplatmx",	      VX(4, 0x35E), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10343 RA}},
10344 {"zstddmx",	      VX(4, 0x360), VX_MASK,	PPCLSP, 0,		{RS_EVEN, RA, RB}},
10345 {"zstddu",	      VX(4, 0x361), VX_MASK,	PPCLSP, 0,		{RS, EVUIMM_8_EX0, RA}},
10346 {"zstdwmx",	      VX(4, 0x362), VX_MASK,	PPCLSP, 0,		{RS_EVEN, RA, RB}},
10347 {"zstdwu",	      VX(4, 0x363), VX_MASK,	PPCLSP, 0,		{RS_EVEN, EVUIMM_8_EX0, RA}},
10348 {"zstdhmx",	      VX(4, 0x364), VX_MASK,	PPCLSP, 0,		{RS_EVEN, RA, RB}},
10349 {"zstdhu",	      VX(4, 0x365), VX_MASK,	PPCLSP, 0,		{RS_EVEN, EVUIMM_8_EX0, RA}},
10350 {"zstwhedmx",	      VX(4, 0x368), VX_MASK,	PPCLSP, 0,		{RS_EVEN, RA, RB}},
10351 {"zstwhedu",	      VX(4, 0x369), VX_MASK,	PPCLSP, 0,		{RS_EVEN, EVUIMM_4_EX0, RA}},
10352 {"zstwhodmx",	      VX(4, 0x36A), VX_MASK,	PPCLSP, 0,		{RS_EVEN, RA, RB}},
10353 {"zstwhodu",	      VX(4, 0x36B), VX_MASK,	PPCLSP, 0,		{RS_EVEN, EVUIMM_4_EX0, RA}},
10354 {"zlhhemx",	      VX(4, 0x370), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10355 {"zlhheu",	      VX(4, 0x371), VX_MASK,	PPCLSP, 0,		{RD, EVUIMM_2_EX0, RA}},
10356 {"zlhhosmx",	      VX(4, 0x372), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10357 {"zlhhosu",	      VX(4, 0x373), VX_MASK,	PPCLSP, 0,		{RD, EVUIMM_2_EX0, RA}},
10358 {"zlhhoumx",	      VX(4, 0x374), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10359 {"zlhhouu",	      VX(4, 0x375), VX_MASK,	PPCLSP, 0,		{RD, EVUIMM_2_EX0, RA}},
10360 {"zsthemx",	      VX(4, 0x378), VX_MASK,	PPCLSP, 0,		{RS, RA, RB}},
10361 {"zstheu",	      VX(4, 0x379), VX_MASK,	PPCLSP, 0,		{RS, EVUIMM_2_EX0, RA}},
10362 {"zsthomx",	      VX(4, 0x37A), VX_MASK,	PPCLSP, 0,		{RS, RA, RB}},
10363 {"zsthou",	      VX(4, 0x37B), VX_MASK,	PPCLSP, 0,		{RS, EVUIMM_2_EX0, RA}},
10364 {"zstwhmx",	      VX(4, 0x37C), VX_MASK,	PPCLSP, 0,		{RS, RA, RB}},
10365 {"zstwhu",	      VX(4, 0x37D), VX_MASK,	PPCLSP, 0,		{RS, EVUIMM_4_EX0, RA}},
10366 {"zstwwmx",	      VX(4, 0x37E), VX_MASK,	PPCLSP, 0,		{RS, RA, RB}},
10367 {"zstwwu",	      VX(4, 0x37F), VX_MASK,	PPCLSP, 0,		{RS, EVUIMM_4_EX0, RA}},
10368 {"zaddwgui",	      VX(4, 0x460), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10369 {"zsubfwgui",	      VX(4, 0x461), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10370 {"zaddd",	      VX(4, 0x462), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10371 {"zsubfd",	      VX(4, 0x463), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10372 {"zvaddsubfw",	      VX(4, 0x464), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10373 {"zvsubfaddw",	      VX(4, 0x465), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10374 {"zvaddw",	      VX(4, 0x466), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10375 {"zvsubfw",	      VX(4, 0x467), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10376 {"zaddwgsi",	      VX(4, 0x468), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10377 {"zsubfwgsi",	      VX(4, 0x469), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10378 {"zadddss",	      VX(4, 0x46A), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10379 {"zsubfdss",	      VX(4, 0x46B), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10380 {"zvaddsubfwss",      VX(4, 0x46C), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10381 {"zvsubfaddwss",      VX(4, 0x46D), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10382 {"zvaddwss",	      VX(4, 0x46E), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10383 {"zvsubfwss",	      VX(4, 0x46F), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10384 {"zaddwgsf",	      VX(4, 0x470), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10385 {"zsubfwgsf",	      VX(4, 0x471), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10386 {"zadddus",	      VX(4, 0x472), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10387 {"zsubfdus",	      VX(4, 0x473), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10388 {"zvaddwus",	      VX(4, 0x476), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10389 {"zvsubfwus",	      VX(4, 0x477), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10390 {"zvunpkhgwsf",	      VX_LSP(4, 0x478), VX_LSP_MASK, PPCLSP, 0,		{RD_EVEN, RA}},
10391 {"zvunpkhsf",	      VX_LSP(4, 0xC78), VX_LSP_MASK, PPCLSP, 0,		{RD_EVEN, RA}},
10392 {"zvunpkhui",	      VX_LSP(4, 0x1478), VX_LSP_MASK, PPCLSP, 0,	{RD_EVEN, RA}},
10393 {"zvunpkhsi",	      VX_LSP(4, 0x1C78), VX_LSP_MASK, PPCLSP, 0,	{RD_EVEN, RA}},
10394 {"zunpkwgsf",	      VX_LSP(4, 0x2478), VX_LSP_MASK, PPCLSP, 0,	{RD_EVEN, RA}},
10395 {"zvdotphgwasmf",     VX(4, 0x488), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10396 {"zvdotphgwasmfr",    VX(4, 0x489), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10397 {"zvdotphgwasmfaa",   VX(4, 0x48A), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10398 {"zvdotphgwasmfraa",  VX(4, 0x48B), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10399 {"zvdotphgwasmfan",   VX(4, 0x48C), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10400 {"zvdotphgwasmfran",  VX(4, 0x48D), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10401 {"zvmhulgwsmf",	      VX(4, 0x490), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10402 {"zvmhulgwsmfr",      VX(4, 0x491), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10403 {"zvmhulgwsmfaa",     VX(4, 0x492), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10404 {"zvmhulgwsmfraa",    VX(4, 0x493), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10405 {"zvmhulgwsmfan",     VX(4, 0x494), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10406 {"zvmhulgwsmfran",    VX(4, 0x495), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10407 {"zvmhulgwsmfanp",    VX(4, 0x496), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10408 {"zvmhulgwsmfranp",   VX(4, 0x497), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10409 {"zmhegwsmf",	      VX(4, 0x498), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10410 {"zmhegwsmfr",	      VX(4, 0x499), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10411 {"zmhegwsmfaa",	      VX(4, 0x49A), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10412 {"zmhegwsmfraa",      VX(4, 0x49B), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10413 {"zmhegwsmfan",	      VX(4, 0x49C), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10414 {"zmhegwsmfran",      VX(4, 0x49D), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10415 {"zvdotphxgwasmf",    VX(4, 0x4A8), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10416 {"zvdotphxgwasmfr",   VX(4, 0x4A9), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10417 {"zvdotphxgwasmfaa",  VX(4, 0x4AA), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10418 {"zvdotphxgwasmfraa", VX(4, 0x4AB), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10419 {"zvdotphxgwasmfan",  VX(4, 0x4AC), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10420 {"zvdotphxgwasmfran", VX(4, 0x4AD), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10421 {"zvmhllgwsmf",	      VX(4, 0x4B0), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10422 {"zvmhllgwsmfr",      VX(4, 0x4B1), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10423 {"zvmhllgwsmfaa",     VX(4, 0x4B2), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10424 {"zvmhllgwsmfraa",    VX(4, 0x4B3), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10425 {"zvmhllgwsmfan",     VX(4, 0x4B4), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10426 {"zvmhllgwsmfran",    VX(4, 0x4B5), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10427 {"zvmhllgwsmfanp",    VX(4, 0x4B6), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10428 {"zvmhllgwsmfranp",   VX(4, 0x4B7), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10429 {"zmheogwsmf",	      VX(4, 0x4B8), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10430 {"zmheogwsmfr",	      VX(4, 0x4B9), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10431 {"zmheogwsmfaa",      VX(4, 0x4BA), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10432 {"zmheogwsmfraa",     VX(4, 0x4BB), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10433 {"zmheogwsmfan",      VX(4, 0x4BC), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10434 {"zmheogwsmfran",     VX(4, 0x4BD), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10435 {"zvdotphgwssmf",     VX(4, 0x4C8), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10436 {"zvdotphgwssmfr",    VX(4, 0x4C9), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10437 {"zvdotphgwssmfaa",   VX(4, 0x4CA), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10438 {"zvdotphgwssmfraa",  VX(4, 0x4CB), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10439 {"zvdotphgwssmfan",   VX(4, 0x4CC), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10440 {"zvdotphgwssmfran",  VX(4, 0x4CD), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10441 {"zvmhuugwsmf",	      VX(4, 0x4D0), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10442 {"zvmhuugwsmfr",      VX(4, 0x4D1), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10443 {"zvmhuugwsmfaa",     VX(4, 0x4D2), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10444 {"zvmhuugwsmfraa",    VX(4, 0x4D3), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10445 {"zvmhuugwsmfan",     VX(4, 0x4D4), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10446 {"zvmhuugwsmfran",    VX(4, 0x4D5), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10447 {"zvmhuugwsmfanp",    VX(4, 0x4D6), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10448 {"zvmhuugwsmfranp",   VX(4, 0x4D7), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10449 {"zmhogwsmf",	      VX(4, 0x4D8), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10450 {"zmhogwsmfr",	      VX(4, 0x4D9), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10451 {"zmhogwsmfaa",	      VX(4, 0x4DA), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10452 {"zmhogwsmfraa",      VX(4, 0x4DB), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10453 {"zmhogwsmfan",	      VX(4, 0x4DC), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10454 {"zmhogwsmfran",      VX(4, 0x4DD), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10455 {"zvmhxlgwsmf",	      VX(4, 0x4F0), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10456 {"zvmhxlgwsmfr",      VX(4, 0x4F1), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10457 {"zvmhxlgwsmfaa",     VX(4, 0x4F2), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10458 {"zvmhxlgwsmfraa",    VX(4, 0x4F3), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10459 {"zvmhxlgwsmfan",     VX(4, 0x4F4), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10460 {"zvmhxlgwsmfran",    VX(4, 0x4F5), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10461 {"zvmhxlgwsmfanp",    VX(4, 0x4F6), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10462 {"zvmhxlgwsmfranp",   VX(4, 0x4F7), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10463 {"zmhegui",	      VX(4, 0x500), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10464 {"zvdotphgaui",	      VX(4, 0x501), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10465 {"zmheguiaa",	      VX(4, 0x502), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10466 {"zvdotphgauiaa",     VX(4, 0x503), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10467 {"zmheguian",	      VX(4, 0x504), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10468 {"zvdotphgauian",     VX(4, 0x505), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10469 {"zmhegsi",	      VX(4, 0x508), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10470 {"zvdotphgasi",	      VX(4, 0x509), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10471 {"zmhegsiaa",	      VX(4, 0x50A), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10472 {"zvdotphgasiaa",     VX(4, 0x50B), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10473 {"zmhegsian",	      VX(4, 0x50C), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10474 {"zvdotphgasian",     VX(4, 0x50D), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10475 {"zmhegsui",	      VX(4, 0x510), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10476 {"zvdotphgasui",      VX(4, 0x511), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10477 {"zmhegsuiaa",	      VX(4, 0x512), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10478 {"zvdotphgasuiaa",    VX(4, 0x513), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10479 {"zmhegsuian",	      VX(4, 0x514), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10480 {"zvdotphgasuian",    VX(4, 0x515), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10481 {"zmhegsmf",	      VX(4, 0x518), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10482 {"zvdotphgasmf",      VX(4, 0x519), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10483 {"zmhegsmfaa",	      VX(4, 0x51A), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10484 {"zvdotphgasmfaa",    VX(4, 0x51B), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10485 {"zmhegsmfan",	      VX(4, 0x51C), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10486 {"zvdotphgasmfan",    VX(4, 0x51D), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10487 {"zmheogui",	      VX(4, 0x520), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10488 {"zvdotphxgaui",      VX(4, 0x521), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10489 {"zmheoguiaa",	      VX(4, 0x522), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10490 {"zvdotphxgauiaa",    VX(4, 0x523), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10491 {"zmheoguian",	      VX(4, 0x524), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10492 {"zvdotphxgauian",    VX(4, 0x525), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10493 {"zmheogsi",	      VX(4, 0x528), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10494 {"zvdotphxgasi",      VX(4, 0x529), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10495 {"zmheogsiaa",	      VX(4, 0x52A), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10496 {"zvdotphxgasiaa",    VX(4, 0x52B), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10497 {"zmheogsian",	      VX(4, 0x52C), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10498 {"zvdotphxgasian",    VX(4, 0x52D), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10499 {"zmheogsui",	      VX(4, 0x530), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10500 {"zvdotphxgasui",     VX(4, 0x531), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10501 {"zmheogsuiaa",	      VX(4, 0x532), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10502 {"zvdotphxgasuiaa",   VX(4, 0x533), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10503 {"zmheogsuian",	      VX(4, 0x534), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10504 {"zvdotphxgasuian",   VX(4, 0x535), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10505 {"zmheogsmf",	      VX(4, 0x538), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10506 {"zvdotphxgasmf",     VX(4, 0x539), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10507 {"zmheogsmfaa",	      VX(4, 0x53A), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10508 {"zvdotphxgasmfaa",   VX(4, 0x53B), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10509 {"zmheogsmfan",	      VX(4, 0x53C), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10510 {"zvdotphxgasmfan",   VX(4, 0x53D), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10511 {"zmhogui",	      VX(4, 0x540), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10512 {"zvdotphgsui",	      VX(4, 0x541), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10513 {"zmhoguiaa",	      VX(4, 0x542), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10514 {"zvdotphgsuiaa",     VX(4, 0x543), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10515 {"zmhoguian",	      VX(4, 0x544), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10516 {"zvdotphgsuian",     VX(4, 0x545), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10517 {"zmhogsi",	      VX(4, 0x548), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10518 {"zvdotphgssi",	      VX(4, 0x549), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10519 {"zmhogsiaa",	      VX(4, 0x54A), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10520 {"zvdotphgssiaa",     VX(4, 0x54B), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10521 {"zmhogsian",	      VX(4, 0x54C), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10522 {"zvdotphgssian",     VX(4, 0x54D), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10523 {"zmhogsui",	      VX(4, 0x550), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10524 {"zvdotphgssui",      VX(4, 0x551), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10525 {"zmhogsuiaa",	      VX(4, 0x552), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10526 {"zvdotphgssuiaa",    VX(4, 0x553), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10527 {"zmhogsuian",	      VX(4, 0x554), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10528 {"zvdotphgssuian",    VX(4, 0x555), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10529 {"zmhogsmf",	      VX(4, 0x558), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10530 {"zvdotphgssmf",      VX(4, 0x559), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10531 {"zmhogsmfaa",	      VX(4, 0x55A), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10532 {"zvdotphgssmfaa",    VX(4, 0x55B), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10533 {"zmhogsmfan",	      VX(4, 0x55C), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10534 {"zvdotphgssmfan",    VX(4, 0x55D), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10535 {"zmwgui",	      VX(4, 0x560), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10536 {"zmwguiaa",	      VX(4, 0x562), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10537 {"zmwguiaas",	      VX(4, 0x563), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10538 {"zmwguian",	      VX(4, 0x564), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10539 {"zmwguians",	      VX(4, 0x565), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10540 {"zmwgsi",	      VX(4, 0x568), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10541 {"zmwgsiaa",	      VX(4, 0x56A), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10542 {"zmwgsiaas",	      VX(4, 0x56B), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10543 {"zmwgsian",	      VX(4, 0x56C), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10544 {"zmwgsians",	      VX(4, 0x56D), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10545 {"zmwgsui",	      VX(4, 0x570), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10546 {"zmwgsuiaa",	      VX(4, 0x572), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10547 {"zmwgsuiaas",	      VX(4, 0x573), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10548 {"zmwgsuian",	      VX(4, 0x574), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10549 {"zmwgsuians",	      VX(4, 0x575), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10550 {"zmwgsmf",	      VX(4, 0x578), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10551 {"zmwgsmfr",	      VX(4, 0x579), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10552 {"zmwgsmfaa",	      VX(4, 0x57A), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10553 {"zmwgsmfraa",	      VX(4, 0x57B), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10554 {"zmwgsmfan",	      VX(4, 0x57C), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10555 {"zmwgsmfran",	      VX(4, 0x57D), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10556 {"zvmhului",	      VX(4, 0x580), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10557 {"zvmhuluiaa",	      VX(4, 0x582), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10558 {"zvmhuluiaas",	      VX(4, 0x583), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10559 {"zvmhuluian",	      VX(4, 0x584), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10560 {"zvmhuluians",	      VX(4, 0x585), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10561 RA, RB}},
10562 {"zvmhuluianps",      VX(4, 0x587), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10563 {"zvmhulsi",	      VX(4, 0x588), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10564 {"zvmhulsiaa",	      VX(4, 0x58A), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10565 {"zvmhulsiaas",	      VX(4, 0x58B), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10566 {"zvmhulsian",	      VX(4, 0x58C), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10567 {"zvmhulsians",	      VX(4, 0x58D), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10568 {"zvmhulsianp",	      VX(4, 0x58E), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10569 {"zvmhulsianps",      VX(4, 0x58F), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10570 {"zvmhulsui",	      VX(4, 0x590), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10571 {"zvmhulsuiaa",	      VX(4, 0x592), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10572 {"zvmhulsuiaas",      VX(4, 0x593), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10573 {"zvmhulsuian",	      VX(4, 0x594), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10574 {"zvmhulsuians",      VX(4, 0x595), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10575 {"zvmhulsuianp",      VX(4, 0x596), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10576 {"zvmhulsuianps",     VX(4, 0x597), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10577 {"zvmhulsf",	      VX(4, 0x598), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10578 {"zvmhulsfr",	      VX(4, 0x599), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10579 {"zvmhulsfaas",	      VX(4, 0x59A), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10580 {"zvmhulsfraas",      VX(4, 0x59B), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10581 {"zvmhulsfans",	      VX(4, 0x59C), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10582 {"zvmhulsfrans",      VX(4, 0x59D), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10583 {"zvmhulsfanps",      VX(4, 0x59E), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10584 {"zvmhulsfranps",     VX(4, 0x59F), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10585 {"zvmhllui",	      VX(4, 0x5A0), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10586 {"zvmhlluiaa",	      VX(4, 0x5A2), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10587 {"zvmhlluiaas",	      VX(4, 0x5A3), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10588 {"zvmhlluian",	      VX(4, 0x5A4), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10589 {"zvmhlluians",	      VX(4, 0x5A5), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10590 {"zvmhlluianp",	      VX(4, 0x5A6), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10591 {"zvmhlluianps",      VX(4, 0x5A7), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10592 {"zvmhllsi",	      VX(4, 0x5A8), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10593 {"zvmhllsiaa",	      VX(4, 0x5AA), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10594 {"zvmhllsiaas",	      VX(4, 0x5AB), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10595 {"zvmhllsian",	      VX(4, 0x5AC), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10596 {"zvmhllsians",	      VX(4, 0x5AD), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10597 {"zvmhllsianp",	      VX(4, 0x5AE), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10598 {"zvmhllsianps",      VX(4, 0x5AF), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10599 {"zvmhllsui",	      VX(4, 0x5B0), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10600 {"zvmhllsuiaa",	      VX(4, 0x5B2), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10601 {"zvmhllsuiaas",      VX(4, 0x5B3), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10602 {"zvmhllsuian",	      VX(4, 0x5B4), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10603 {"zvmhllsuians",      VX(4, 0x5B5), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10604 {"zvmhllsuianp",      VX(4, 0x5B6), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10605 {"zvmhllsuianps",     VX(4, 0x5B7), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10606 {"zvmhllsf",	      VX(4, 0x5B8), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10607 {"zvmhllsfr",	      VX(4, 0x5B9), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10608 {"zvmhllsfaas",	      VX(4, 0x5BA), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10609 {"zvmhllsfraas",      VX(4, 0x5BB), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10610 {"zvmhllsfans",	      VX(4, 0x5BC), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10611 {"zvmhllsfrans",      VX(4, 0x5BD), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10612 {"zvmhllsfanps",      VX(4, 0x5BE), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10613 {"zvmhllsfranps",     VX(4, 0x5BF), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10614 {"zvmhuuui",	      VX(4, 0x5C0), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10615 {"zvmhuuuiaa",	      VX(4, 0x5C2), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10616 {"zvmhuuuiaas",	      VX(4, 0x5C3), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10617 {"zvmhuuuian",	      VX(4, 0x5C4), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10618 {"zvmhuuuians",	      VX(4, 0x5C5), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10619 {"zvmhuuuianp",	      VX(4, 0x5C6), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10620 {"zvmhuuuianps",      VX(4, 0x5C7), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10621 {"zvmhuusi",	      VX(4, 0x5C8), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10622 {"zvmhuusiaa",	      VX(4, 0x5CA), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10623 {"zvmhuusiaas",	      VX(4, 0x5CB), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10624 {"zvmhuusian",	      VX(4, 0x5CC), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10625 {"zvmhuusians",	      VX(4, 0x5CD), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10626 {"zvmhuusianp",	      VX(4, 0x5CE), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10627 {"zvmhuusianps",      VX(4, 0x5CF), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10628 {"zvmhuusui",	      VX(4, 0x5D0), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10629 {"zvmhuusuiaa",	      VX(4, 0x5D2), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10630 {"zvmhuusuiaas",      VX(4, 0x5D3), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10631 {"zvmhuusuian",	      VX(4, 0x5D4), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10632 {"zvmhuusuians",      VX(4, 0x5D5), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10633 {"zvmhuusuianp",      VX(4, 0x5D6), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10634 {"zvmhuusuianps",     VX(4, 0x5D7), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10635 {"zvmhuusf",	      VX(4, 0x5D8), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10636 {"zvmhuusfr",	      VX(4, 0x5D9), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10637 {"zvmhuusfaas",	      VX(4, 0x5DA), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10638 {"zvmhuusfraas",      VX(4, 0x5DB), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10639 {"zvmhuusfans",	      VX(4, 0x5DC), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10640 {"zvmhuusfrans",      VX(4, 0x5DD), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10641 {"zvmhuusfanps",      VX(4, 0x5DE), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10642 {"zvmhuusfranps",     VX(4, 0x5DF), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10643 {"zvmhxlui",	      VX(4, 0x5E0), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10644 {"zvmhxluiaa",	      VX(4, 0x5E2), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10645 {"zvmhxluiaas",	      VX(4, 0x5E3), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10646 {"zvmhxluian",	      VX(4, 0x5E4), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10647 {"zvmhxluians",	      VX(4, 0x5E5), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10648 {"zvmhxluianp",	      VX(4, 0x5E6), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10649 {"zvmhxluianps",      VX(4, 0x5E7), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10650 {"zvmhxlsi",	      VX(4, 0x5E8), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10651 {"zvmhxlsiaa",	      VX(4, 0x5EA), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10652 {"zvmhxlsiaas",	      VX(4, 0x5EB), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10653 {"zvmhxlsian",	      VX(4, 0x5EC), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10654 {"zvmhxlsians",	      VX(4, 0x5ED), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10655 {"zvmhxlsianp",	      VX(4, 0x5EE), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10656 {"zvmhxlsianps",      VX(4, 0x5EF), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10657 {"zvmhxlsui",	      VX(4, 0x5F0), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10658 {"zvmhxlsuiaa",	      VX(4, 0x5F2), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10659 {"zvmhxlsuiaas",      VX(4, 0x5F3), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10660 {"zvmhxlsuian",	      VX(4, 0x5F4), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10661 {"zvmhxlsuians",      VX(4, 0x5F5), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10662 {"zvmhxlsuianp",      VX(4, 0x5F6), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10663 {"zvmhxlsuianps",     VX(4, 0x5F7), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10664 {"zvmhxlsf",	      VX(4, 0x5F8), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10665 {"zvmhxlsfr",	      VX(4, 0x5F9), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10666 {"zvmhxlsfaas",	      VX(4, 0x5FA), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10667 {"zvmhxlsfraas",      VX(4, 0x5FB), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10668 {"zvmhxlsfans",	      VX(4, 0x5FC), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10669 {"zvmhxlsfrans",      VX(4, 0x5FD), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10670 {"zvmhxlsfanps",      VX(4, 0x5FE), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10671 {"zvmhxlsfranps",     VX(4, 0x5FF), VX_MASK,	PPCLSP, 0,		{RD_EVEN, RA, RB}},
10672 {"zmheui",	      VX(4, 0x600), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10673 {"zmheuiaa",	      VX(4, 0x602), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10674 {"zmheuiaas",	      VX(4, 0x603), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10675 {"zmheuian",	      VX(4, 0x604), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10676 {"zmheuians",	      VX(4, 0x605), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10677 {"zmhesi",	      VX(4, 0x608), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10678 {"zmhesiaa",	      VX(4, 0x60A), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10679 {"zmhesiaas",	      VX(4, 0x60B), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10680 {"zmhesian",	      VX(4, 0x60C), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10681 {"zmhesians",	      VX(4, 0x60D), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10682 {"zmhesui",	      VX(4, 0x610), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10683 {"zmhesuiaa",	      VX(4, 0x612), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10684 {"zmhesuiaas",	      VX(4, 0x613), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10685 {"zmhesuian",	      VX(4, 0x614), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10686 {"zmhesuians",	      VX(4, 0x615), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10687 {"zmhesf",	      VX(4, 0x618), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10688 {"zmhesfr",	      VX(4, 0x619), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10689 {"zmhesfaas",	      VX(4, 0x61A), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10690 {"zmhesfraas",	      VX(4, 0x61B), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10691 {"zmhesfans",	      VX(4, 0x61C), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10692 {"zmhesfrans",	      VX(4, 0x61D), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10693 {"zmheoui",	      VX(4, 0x620), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10694 {"zmheouiaa",	      VX(4, 0x622), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10695 {"zmheouiaas",	      VX(4, 0x623), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10696 {"zmheouian",	      VX(4, 0x624), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10697 {"zmheouians",	      VX(4, 0x625), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10698 {"zmheosi",	      VX(4, 0x628), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10699 {"zmheosiaa",	      VX(4, 0x62A), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10700 {"zmheosiaas",	      VX(4, 0x62B), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10701 {"zmheosian",	      VX(4, 0x62C), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10702 {"zmheosians",	      VX(4, 0x62D), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10703 {"zmheosui",	      VX(4, 0x630), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10704 {"zmheosuiaa",	      VX(4, 0x632), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10705 {"zmheosuiaas",	      VX(4, 0x633), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10706 {"zmheosuian",	      VX(4, 0x634), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10707 {"zmheosuians",	      VX(4, 0x635), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10708 {"zmheosf",	      VX(4, 0x638), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10709 {"zmheosfr",	      VX(4, 0x639), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10710 {"zmheosfaas",	      VX(4, 0x63A), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10711 {"zmheosfraas",	      VX(4, 0x63B), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10712 {"zmheosfans",	      VX(4, 0x63C), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10713 {"zmheosfrans",	      VX(4, 0x63D), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10714 {"zmhoui",	      VX(4, 0x640), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10715 {"zmhouiaa",	      VX(4, 0x642), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10716 {"zmhouiaas",	      VX(4, 0x643), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10717 {"zmhouian",	      VX(4, 0x644), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10718 {"zmhouians",	      VX(4, 0x645), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10719 {"zmhosi",	      VX(4, 0x648), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10720 {"zmhosiaa",	      VX(4, 0x64A), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10721 {"zmhosiaas",	      VX(4, 0x64B), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10722 {"zmhosian",	      VX(4, 0x64C), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10723 {"zmhosians",	      VX(4, 0x64D), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10724 {"zmhosui",	      VX(4, 0x650), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10725 {"zmhosuiaa",	      VX(4, 0x652), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10726 {"zmhosuiaas",	      VX(4, 0x653), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10727 {"zmhosuian",	      VX(4, 0x654), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10728 {"zmhosuians",	      VX(4, 0x655), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10729 {"zmhosf",	      VX(4, 0x658), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10730 {"zmhosfr",	      VX(4, 0x659), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10731 {"zmhosfaas",	      VX(4, 0x65A), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10732 {"zmhosfraas",	      VX(4, 0x65B), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10733 {"zmhosfans",	      VX(4, 0x65C), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10734 {"zmhosfrans",	      VX(4, 0x65D), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10735 {"zvmhuih",	      VX(4, 0x660), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10736 {"zvmhuihs",	      VX(4, 0x661), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10737 {"zvmhuiaah",	      VX(4, 0x662), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10738 {"zvmhuiaahs",	      VX(4, 0x663), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10739 {"zvmhuianh",	      VX(4, 0x664), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10740 {"zvmhuianhs",	      VX(4, 0x665), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10741 {"zvmhsihs",	      VX(4, 0x669), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10742 {"zvmhsiaahs",	      VX(4, 0x66B), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10743 {"zvmhsianhs",	      VX(4, 0x66D), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10744 {"zvmhsuihs",	      VX(4, 0x671), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10745 {"zvmhsuiaahs",	      VX(4, 0x673), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10746 {"zvmhsuianhs",	      VX(4, 0x675), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10747 {"zvmhsfh",	      VX(4, 0x678), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10748 {"zvmhsfrh",	      VX(4, 0x679), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10749 {"zvmhsfaahs",	      VX(4, 0x67A), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10750 {"zvmhsfraahs",	      VX(4, 0x67B), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10751 {"zvmhsfanhs",	      VX(4, 0x67C), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10752 {"zvmhsfranhs",	      VX(4, 0x67D), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10753 {"zvdotphaui",	      VX(4, 0x680), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10754 {"zvdotphauis",	      VX(4, 0x681), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10755 {"zvdotphauiaa",      VX(4, 0x682), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10756 {"zvdotphauiaas",     VX(4, 0x683), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10757 {"zvdotphauian",      VX(4, 0x684), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10758 {"zvdotphauians",     VX(4, 0x685), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10759 {"zvdotphasi",	      VX(4, 0x688), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10760 {"zvdotphasis",	      VX(4, 0x689), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10761 {"zvdotphasiaa",      VX(4, 0x68A), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10762 {"zvdotphasiaas",     VX(4, 0x68B), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10763 {"zvdotphasian",      VX(4, 0x68C), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10764 {"zvdotphasians",     VX(4, 0x68D), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10765 {"zvdotphasui",	      VX(4, 0x690), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10766 {"zvdotphasuis",      VX(4, 0x691), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10767 {"zvdotphasuiaa",     VX(4, 0x692), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10768 {"zvdotphasuiaas",    VX(4, 0x693), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10769 {"zvdotphasuian",     VX(4, 0x694), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10770 {"zvdotphasuians",    VX(4, 0x695), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10771 {"zvdotphasfs",	      VX(4, 0x698), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10772 {"zvdotphasfrs",      VX(4, 0x699), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10773 {"zvdotphasfaas",     VX(4, 0x69A), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10774 {"zvdotphasfraas",    VX(4, 0x69B), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10775 {"zvdotphasfans",     VX(4, 0x69C), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10776 {"zvdotphasfrans",    VX(4, 0x69D), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10777 {"zvdotphxaui",	      VX(4, 0x6A0), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10778 {"zvdotphxauis",      VX(4, 0x6A1), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10779 {"zvdotphxauiaa",     VX(4, 0x6A2), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10780 {"zvdotphxauiaas",    VX(4, 0x6A3), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10781 {"zvdotphxauian",     VX(4, 0x6A4), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10782 {"zvdotphxauians",    VX(4, 0x6A5), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10783 {"zvdotphxasi",	      VX(4, 0x6A8), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10784 RA, RB}},
10785 {"zvdotphxasiaa",     VX(4, 0x6AA), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10786 {"zvdotphxasiaas",    VX(4, 0x6AB), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10787 {"zvdotphxasian",     VX(4, 0x6AC), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10788 {"zvdotphxasians",    VX(4, 0x6AD), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10789 {"zvdotphxasui",      VX(4, 0x6B0), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10790 {"zvdotphxasuis",     VX(4, 0x6B1), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10791 {"zvdotphxasuiaa",    VX(4, 0x6B2), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10792 {"zvdotphxasuiaas",   VX(4, 0x6B3), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10793 {"zvdotphxasuian",    VX(4, 0x6B4), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10794 {"zvdotphxasuians",   VX(4, 0x6B5), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10795 {"zvdotphxasfs",      VX(4, 0x6B8), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10796 {"zvdotphxasfrs",     VX(4, 0x6B9), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10797 {"zvdotphxasfaas",    VX(4, 0x6BA), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10798 {"zvdotphxasfraas",   VX(4, 0x6BB), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10799 {"zvdotphxasfans",    VX(4, 0x6BC), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10800 {"zvdotphxasfrans",   VX(4, 0x6BD), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10801 {"zvdotphsui",	      VX(4, 0x6C0), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10802 {"zvdotphsuis",	      VX(4, 0x6C1), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10803 {"zvdotphsuiaa",      VX(4, 0x6C2), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10804 {"zvdotphsuiaas",     VX(4, 0x6C3), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10805 {"zvdotphsuian",      VX(4, 0x6C4), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10806 {"zvdotphsuians",     VX(4, 0x6C5), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10807 {"zvdotphssi",	      VX(4, 0x6C8), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10808 {"zvdotphssis",	      VX(4, 0x6C9), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10809 {"zvdotphssiaa",      VX(4, 0x6CA), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10810 {"zvdotphssiaas",     VX(4, 0x6CB), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10811 {"zvdotphssian",      VX(4, 0x6CC), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10812 {"zvdotphssians",     VX(4, 0x6CD), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10813 {"zvdotphssui",	      VX(4, 0x6D0), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10814 {"zvdotphssuis",      VX(4, 0x6D1), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10815 {"zvdotphssuiaa",     VX(4, 0x6D2), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10816 {"zvdotphssuiaas",    VX(4, 0x6D3), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10817 {"zvdotphssuian",     VX(4, 0x6D4), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10818 {"zvdotphssuians",    VX(4, 0x6D5), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10819 {"zvdotphssfs",	      VX(4, 0x6D8), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10820 {"zvdotphssfrs",      VX(4, 0x6D9), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10821 {"zvdotphssfaas",     VX(4, 0x6DA), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10822 {"zvdotphssfraas",    VX(4, 0x6DB), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10823 {"zvdotphssfans",     VX(4, 0x6DC), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10824 {"zvdotphssfrans",    VX(4, 0x6DD), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10825 {"zmwluis",	      VX(4, 0x6E1), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10826 {"zmwluiaa",	      VX(4, 0x6E2), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10827 {"zmwluiaas",	      VX(4, 0x6E3), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10828 {"zmwluian",	      VX(4, 0x6E4), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10829 {"zmwluians",	      VX(4, 0x6E5), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10830 {"zmwlsis",	      VX(4, 0x6E9), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10831 {"zmwlsiaas",	      VX(4, 0x6EB), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10832 {"zmwlsians",	      VX(4, 0x6ED), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10833 {"zmwlsuis",	      VX(4, 0x6F1), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10834 {"zmwlsuiaas",	      VX(4, 0x6F3), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10835 {"zmwlsuians",	      VX(4, 0x6F5), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10836 {"zmwsf",	      VX(4, 0x6F8), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10837 {"zmwsfr",	      VX(4, 0x6F9), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10838 {"zmwsfaas",	      VX(4, 0x6FA), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10839 {"zmwsfraas",	      VX(4, 0x6FB), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10840 {"zmwsfans",	      VX(4, 0x6FC), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10841 {"zmwsfrans",	      VX(4, 0x6FD), VX_MASK,	PPCLSP, 0,		{RD, RA, RB}},
10848 {"evdotpwcssi",		  VX (4, 128),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10849 {"evdotpwcsmi",		  VX (4, 129),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10850 {"evdotpwcssfr",	  VX (4, 130),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10851 {"evdotpwcssf",		  VX (4, 131),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10852 {"evdotpwgasmf",	  VX (4, 136),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10853 {"evdotpwxgasmf",	  VX (4, 137),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10854 {"evdotpwgasmfr",	  VX (4, 138),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10855 {"evdotpwxgasmfr",	  VX (4, 139),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10856 {"evdotpwgssmf",	  VX (4, 140),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10857 {"evdotpwxgssmf",	  VX (4, 141),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10858 {"evdotpwgssmfr",	  VX (4, 142),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10859 {"evdotpwxgssmfr",	  VX (4, 143),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10860 {"evdotpwcssiaaw3",	  VX (4, 144),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10861 {"evdotpwcsmiaaw3",	  VX (4, 145),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10862 {"evdotpwcssfraaw3",	  VX (4, 146),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10863 {"evdotpwcssfaaw3",	  VX (4, 147),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10864 {"evdotpwgasmfaa3",	  VX (4, 152),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10865 {"evdotpwxgasmfaa3",	  VX (4, 153),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10866 {"evdotpwgasmfraa3",	  VX (4, 154),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10867 {"evdotpwxgasmfraa3",	  VX (4, 155),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10868 {"evdotpwgssmfaa3",	  VX (4, 156),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10869 {"evdotpwxgssmfaa3",	  VX (4, 157),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10870 {"evdotpwgssmfraa3",	  VX (4, 158),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10871 {"evdotpwxgssmfraa3",	  VX (4, 159),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10872 {"evdotpwcssia",	  VX (4, 160),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10873 {"evdotpwcsmia",	  VX (4, 161),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10874 {"evdotpwcssfra",	  VX (4, 162),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10875 {"evdotpwcssfa",	  VX (4, 163),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10876 {"evdotpwgasmfa",	  VX (4, 168),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10877 {"evdotpwxgasmfa",	  VX (4, 169),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10878 {"evdotpwgasmfra",	  VX (4, 170),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10879 {"evdotpwxgasmfra",	  VX (4, 171),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10880 {"evdotpwgssmfa",	  VX (4, 172),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10881 {"evdotpwxgssmfa",	  VX (4, 173),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10882 {"evdotpwgssmfra",	  VX (4, 174),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10883 {"evdotpwxgssmfra",	  VX (4, 175),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10884 {"evdotpwcssiaaw",	  VX (4, 176),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10885 {"evdotpwcsmiaaw",	  VX (4, 177),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10886 {"evdotpwcssfraaw",	  VX (4, 178),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10887 {"evdotpwcssfaaw",	  VX (4, 179),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10888 {"evdotpwgasmfaa",	  VX (4, 184),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10889 {"evdotpwxgasmfaa",	  VX (4, 185),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10890 {"evdotpwgasmfraa",	  VX (4, 186),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10891 {"evdotpwxgasmfraa",	  VX (4, 187),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10892 {"evdotpwgssmfaa",	  VX (4, 188),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10893 {"evdotpwxgssmfaa",	  VX (4, 189),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10894 {"evdotpwgssmfraa",	  VX (4, 190),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10895 {"evdotpwxgssmfraa",	  VX (4, 191),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10896 {"evdotphihcssi",	  VX (4, 256),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10897 {"evdotplohcssi",	  VX (4, 257),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10898 {"evdotphihcssf",	  VX (4, 258),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10899 {"evdotplohcssf",	  VX (4, 259),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10900 {"evdotphihcsmi",	  VX (4, 264),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10901 {"evdotplohcsmi",	  VX (4, 265),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10902 {"evdotphihcssfr",	  VX (4, 266),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10903 {"evdotplohcssfr",	  VX (4, 267),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10904 {"evdotphihcssiaaw3",	  VX (4, 272),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10905 {"evdotplohcssiaaw3",	  VX (4, 273),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10906 {"evdotphihcssfaaw3",	  VX (4, 274),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10907 {"evdotplohcssfaaw3",	  VX (4, 275),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10908 {"evdotphihcsmiaaw3",	  VX (4, 280),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10909 {"evdotplohcsmiaaw3",	  VX (4, 281),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10910 {"evdotphihcssfraaw3",	  VX (4, 282),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10911 {"evdotplohcssfraaw3",	  VX (4, 283),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10912 {"evdotphihcssia",	  VX (4, 288),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10913 {"evdotplohcssia",	  VX (4, 289),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10914 {"evdotphihcssfa",	  VX (4, 290),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10915 {"evdotplohcssfa",	  VX (4, 291),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10916 {"evdotphihcsmia",	  VX (4, 296),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10917 {"evdotplohcsmia",	  VX (4, 297),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10918 {"evdotphihcssfra",	  VX (4, 298),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10919 {"evdotplohcssfra",	  VX (4, 299),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10920 {"evdotphihcssiaaw",	  VX (4, 304),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10921 {"evdotplohcssiaaw",	  VX (4, 305),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10922 {"evdotphihcssfaaw",	  VX (4, 306),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10923 {"evdotplohcssfaaw",	  VX (4, 307),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10924 {"evdotphihcsmiaaw",	  VX (4, 312),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10925 {"evdotplohcsmiaaw",	  VX (4, 313),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10926 {"evdotphihcssfraaw",	  VX (4, 314),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10927 {"evdotplohcssfraaw",	  VX (4, 315),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10928 {"evdotphausi",		  VX (4, 320),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10929 {"evdotphassi",		  VX (4, 321),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10930 {"evdotphasusi",	  VX (4, 322),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10931 {"evdotphassf",		  VX (4, 323),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10932 {"evdotphsssf",		  VX (4, 327),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10933 {"evdotphaumi",		  VX (4, 328),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10934 {"evdotphasmi",		  VX (4, 329),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10935 {"evdotphasumi",	  VX (4, 330),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10936 {"evdotphassfr",	  VX (4, 331),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10937 {"evdotphssmi",		  VX (4, 333),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10938 {"evdotphsssi",		  VX (4, 333),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10939 {"evdotphsssfr",	  VX (4, 335),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10940 {"evdotphausiaaw3",	  VX (4, 336),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10941 {"evdotphassiaaw3",	  VX (4, 337),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10942 {"evdotphasusiaaw3",	  VX (4, 338),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10943 {"evdotphassfaaw3",	  VX (4, 339),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10944 {"evdotphsssiaaw3",	  VX (4, 341),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10945 {"evdotphsssfaaw3",	  VX (4, 343),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10946 {"evdotphaumiaaw3",	  VX (4, 344),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10947 {"evdotphasmiaaw3",	  VX (4, 345),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10948 {"evdotphasumiaaw3",	  VX (4, 346),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10949 {"evdotphassfraaw3",	  VX (4, 347),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10950 {"evdotphssmiaaw3",	  VX (4, 349),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10951 {"evdotphsssfraaw3",	  VX (4, 351),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10952 {"evdotphausia",	  VX (4, 352),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10953 {"evdotphassia",	  VX (4, 353),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10954 {"evdotphasusia",	  VX (4, 354),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10955 {"evdotphassfa",	  VX (4, 355),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10956 {"evdotphsssfa",	  VX (4, 359),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10957 {"evdotphaumia",	  VX (4, 360),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10958 {"evdotphasmia",	  VX (4, 361),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10959 {"evdotphasumia",	  VX (4, 362),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10960 {"evdotphassfra",	  VX (4, 363),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10961 {"evdotphssmia",	  VX (4, 365),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10962 {"evdotphsssia",	  VX (4, 365),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10963 {"evdotphsssfra",	  VX (4, 367),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10964 {"evdotphausiaaw",	  VX (4, 368),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10965 {"evdotphassiaaw",	  VX (4, 369),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10966 {"evdotphasusiaaw",	  VX (4, 370),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10967 {"evdotphassfaaw",	  VX (4, 371),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10968 {"evdotphsssiaaw",	  VX (4, 373),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10969 {"evdotphsssfaaw",	  VX (4, 375),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10970 {"evdotphaumiaaw",	  VX (4, 376),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10971 {"evdotphasmiaaw",	  VX (4, 377),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10972 {"evdotphasumiaaw",	  VX (4, 378),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10973 {"evdotphassfraaw",	  VX (4, 379),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10974 {"evdotphssmiaaw",	  VX (4, 381),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10975 {"evdotphsssfraaw",	  VX (4, 383),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10976 {"evdotp4hgaumi",	  VX (4, 384),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10977 {"evdotp4hgasmi",	  VX (4, 385),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10978 {"evdotp4hgasumi",	  VX (4, 386),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10979 {"evdotp4hgasmf",	  VX (4, 387),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10980 {"evdotp4hgssmi",	  VX (4, 388),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10981 {"evdotp4hgssmf",	  VX (4, 389),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10982 {"evdotp4hxgasmi",	  VX (4, 390),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10983 {"evdotp4hxgasmf",	  VX (4, 391),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10984 {"evdotpbaumi",		  VX (4, 392),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10985 {"evdotpbasmi",		  VX (4, 393),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10986 {"evdotpbasumi",	  VX (4, 394),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10987 {"evdotp4hxgssmi",	  VX (4, 398),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10988 {"evdotp4hxgssmf",	  VX (4, 399),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10989 {"evdotp4hgaumiaa3",	  VX (4, 400),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10990 {"evdotp4hgasmiaa3",	  VX (4, 401),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10991 {"evdotp4hgasumiaa3",	  VX (4, 402),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10992 {"evdotp4hgasmfaa3",	  VX (4, 403),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10993 {"evdotp4hgssmiaa3",	  VX (4, 404),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10994 {"evdotp4hgssmfaa3",	  VX (4, 405),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10995 {"evdotp4hxgasmiaa3",	  VX (4, 406),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10996 {"evdotp4hxgasmfaa3",	  VX (4, 407),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10997 {"evdotpbaumiaaw3",	  VX (4, 408),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10998 {"evdotpbasmiaaw3",	  VX (4, 409),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
10999 {"evdotpbasumiaaw3",	  VX (4, 410),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11000 {"evdotp4hxgssmiaa3",	  VX (4, 414),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11001 {"evdotp4hxgssmfaa3",	  VX (4, 415),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11002 {"evdotp4hgaumia",	  VX (4, 416),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11003 {"evdotp4hgasmia",	  VX (4, 417),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11004 {"evdotp4hgasumia",	  VX (4, 418),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11005 {"evdotp4hgasmfa",	  VX (4, 419),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11006 {"evdotp4hgssmia",	  VX (4, 420),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11007 {"evdotp4hgssmfa",	  VX (4, 421),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11008 {"evdotp4hxgasmia",	  VX (4, 422),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11009 {"evdotp4hxgasmfa",	  VX (4, 423),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11010 {"evdotpbaumia",	  VX (4, 424),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11011 {"evdotpbasmia",	  VX (4, 425),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11012 {"evdotpbasumia",	  VX (4, 426),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11013 {"evdotp4hxgssmia",	  VX (4, 430),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11014 {"evdotp4hxgssmfa",	  VX (4, 431),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11015 {"evdotp4hgaumiaa",	  VX (4, 432),		VX_MASK,		PPCSPE2, 0, {RD, RA
11016 {"evdotp4hgasmiaa",	  VX (4, 433),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11017 {"evdotp4hgasumiaa",	  VX (4, 434),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11018 {"evdotp4hgasmfaa",	  VX (4, 435),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11019 {"evdotp4hgssmiaa",	  VX (4, 436),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11020 {"evdotp4hgssmfaa",	  VX (4, 437),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11021 {"evdotp4hxgasmiaa",	  VX (4, 438),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11022 {"evdotp4hxgasmfaa",	  VX (4, 439),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11023 {"evdotpbaumiaaw",	  VX (4, 440),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11024 {"evdotpbasmiaaw",	  VX (4, 441),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11025 {"evdotpbasumiaaw",	  VX (4, 442),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11026 {"evdotp4hxgssmiaa",	  VX (4, 446),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11027 {"evdotp4hxgssmfaa",	  VX (4, 447),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11028 {"evdotpwausi",		  VX (4, 448),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11029 {"evdotpwassi",		  VX (4, 449),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11030 {"evdotpwasusi",	  VX (4, 450),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11031 {"evdotpwaumi",		  VX (4, 456),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11032 {"evdotpwasmi",		  VX (4, 457),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11033 {"evdotpwasumi",	  VX (4, 458),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11034 {"evdotpwssmi",		  VX (4, 461),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11035 {"evdotpwsssi",		  VX (4, 461),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11036 {"evdotpwausiaa3",	  VX (4, 464),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11037 {"evdotpwassiaa3",	  VX (4, 465),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11038 {"evdotpwasusiaa3",	  VX (4, 466),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11039 {"evdotpwsssiaa3",	  VX (4, 469),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11040 {"evdotpwaumiaa3",	  VX (4, 472),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11041 {"evdotpwasmiaa3",	  VX (4, 473),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11042 {"evdotpwasumiaa3",	  VX (4, 474),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11043 {"evdotpwssmiaa3",	  VX (4, 477),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11044 {"evdotpwausia",	  VX (4, 480),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11045 {"evdotpwassia",	  VX (4, 481),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11046 {"evdotpwasusia",	  VX (4, 482),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11047 {"evdotpwaumia",	  VX (4, 488),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11048 {"evdotpwasmia",	  VX (4, 489),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11049 {"evdotpwasumia",	  VX (4, 490),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11050 {"evdotpwssmia",	  VX (4, 493),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11051 {"evdotpwsssia",	  VX (4, 493),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11052 {"evdotpwausiaa",	  VX (4, 496),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11053 {"evdotpwassiaa",	  VX (4, 497),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11054 {"evdotpwasusiaa",	  VX (4, 498),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11055 {"evdotpwsssiaa",	  VX (4, 501),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11056 {"evdotpwaumiaa",	  VX (4, 504),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11057 {"evdotpwasmiaa",	  VX (4, 505),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11058 {"evdotpwasumiaa",	  VX (4, 506),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11059 {"evdotpwssmiaa",	  VX (4, 509),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11064 {"evabsb",		  VX_RB_CONST(4, 520, 2),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11065 {"evabsh",		  VX_RB_CONST(4, 520, 4),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11066 {"evabsd",		  VX_RB_CONST(4, 520, 6),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11067 {"evabss",		  VX_RB_CONST(4, 520, 8),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11068 {"evabsbs",		  VX_RB_CONST(4, 520, 10), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11069 {"evabshs",		  VX_RB_CONST(4, 520, 12), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11070 {"evabsds",		  VX_RB_CONST(4, 520, 14), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11071 {"evnegwo",		  VX_RB_CONST(4, 521, 1),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11072 {"evnegb",		  VX_RB_CONST(4, 521, 2),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11073 {"evnegbo",		  VX_RB_CONST(4, 521, 3),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11074 {"evnegh",		  VX_RB_CONST(4, 521, 4),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11075 {"evnegho",		  VX_RB_CONST(4, 521, 5),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11076 {"evnegd",		  VX_RB_CONST(4, 521, 6),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11077 {"evnegs",		  VX_RB_CONST(4, 521, 8),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11078 {"evnegwos",		  VX_RB_CONST(4, 521, 9),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11079 {"evnegbs",		  VX_RB_CONST(4, 521, 10), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11080 {"evnegbos",		  VX_RB_CONST(4, 521, 11), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11081 {"evneghs",		  VX_RB_CONST(4, 521, 12), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11082 {"evneghos",		  VX_RB_CONST(4, 521, 13), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11083 {"evnegds",		  VX_RB_CONST(4, 521, 14), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11084 {"evextzb",		  VX_RB_CONST(4, 522, 1),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11085 {"evextsbh",		  VX_RB_CONST(4, 522, 4),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11086 {"evextsw",		  VX_RB_CONST(4, 523, 6),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11087 {"evrndwh",		  VX_RB_CONST(4, 524, 0),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11088 {"evrndhb",		  VX_RB_CONST(4, 524, 4),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11089 {"evrnddw",		  VX_RB_CONST(4, 524, 6),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11090 {"evrndwhus",		  VX_RB_CONST(4, 524, 8),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11091 {"evrndwhss",		  VX_RB_CONST(4, 524, 9),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11092 {"evrndhbus",		  VX_RB_CONST(4, 524, 12), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11093 {"evrndhbss",		  VX_RB_CONST(4, 524, 13), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11094 {"evrnddwus",		  VX_RB_CONST(4, 524, 14), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11095 {"evrnddwss",		  VX_RB_CONST(4, 524, 15), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11096 {"evrndwnh",		  VX_RB_CONST(4, 524, 16), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11097 {"evrndhnb",		  VX_RB_CONST(4, 524, 20), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11098 {"evrnddnw",		  VX_RB_CONST(4, 524, 22), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11099 {"evrndwnhus",		  VX_RB_CONST(4, 524, 24), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11100 {"evrndwnhss",		  VX_RB_CONST(4, 524, 25), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11101 {"evrndhnbus",		  VX_RB_CONST(4, 524, 28), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11102 {"evrndhnbss",		  VX_RB_CONST(4, 524, 29), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11103 {"evrnddnwus",		  VX_RB_CONST(4, 524, 30), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11104 {"evrnddnwss",		  VX_RB_CONST(4, 524, 31), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11105 {"evcntlzh",		  VX_RB_CONST(4, 525, 4),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11106 {"evcntlsh",		  VX_RB_CONST(4, 526, 4),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11107 {"evpopcntb",		  VX_RB_CONST(4, 526, 26), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11108 {"circinc",		  VX (4, 528),		   VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11109 {"evunpkhibui",		  VX_RB_CONST(4, 540, 0),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11110 {"evunpkhibsi",		  VX_RB_CONST(4, 540, 1),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11111 {"evunpkhihui",		  VX_RB_CONST(4, 540, 2),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11112 {"evunpkhihsi",		  VX_RB_CONST(4, 540, 3),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11113 {"evunpklobui",		  VX_RB_CONST(4, 540, 4),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11114 {"evunpklobsi",		  VX_RB_CONST(4, 540, 5),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11115 {"evunpklohui",		  VX_RB_CONST(4, 540, 6),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11116 {"evunpklohsi",		  VX_RB_CONST(4, 540, 7),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11117 {"evunpklohf",		  VX_RB_CONST(4, 540, 8),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11118 {"evunpkhihf",		  VX_RB_CONST(4, 540, 9),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11119 {"evunpklowgsf",	  VX_RB_CONST(4, 540, 12), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11120 {"evunpkhiwgsf",	  VX_RB_CONST(4, 540, 13), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11121 {"evsatsduw",		  VX_RB_CONST(4, 540, 16), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11122 {"evsatsdsw",		  VX_RB_CONST(4, 540, 17), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11123 {"evsatshub",		  VX_RB_CONST(4, 540, 18), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11124 {"evsatshsb",		  VX_RB_CONST(4, 540, 19), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11125 {"evsatuwuh",		  VX_RB_CONST(4, 540, 20), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11126 {"evsatswsh",		  VX_RB_CONST(4, 540, 21), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11127 {"evsatswuh",		  VX_RB_CONST(4, 540, 22), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11128 {"evsatuhub",		  VX_RB_CONST(4, 540, 23), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11129 {"evsatuduw",		  VX_RB_CONST(4, 540, 24), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11130 {"evsatuwsw",		  VX_RB_CONST(4, 540, 25), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11131 {"evsatshuh",		  VX_RB_CONST(4, 540, 26), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11132 {"evsatuhsh",		  VX_RB_CONST(4, 540, 27), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11133 {"evsatswuw",		  VX_RB_CONST(4, 540, 28), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11134 {"evsatswgsdf",		  VX_RB_CONST(4, 540, 29), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11135 {"evsatsbub",		  VX_RB_CONST(4, 540, 30), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11136 {"evsatubsb",		  VX_RB_CONST(4, 540, 31), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11137 {"evmaxhpuw",		  VX_RB_CONST(4, 541, 0),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11138 {"evmaxhpsw",		  VX_RB_CONST(4, 541, 1),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11139 {"evmaxbpuh",		  VX_RB_CONST(4, 541, 4),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11140 {"evmaxbpsh",		  VX_RB_CONST(4, 541, 5),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11141 {"evmaxwpud",		  VX_RB_CONST(4, 541, 6),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11142 {"evmaxwpsd",		  VX_RB_CONST(4, 541, 7),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11143 {"evminhpuw",		  VX_RB_CONST(4, 541, 8),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11144 {"evminhpsw",		  VX_RB_CONST(4, 541, 9),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11145 {"evminbpuh",		  VX_RB_CONST(4, 541, 12), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11146 {"evminbpsh",		  VX_RB_CONST(4, 541, 13), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11147 {"evminwpud",		  VX_RB_CONST(4, 541, 14), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11148 {"evminwpsd",		  VX_RB_CONST(4, 541, 15), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11149 {"evmaxmagws",		  VX (4, 543),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11150 {"evsl",		  VX (4, 549),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11151 {"evsli",		  VX (4, 551),		VX_MASK,		PPCSPE2, 0, {RD, RA, EVUIMM}},
11178 {"evcmpgtdu",		  VX_SPE_CRFD (4, 560, 1), VX_SPE_CRFD_MASK,	PPCSPE2, 0, {CRFD, RA, RB}},
11179 {"evcmpgtds",		  VX_SPE_CRFD (4, 561, 1), VX_SPE_CRFD_MASK,	PPCSPE2, 0, {CRFD, RA, RB}},
11180 {"evcmpltdu",		  VX_SPE_CRFD (4, 562, 1), VX_SPE_CRFD_MASK,	PPCSPE2, 0, {CRFD, RA, RB}},
11181 {"evcmpltds",		  VX_SPE_CRFD (4, 563, 1), VX_SPE_CRFD_MASK,	PPCSPE2, 0, {CRFD, RA, RB}},
11182 {"evcmpeqd",		  VX_SPE_CRFD (4, 564, 1), VX_SPE_CRFD_MASK,	PPCSPE2, 0, {CRFD, RA, RB}},
11183 {"evswapbhilo",		  VX (4, 568),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11184 {"evswapblohi",		  VX (4, 569),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11185 {"evswaphhilo",		  VX (4, 570),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11186 {"evswaphlohi",		  VX (4, 571),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11187 {"evswaphe",		  VX (4, 572),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11188 {"evswaphhi",		  VX (4, 573),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11189 {"evswaphlo",		  VX (4, 574),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11190 {"evswapho",		  VX (4, 575),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11191 {"evinsb",		  VX (4, 584),		VX_MASK_DDD,		PPCSPE2, 0, {RD, RA, DDD, BBB}},
11192 {"evxtrb",		  VX (4, 586),		VX_MASK_DDD,		PPCSPE2, 0, {RD, RA, DDD, BBB}},
11193 {"evsplath",		  VX_SPE2_HH (4, 588, 0, 0), VX_SPE2_HH_MASK,	PPCSPE2, 0, {RD, RA, HH}},
11194 {"evsplatb",		  VX_SPE2_SPLATB (4, 588, 2), VX_SPE2_SPLATB_MASK, PPCSPE2, 0, {RD, RA, BBB}},
11195 {"evinsh",		  VX_SPE2_DDHH (4, 589, 0), VX_SPE2_DDHH_MASK,	PPCSPE2, 0, {RD, RA, DD, HH}},
11196 {"evclrbe",		  VX_SPE2_CLR (4, 590, 0), VX_SPE2_CLR_MASK,	PPCSPE2, 0, {RD, RA, MMMM}},
11197 {"evclrbo",		  VX_SPE2_CLR (4, 590, 1), VX_SPE2_CLR_MASK,	PPCSPE2, 0, {RD, RA, MMMM}},
11198 {"evclrh",		  VX_SPE2_CLR (4, 591, 1), VX_SPE2_CLR_MASK,	PPCSPE2, 0, {RD, RA, MMMM}},
11199 {"evxtrh",		  VX_SPE2_DDHH (4, 591, 0), VX_SPE2_DDHH_MASK,	PPCSPE2, 0, {RD, RA, DD, HH}},
11200 {"evselbitm0",		  VX (4, 592),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11201 {"evselbitm1",		  VX (4, 593),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11202 {"evselbit",		  VX (4, 594),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11203 {"evperm",		  VX (4, 596),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11204 {"evperm2",		  VX (4, 597),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11205 {"evperm3",		  VX (4, 598),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11206 {"evxtrd",		  VX (4, 600),		VX_OFF_SPE2_MASK,	PPCSPE2, 0, {RD, RA, RB, VX_OFF_SPE2}},
11207 {"evsrbu",		  VX (4, 608),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11208 {"evsrbs",		  VX (4, 609),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11209 {"evsrbiu",		  VX (4, 610),		VX_MASK,		PPCSPE2, 0, {RD, RA, EVUIMM_LT8}},
11210 {"evsrbis",		  VX (4, 611),		VX_MASK,		PPCSPE2, 0, {RD, RA, EVUIMM_LT8}},
11211 {"evslb",		  VX (4, 612),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11212 {"evrlb",		  VX (4, 613),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11213 {"evslbi",		  VX (4, 614),		VX_MASK,		PPCSPE2, 0, {RD, RA, EVUIMM_LT8}},
11214 {"evrlbi",		  VX (4, 615),		VX_MASK,		PPCSPE2, 0, {RD, RA, EVUIMM_LT8}},
11215 {"evsrhu",		  VX (4, 616),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11216 {"evsrhs",		  VX (4, 617),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11217 {"evsrhiu",		  VX (4, 618),		VX_MASK,		PPCSPE2, 0, {RD, RA, EVUIMM_LT16}},
11218 {"evsrhis",		  VX (4, 619),		VX_MASK,		PPCSPE2, 0, {RD, RA, EVUIMM_LT16}},
11219 {"evslh",		  VX (4, 620),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11220 {"evrlh",		  VX (4, 621),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11221 {"evslhi",		  VX (4, 622),		VX_MASK,		PPCSPE2, 0, {RD, RA, EVUIMM_LT16}},
11222 {"evrlhi",		  VX (4, 623),		VX_MASK,		PPCSPE2, 0, {RD, RA, EVUIMM_LT16}},
11223 {"evsru",		  VX (4, 624),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11224 RA, RB}},
11225 {"evsriu",		  VX (4, 626),		VX_MASK,		PPCSPE2, 0, {RD, RA, EVUIMM}},
11226 {"evsris",		  VX (4, 627),		VX_MASK,		PPCSPE2, 0, {RD, RA, EVUIMM}},
11227 {"evlvsl",		  VX (4, 628),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11228 {"evlvsr",		  VX (4, 629),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11229 {"evsroiu",		  VX_SPE2_OCTET (4, 631, 0), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}},
11230 {"evsrois",		  VX_SPE2_OCTET (4, 631, 1), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}},
11231 {"evsloi",		  VX_SPE2_OCTET (4, 631, 2), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}},
11232 {"evldbx",		  VX (4, 774),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11233 {"evldb",		  VX (4, 775),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_8, RA}},
11234 {"evlhhsplathx",	  VX (4, 778),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11235 {"evlhhsplath",		  VX (4, 779),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_2, RA}},
11236 {"evlwbsplatwx",	  VX (4, 786),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11237 {"evlwbsplatw",		  VX (4, 787),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_4, RA}},
11238 {"evlwhsplatwx",	  VX (4, 794),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11239 {"evlwhsplatw",		  VX (4, 795),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_4, RA}},
11240 {"evlbbsplatbx",	  VX (4, 798),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11241 {"evlbbsplatb",		  VX (4, 799),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_1, RA}},
11242 {"evstdbx",		  VX (4, 806),		VX_MASK,		PPCSPE2, 0, {RS, RA, RB}},
11243 {"evstdb",		  VX (4, 807),		VX_MASK,		PPCSPE2, 0, {RS, EVUIMM_8, RA}},
11244 {"evlwbex",		  VX (4, 810),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11245 {"evlwbe",		  VX (4, 811),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_4, RA}},
11246 {"evlwboux",		  VX (4, 812),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11247 {"evlwbou",		  VX (4, 813),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_4, RA}},
11248 {"evlwbosx",		  VX (4, 814),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11249 {"evlwbos",		  VX (4, 815),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_4, RA}},
11250 {"evstwbex",		  VX (4, 818),		VX_MASK,		PPCSPE2, 0, {RS, RA, RB}},
11251 {"evstwbe",		  VX (4, 819),		VX_MASK,		PPCSPE2, 0, {RS, EVUIMM_4, RA}},
11252 {"evstwbox",		  VX (4, 822),		VX_MASK,		PPCSPE2, 0, {RS, RA, RB}},
11253 {"evstwbo",		  VX (4, 823),		VX_MASK,		PPCSPE2, 0, {RS, EVUIMM_4, RA}},
11254 {"evstwbx",		  VX (4, 826),		VX_MASK,		PPCSPE2, 0, {RS, RA, RB}},
11255 {"evstwb",		  VX (4, 827),		VX_MASK,		PPCSPE2, 0, {RS, EVUIMM_4, RA}},
11256 {"evsthbx",		  VX (4, 830),		VX_MASK,		PPCSPE2, 0, {RS, RA, RB}},
11257 {"evsthb",		  VX (4, 831),		VX_MASK,		PPCSPE2, 0, {RS, EVUIMM_2, RA}},
11258 {"evlddmx",		  VX (4, 832),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11259 {"evlddu",		  VX (4, 833),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}},
11260 {"evldwmx",		  VX (4, 834),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11261 {"evldwu",		  VX (4, 835),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}},
11262 {"evldhmx",		  VX (4, 836),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11263 {"evldhu",		  VX (4, 837),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}},
11264 {"evldbmx",		  VX (4, 838),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11265 {"evldbu",		  VX (4, 839),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}},
11266 {"evlhhesplatmx",	  VX (4, 840),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11267 {"evlhhesplatu",	  VX (4, 841),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}},
11268 {"evlhhsplathmx",	  VX (4, 842),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11269 {"evlhhsplathu",	  VX (4, 843),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}},
11270 {"evlhhousplatmx",	  VX (4, 844),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11271 {"evlhhousplatu",	  VX (4, 845),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}},
11272 {"evlhhossplatmx",	  VX (4, 846),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11273 {"evlhhossplatu",	  VX (4, 847),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}},
11274 {"evlwhemx",		  VX (4, 848),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11275 {"evlwheu",		  VX (4, 849),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
11276 {"evlwbsplatwmx",	  VX (4, 850),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11277 {"evlwbsplatwu",	  VX (4, 851),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
11278 {"evlwhoumx",		  VX (4, 852),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11279 {"evlwhouu",		  VX (4, 853),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
11280 {"evlwhosmx",		  VX (4, 854),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11281 {"evlwhosu",		  VX (4, 855),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
11282 {"evlwwsplatmx",	  VX (4, 856),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11283 {"evlwwsplatu",		  VX (4, 857),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
11284 {"evlwhsplatwmx",	  VX (4, 858),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11285 {"evlwhsplatwu",	  VX (4, 859),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
11286 {"evlwhsplatmx",	  VX (4, 860),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11287 {"evlwhsplatu",		  VX (4, 861),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
11288 {"evlbbsplatbmx",	  VX (4, 862),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11289 {"evlbbsplatbu",	  VX (4, 863),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_1_EX0, RA}},
11290 {"evstddmx",		  VX (4, 864),		VX_MASK,		PPCSPE2, 0, {RS, RA, RB}},
11291 {"evstddu",		  VX (4, 865),		VX_MASK,		PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}},
11292 {"evstdwmx",		  VX (4, 866),		VX_MASK,		PPCSPE2, 0, {RS, RA, RB}},
11293 {"evstdwu",		  VX (4, 867),		VX_MASK,		PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}},
11294 {"evstdhmx",		  VX (4, 868),		VX_MASK,		PPCSPE2, 0, {RS, RA, RB}},
11295 {"evstdhu",		  VX (4, 869),		VX_MASK,		PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}},
11296 {"evstdbmx",		  VX (4, 870),		VX_MASK,		PPCSPE2, 0, {RS, RA, RB}},
11297 {"evstdbu",		  VX (4, 871),		VX_MASK,		PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}},
11298 {"evlwbemx",		  VX (4, 874),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11299 {"evlwbeu",		  VX (4, 875),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
11300 {"evlwboumx",		  VX (4, 876),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11301 {"evlwbouu",		  VX (4, 877),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
11302 {"evlwbosmx",		  VX (4, 878),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11303 {"evlwbosu",		  VX (4, 879),		VX_MASK,		PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
11304 {"evstwhemx",		  VX (4, 880),		VX_MASK,		PPCSPE2, 0, {RS, RA, RB}},
11305 {"evstwheu",		  VX (4, 881),		VX_MASK,		PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
11306 {"evstwbemx",		  VX (4, 882),		VX_MASK,		PPCSPE2, 0, {RS, RA, RB}},
11307 {"evstwbeu",		  VX (4, 883),		VX_MASK,		PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
11308 {"evstwhomx",		  VX (4, 884),		VX_MASK,		PPCSPE2, 0, {RS, RA, RB}},
11309 {"evstwhou",		  VX (4, 885),		VX_MASK,		PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
11310 {"evstwbomx",		  VX (4, 886),		VX_MASK,		PPCSPE2, 0, {RS, RA, RB}},
11311 {"evstwbou",		  VX (4, 887),		VX_MASK,		PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
11312 {"evstwwemx",		  VX (4, 888),		VX_MASK,		PPCSPE2, 0, {RS, RA, RB}},
11313 {"evstwweu",		  VX (4, 889),		VX_MASK,		PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
11314 {"evstwbmx",		  VX (4, 890),		VX_MASK,		PPCSPE2, 0, {RS, RA, RB}},
11315 {"evstwbu",		  VX (4, 891),		VX_MASK,		PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
11316 {"evstwwomx",		  VX (4, 892),		VX_MASK,		PPCSPE2, 0, {RS, RA, RB}},
11317 {"evstwwou",		  VX (4, 893),		VX_MASK,		PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
11318 {"evsthbmx",		  VX (4, 894),		VX_MASK,		PPCSPE2, 0, {RS, RA, RB}},
11319 {"evsthbu",		  VX (4, 895),		VX_MASK,		PPCSPE2, 0, {RS, EVUIMM_2_EX0, RA}},
11320 {"evmhusi",		  VX (4, 1024),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11321 {"evmhssi",		  VX (4, 1025),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11322 {"evmhsusi",		  VX (4, 1026),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11323 {"evmhssf",		  VX (4, 1028),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11324 {"evmhumi",		  VX (4, 1029),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11325 {"evmhssfr",		  VX (4, 1030),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11326 {"evmhesumi",		  VX (4, 1034),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11327 {"evmhosumi",		  VX (4, 1038),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11328 {"evmbeumi",		  VX (4, 1048),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11329 {"evmbesmi",		  VX (4, 1049),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11330 {"evmbesumi",		  VX (4, 1050),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11331 {"evmboumi",		  VX (4, 1052),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11332 {"evmbosmi",		  VX (4, 1053),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11333 {"evmbosumi",		  VX (4, 1054),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11334 {"evmhesumia",		  VX (4, 1066),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11335 {"evmhosumia",		  VX (4, 1070),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11336 {"evmbeumia",		  VX (4, 1080),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11337 {"evmbesmia",		  VX (4, 1081),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11338 {"evmbesumia",		  VX (4, 1082),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11339 {"evmboumia",		  VX (4, 1084),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11340 {"evmbosmia",		  VX (4, 1085),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11341 {"evmbosumia",		  VX (4, 1086),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11342 {"evmwusiw",		  VX (4, 1088),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11343 {"evmwssiw",		  VX (4, 1089),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11344 {"evmwhssfr",		  VX (4, 1094),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11345 {"evmwehgsmfr",		  VX (4, 1110),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11346 {"evmwehgsmf",		  VX (4, 1111),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11347 {"evmwohgsmfr",		  VX (4, 1118),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11348 {"evmwohgsmf",		  VX (4, 1119),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11349 {"evmwhssfra",		  VX (4, 1126),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11350 {"evmwehgsmfra",	  VX (4, 1142),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11351 {"evmwehgsmfa",		  VX (4, 1143),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11352 {"evmwohgsmfra",	  VX (4, 1150),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11353 {"evmwohgsmfa",		  VX (4, 1151),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11354 {"evaddusiaa",		  VX_RB_CONST(4, 1152, 0), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11355 {"evaddssiaa",		  VX_RB_CONST(4, 1153, 0), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11356 {"evsubfusiaa",		  VX_RB_CONST(4, 1154, 0), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11357 {"evsubfssiaa",		  VX_RB_CONST(4, 1155, 0), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11358 {"evaddsmiaa",		  VX_RB_CONST(4, 1156, 0), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11359 {"evsubfsmiaa",		  VX_RB_CONST(4, 1158, 0), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11360 {"evaddh",		  VX (4, 1160),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11361 {"evaddhss",		  VX (4, 1161),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11362 {"evsubfh",		  VX (4, 1162),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11363 {"evsubfhss",		  VX (4, 1163),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11364 {"evaddhx",		  VX (4, 1164),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11365 {"evaddhxss",		  VX (4, 1165),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11366 {"evsubfhx",		  VX (4, 1166),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11367 {"evsubfhxss",		  VX (4, 1167),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11368 {"evaddd",		  VX (4, 1168),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11369 {"evadddss",		  VX (4, 1169),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11370 {"evsubfd",		  VX (4, 1170),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11371 {"evsubfdss",		  VX (4, 1171),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11372 {"evaddb",		  VX (4, 1172),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11373 {"evaddbss",		  VX (4, 1173),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11374 {"evsubfb",		  VX (4, 1174),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11375 {"evsubfbss",		  VX (4, 1175),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11376 {"evaddsubfh",		  VX (4, 1176),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11377 {"evaddsubfhss",	  VX (4, 1177),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11378 {"evsubfaddh",		  VX (4, 1178),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11379 {"evsubfaddhss",	  VX (4, 1179),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11380 {"evaddsubfhx",		  VX (4, 1180),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11381 {"evaddsubfhxss",	  VX (4, 1181),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11382 {"evsubfaddhx",		  VX (4, 1182),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11383 {"evsubfaddhxss",	  VX (4, 1183),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11384 {"evadddus",		  VX (4, 1184),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11385 {"evaddbus",		  VX (4, 1185),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11386 {"evsubfdus",		  VX (4, 1186),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11387 {"evsubfbus",		  VX (4, 1187),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11388 {"evaddwus",		  VX (4, 1188),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11389 {"evaddwxus",		  VX (4, 1189),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11390 {"evsubfwus",		  VX (4, 1190),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11391 {"evsubfwxus",		  VX (4, 1191),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11392 {"evadd2subf2h",	  VX (4, 1192),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11393 {"evadd2subf2hss",	  VX (4, 1193),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11394 {"evsubf2add2h",	  VX (4, 1194),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11395 {"evsubf2add2hss",	  VX (4, 1195),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11396 {"evaddhus",		  VX (4, 1196),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11397 {"evaddhxus",		  VX (4, 1197),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11398 {"evsubfhus",		  VX (4, 1198),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11399 {"evsubfhxus",		  VX (4, 1199),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11400 {"evaddwss",		  VX (4, 1201),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11401 {"evsubfwss",		  VX (4, 1203),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11402 {"evaddwx",		  VX (4, 1204),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11403 {"evaddwxss",		  VX (4, 1205),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11404 {"evsubfwx",		  VX (4, 1206),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11405 {"evsubfwxss",		  VX (4, 1207),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11406 {"evaddsubfw",		  VX (4, 1208),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11407 {"evaddsubfwss",	  VX (4, 1209),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11408 {"evsubfaddw",		  VX (4, 1210),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11409 {"evsubfaddwss",	  VX (4, 1211),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11410 {"evaddsubfwx",		  VX (4, 1212),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11411 {"evaddsubfwxss",	  VX (4, 1213),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11412 {"evsubfaddwx",		  VX (4, 1214),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11413 {"evsubfaddwxss",	  VX (4, 1215),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11415 {"evsumwu",		  VX_RB_CONST(4, 1221, 0),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11416 {"evsumws",		  VX_RB_CONST(4, 1221, 1),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11417 {"evsum4bu",		  VX_RB_CONST(4, 1221, 2),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11418 {"evsum4bs",		  VX_RB_CONST(4, 1221, 3),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11419 {"evsum2hu",		  VX_RB_CONST(4, 1221, 4),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11420 {"evsum2hs",		  VX_RB_CONST(4, 1221, 5),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11421 {"evdiff2his",		  VX_RB_CONST(4, 1221, 6),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11422 {"evsum2his",		  VX_RB_CONST(4, 1221, 7),  VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11423 {"evsumwua",		  VX_RB_CONST(4, 1221, 16), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11424 {"evsumwsa",		  VX_RB_CONST(4, 1221, 17), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11425 {"evsum4bua",		  VX_RB_CONST(4, 1221, 18), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11426 {"evsum4bsa",		  VX_RB_CONST(4, 1221, 19), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11427 {"evsum2hua",		  VX_RB_CONST(4, 1221, 20), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11428 {"evsum2hsa",		  VX_RB_CONST(4, 1221, 21), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11429 {"evdiff2hisa",		  VX_RB_CONST(4, 1221, 22), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11430 {"evsum2hisa",		  VX_RB_CONST(4, 1221, 23), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11431 {"evsumwuaa",		  VX_RB_CONST(4, 1221, 24), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11432 {"evsumwsaa",		  VX_RB_CONST(4, 1221, 25), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11433 {"evsum4buaaw",		  VX_RB_CONST(4, 1221, 26), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11434 {"evsum4bsaaw",		  VX_RB_CONST(4, 1221, 27), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11435 {"evsum2huaaw",		  VX_RB_CONST(4, 1221, 28), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11436 {"evsum2hsaaw",		  VX_RB_CONST(4, 1221, 29), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11437 {"evdiff2hisaaw",	  VX_RB_CONST(4, 1221, 30), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11438 {"evsum2hisaaw",	  VX_RB_CONST(4, 1221, 31), VX_RB_CONST_MASK,	PPCSPE2, 0, {RD, RA}},
11439 {"evdivwsf",		  VX (4, 1228),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11440 {"evdivwuf",		  VX (4, 1229),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11441 {"evdivs",		  VX (4, 1230),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11442 {"evdivu",		  VX (4, 1231),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11443 {"evaddwegsi",		  VX (4, 1232),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11444 {"evaddwegsf",		  VX (4, 1233),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11445 {"evsubfwegsi",		  VX (4, 1234),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11446 {"evsubfwegsf",		  VX (4, 1235),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11447 {"evaddwogsi",		  VX (4, 1236),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11448 {"evaddwogsf",		  VX (4, 1237),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11449 {"evsubfwogsi",		  VX (4, 1238),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11450 RA, RB}},
11451 {"evaddhhiuw",		  VX (4, 1240),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11452 {"evaddhhisw",		  VX (4, 1241),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11453 {"evsubfhhiuw",		  VX (4, 1242),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11454 {"evsubfhhisw",		  VX (4, 1243),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11455 {"evaddhlouw",		  VX (4, 1244),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11456 {"evaddhlosw",		  VX (4, 1245),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11457 {"evsubfhlouw",		  VX (4, 1246),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11458 {"evsubfhlosw",		  VX (4, 1247),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11459 {"evmhesusiaaw",	  VX (4, 1282),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11460 {"evmhosusiaaw",	  VX (4, 1286),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11461 {"evmhesumiaaw",	  VX (4, 1290),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11462 {"evmhosumiaaw",	  VX (4, 1294),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11463 {"evmbeusiaah",		  VX (4, 1296),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11464 {"evmbessiaah",		  VX (4, 1297),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11465 {"evmbesusiaah",	  VX (4, 1298),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11466 {"evmbousiaah",		  VX (4, 1300),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11467 {"evmbossiaah",		  VX (4, 1301),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11468 {"evmbosusiaah",	  VX (4, 1302),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11469 {"evmbeumiaah",		  VX (4, 1304),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11470 {"evmbesmiaah",		  VX (4, 1305),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11471 {"evmbesumiaah",	  VX (4, 1306),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11472 {"evmboumiaah",		  VX (4, 1308),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11473 {"evmbosmiaah",		  VX (4, 1309),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11474 {"evmbosumiaah",	  VX (4, 1310),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11475 {"evmwlusiaaw3",	  VX (4, 1346),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11476 {"evmwlssiaaw3",	  VX (4, 1347),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11477 {"evmwhssfraaw3",	  VX (4, 1348),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11478 {"evmwhssfaaw3",	  VX (4, 1349),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11479 {"evmwhssfraaw",	  VX (4, 1350),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11480 {"evmwhssfaaw",		  VX (4, 1351),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11481 {"evmwlumiaaw3",	  VX (4, 1354),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11482 {"evmwlsmiaaw3",	  VX (4, 1355),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11483 {"evmwusiaa",		  VX (4, 1360),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11484 {"evmwssiaa",		  VX (4, 1361),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11485 {"evmwehgsmfraa",	  VX (4, 1366),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11486 {"evmwehgsmfaa",	  VX (4, 1367),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11487 {"evmwohgsmfraa",	  VX (4, 1374),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11488 {"evmwohgsmfaa",	  VX (4, 1375),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11489 {"evmhesusianw",	  VX (4, 1410),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11490 {"evmhosusianw",	  VX (4, 1414),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11491 {"evmhesumianw",	  VX (4, 1418),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11492 {"evmhosumianw",	  VX (4, 1422),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11493 {"evmbeusianh",		  VX (4, 1424),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11494 {"evmbessianh",		  VX (4, 1425),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11495 {"evmbesusianh",	  VX (4, 1426),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11496 {"evmbousianh",		  VX (4, 1428),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11497 {"evmbossianh",		  VX (4, 1429),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11498 {"evmbosusianh",	  VX (4, 1430),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11499 {"evmbeumianh",		  VX (4, 1432),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11500 {"evmbesmianh",		  VX (4, 1433),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11501 {"evmbesumianh",	  VX (4, 1434),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11502 {"evmboumianh",		  VX (4, 1436),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11503 {"evmbosmianh",		  VX (4, 1437),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11504 {"evmbosumianh",	  VX (4, 1438),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11505 {"evmwlusianw3",	  VX (4, 1474),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11506 {"evmwlssianw3",	  VX (4, 1475),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11507 {"evmwhssfranw3",	  VX (4, 1476),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11508 {"evmwhssfanw3",	  VX (4, 1477),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11509 {"evmwhssfranw",	  VX (4, 1478),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11510 {"evmwhssfanw",		  VX (4, 1479),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11511 {"evmwlumianw3",	  VX (4, 1482),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11512 {"evmwlsmianw3",	  VX (4, 1483),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11513 {"evmwusian",		  VX (4, 1488),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11514 {"evmwssian",		  VX (4, 1489),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11515 {"evmwehgsmfran",	  VX (4, 1494),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11516 {"evmwehgsmfan",	  VX (4, 1495),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11517 {"evmwohgsmfran",	  VX (4, 1502),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11518 {"evmwohgsmfan",	  VX (4, 1503),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11519 {"evseteqb",		  VX (4, 1536),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11520 {"evseteqb.",		  VX (4, 1537),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11521 {"evseteqh",		  VX (4, 1538),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11522 {"evseteqh.",		  VX (4, 1539),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11523 {"evseteqw",		  VX (4, 1540),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11524 {"evseteqw.",		  VX (4, 1541),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11525 {"evsetgthu",		  VX (4, 1544),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11526 {"evsetgthu.",		  VX (4, 1545),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11527 {"evsetgths",		  VX (4, 1546),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11528 {"evsetgths.",		  VX (4, 1547),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11529 {"evsetgtwu",		  VX (4, 1548),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11530 {"evsetgtwu.",		  VX (4, 1549),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11531 {"evsetgtws",		  VX (4, 1550),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11532 {"evsetgtws.",		  VX (4, 1551),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11533 {"evsetgtbu",		  VX (4, 1552),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11534 {"evsetgtbu.",		  VX (4, 1553),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11535 {"evsetgtbs",		  VX (4, 1554),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11536 {"evsetgtbs.",		  VX (4, 1555),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11537 {"evsetltbu",		  VX (4, 1556),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11538 {"evsetltbu.",		  VX (4, 1557),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11539 {"evsetltbs",		  VX (4, 1558),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11540 {"evsetltbs.",		  VX (4, 1559),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11541 {"evsetlthu",		  VX (4, 1560),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11542 {"evsetlthu.",		  VX (4, 1561),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11543 {"evsetlths",		  VX (4, 1562),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11544 {"evsetlths.",		  VX (4, 1563),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11545 {"evsetltwu",		  VX (4, 1564),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11546 {"evsetltwu.",		  VX (4, 1565),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11547 {"evsetltws",		  VX (4, 1566),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11548 {"evsetltws.",		  VX (4, 1567),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11549 {"evsaduw",		  VX (4, 1568),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11550 {"evsadsw",		  VX (4, 1569),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11551 {"evsad4ub",		  VX (4, 1570),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11552 {"evsad4sb",		  VX (4, 1571),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11553 {"evsad2uh",		  VX (4, 1572),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11554 {"evsad2sh",		  VX (4, 1573),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11555 {"evsaduwa",		  VX (4, 1576),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11556 {"evsadswa",		  VX (4, 1577),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11557 {"evsad4uba",		  VX (4, 1578),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11558 {"evsad4sba",		  VX (4, 1579),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11559 {"evsad2uha",		  VX (4, 1580),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11560 {"evsad2sha",		  VX (4, 1581),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11561 {"evabsdifuw",		  VX (4, 1584),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11562 {"evabsdifsw",		  VX (4, 1585),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11563 {"evabsdifub",		  VX (4, 1586),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11564 {"evabsdifsb",		  VX (4, 1587),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11565 {"evabsdifuh",		  VX (4, 1588),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11566 {"evabsdifsh",		  VX (4, 1589),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11567 {"evsaduwaa",		  VX (4, 1592),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11568 {"evsadswaa",		  VX (4, 1593),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11569 {"evsad4ubaaw",		  VX (4, 1594),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11570 {"evsad4sbaaw",		  VX (4, 1595),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11571 {"evsad2uhaaw",		  VX (4, 1596),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11572 {"evsad2shaaw",		  VX (4, 1597),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11573 {"evpkshubs",		  VX (4, 1600),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11574 {"evpkshsbs",		  VX (4, 1601),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11575 {"evpkswuhs",		  VX (4, 1602),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11576 {"evpkswshs",		  VX (4, 1603),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11577 {"evpkuhubs",		  VX (4, 1604),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11578 {"evpkuwuhs",		  VX (4, 1605),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11579 {"evpkswshilvs",	  VX (4, 1606),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11580 {"evpkswgshefrs",	  VX (4, 1607),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11581 {"evpkswshfrs",		  VX (4, 1608),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11582 {"evpkswshilvfrs",	  VX (4, 1609),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11583 {"evpksdswfrs",		  VX (4, 1610),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11584 {"evpksdshefrs",	  VX (4, 1611),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11585 {"evpkuduws",		  VX (4, 1612),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11586 {"evpksdsws",		  VX (4, 1613),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11587 {"evpkswgswfrs",	  VX (4, 1614),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11588 {"evilveh",		  VX (4, 1616),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11589 {"evilveoh",		  VX (4, 1617),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11590 {"evilvhih",		  VX (4, 1618),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11591 {"evilvhiloh",		  VX (4, 1619),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11592 {"evilvloh",		  VX (4, 1620),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11593 {"evilvlohih",		  VX (4, 1621),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11594 {"evilvoeh",		  VX (4, 1622),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11595 {"evilvoh",		  VX (4, 1623),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11596 {"evdlveb",		  VX (4, 1624),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11597 {"evdlveh",		  VX (4, 1625),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11598 {"evdlveob",		  VX (4, 1626),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11599 {"evdlveoh",		  VX (4, 1627),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11600 {"evdlvob",		  VX (4, 1628),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11601 {"evdlvoh",		  VX (4, 1629),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11602 {"evdlvoeb",		  VX (4, 1630),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11603 {"evdlvoeh",		  VX (4, 1631),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11604 {"evmaxbu",		  VX (4, 1632),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11605 {"evmaxbs",		  VX (4, 1633),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11606 {"evmaxhu",		  VX (4, 1634),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11607 {"evmaxhs",		  VX (4, 1635),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11608 {"evmaxwu",		  VX (4, 1636),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11609 {"evmaxws",		  VX (4, 1637),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11610 {"evmaxdu",		  VX (4, 1638),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11611 {"evmaxds",		  VX (4, 1639),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11612 {"evminbu",		  VX (4, 1640),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11613 {"evminbs",		  VX (4, 1641),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11614 {"evminhu",		  VX (4, 1642),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11615 {"evminhs",		  VX (4, 1643),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11616 {"evminwu",		  VX (4, 1644),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11617 {"evminws",		  VX (4, 1645),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11618 {"evmindu",		  VX (4, 1646),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11619 {"evminds",		  VX (4, 1647),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11620 {"evavgwu",		  VX (4, 1648),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11621 {"evavgws",		  VX (4, 1649),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11622 {"evavgbu",		  VX (4, 1650),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11623 {"evavgbs",		  VX (4, 1651),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11624 {"evavghu",		  VX (4, 1652),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11625 {"evavghs",		  VX (4, 1653),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11626 {"evavgdu",		  VX (4, 1654),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11627 {"evavgds",		  VX (4, 1655),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11628 {"evavgwur",		  VX (4, 1656),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11629 {"evavgwsr",		  VX (4, 1657),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11630 {"evavgbur",		  VX (4, 1658),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11631 {"evavgbsr",		  VX (4, 1659),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11632 {"evavghur",		  VX (4, 1660),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11633 {"evavghsr",		  VX (4, 1661),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11634 {"evavgdur",		  VX (4, 1662),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
11635 {"evavgdsr",		  VX (4, 1663),		VX_MASK,		PPCSPE2, 0, {RD, RA, RB}},
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