Lines Matching refs:OP_SRC1
247 { "add", 1,2,2,0x0000, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
248 { "add", 1,3,3,0x0400, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, REST},
250 { "add", 1,3,3,0x9000, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, REST},/*PREFER*/
256 { "addc", 1,2,2,0x0600, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
258 { "adds", 1,2,2,0x0200, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
260 { "and", 1,2,2,0x1800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST },
266 { "bacc", 1,1,1,0xF4E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, REST},
267 { "baccd", 1,1,1,0xF6E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, REST},
277 { "cala", 1,1,1,0xF4E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, REST},
278 { "calad", 1,1,1,0xF6E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, REST},
288 { "cmps", 1,2,2,0x8E00, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
293 { "drsub", 1,2,2,0x5800, 0xFE00, {OP_Lmem,OP_SRC1}, 0, REST},
295 { "dst", 1,2,2,0x4E00, 0xFE00, {OP_SRC1,OP_Lmem}, FL_NR, REST},
296 { "dsub", 1,2,2,0x5400, 0xFE00, {OP_Lmem,OP_SRC1}, 0, REST},
299 { "exp", 1,1,1,0xF48E, 0xFEFF, {OP_SRC1}, 0, REST},
300 { "fbacc", 1,1,1,0xF4E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, REST},
301 { "fbaccd",1,1,1,0xF6E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, REST},
302 { "fcala", 1,1,1,0xF4E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, REST},
303 { "fcalad",1,1,1,0xF6E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, REST},
337 { "mac", 1,2,2,0x2800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
341 { "macr", 1,2,2,0x2A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
347 { "macd", 2,3,3,0x7A00, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, REST},
348 { "macp", 2,3,3,0x7800, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, REST},
349 { "macsu", 1,3,3,0xA600, 0xFE00, {OP_Xmem,OP_Ymem,OP_SRC1}, 0, REST},
351 { "mas", 1,2,2,0x2C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
353 { "masr", 1,2,2,0x2E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
380 { "or", 1,2,2,0x1A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
404 { "rol", 1,1,1,0xF491, 0xFEFF, {OP_SRC1}, 0, REST},
405 { "roltc", 1,1,1,0xF492, 0xFEFF, {OP_SRC1}, 0, REST},
406 { "ror", 1,1,1,0xF490, 0xFEFF, {OP_SRC1}, 0, REST},
414 { "saccd", 1,3,3,0x9E00, 0xFE00, {OP_SRC1,OP_Xmem,OP_CC2}, 0, REST},
415 { "sat", 1,1,1,0xF483, 0xFEFF, {OP_SRC1}, 0, REST},
417 { "sftc", 1,1,1,0xF494, 0xFEFF, {OP_SRC1}, 0, REST},
422 { "squra", 1,2,2,0x3800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
423 { "squrs", 1,2,2,0x3A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
429 { "sth", 1,2,2,0x8200, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
430 { "sth", 1,3,3,0x8600, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, REST},
431 { "sth", 1,3,3,0x9A00, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, REST},
432 { "sth", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem},
434 { "stl", 1,2,2,0x8000, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
435 { "stl", 1,3,3,0x8400, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, REST},
436 { "stl", 1,3,3,0x9800, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, REST},
437 { "stl", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem},
439 { "stlm", 1,2,2,0x8800, 0xFE00, {OP_SRC1,OP_MMR}, 0, REST},
444 { "sub", 1,2,2,0x0800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
445 { "sub", 1,3,3,0x0C00, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, REST},
447 { "sub", 1,3,3,0x9200, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, REST}, /*PREFER*/
453 { "subb", 1,2,2,0x0E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
454 { "subc", 1,2,2,0x1E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
455 { "subs", 1,2,2,0x0A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
460 { "xor", 1,2,2,0x1C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
Indexes created Sun Mar 01 05:31:48 UTC 2026