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Lines Matching refs:imm12

686 	ARMword imm12 = (tBIT(10) << 11) | (ntBITS (12, 14) << 8) | ntBITS (0, 7);
691 	imm12 = ThumbExpandImm (imm12);	
692 	val = state->Reg[Rn] & imm12;
771 	ARMword imm12 = ((tBIT (10) << 11) | (ntBITS (12, 14) << 8) | ntBITS (0, 7));
774 	imm12 = ThumbExpandImm (imm12);
776 	result = state->Reg[Rn] ^ imm12;
803 	ARMword imm12 = (tBIT (10) << 11) | (ntBITS (12, 14) << 8) | ntBITS (0, 7);
804 	ARMword rhs = ThumbExpandImm (imm12);
850 	ARMword imm12 = (tBIT (10) << 11) | (ntBITS (12, 14) << 8) | ntBITS (0, 7);
852 	ARMword rhs = ThumbExpandImm (imm12);
892 	ARMword imm12 = (tBIT (10) << 11) | (ntBITS (12, 14) << 8) | ntBITS (0, 7);
894 	ARMword rhs = ThumbExpandImm (imm12);
934 	ARMword imm12 = (tBIT (10) << 11) | (ntBITS (12, 14) << 8) | ntBITS (0, 7);
936 	ARMword rhs = ThumbExpandImm (imm12);
978 	ARMword imm12 = (tBIT (10) << 11) | (ntBITS (12, 14) << 8) | ntBITS (0, 7);
980 	ARMword lhs = imm12;
1009     case 0x90: // ADDW<c> <Rd>,<Rn>,#<imm12>
1013 	ARMword imm12 = (tBIT (10) << 11) | (ntBITS (12, 14) << 8) | ntBITS (0, 7);
1018 	state->Reg[Rd] = state->Reg[Rn] + imm12;
1036     case 0x95:// SUBW<c> <Rd>,<Rn>,#<imm12>
1040 	ARMword imm12 = (tBIT (10) << 11) | (ntBITS (12, 14) << 8) | ntBITS (0, 7);
1048 	state->Reg[Rd] = state->Reg[Rn] - imm12;
1144 		/* LDRB<c>.W <Rt>,[<Rn>{,#<imm12>}]         => 1111 1000 1001 rrrr */
1178 		// STRB<c>.W <Rt>,[<Rn>,#<imm12>]
1179 		ARMword imm12 = ntBITS (0, 11);
1181 		ARMul_StoreByte (state, state->Reg[Rn] + imm12, state->Reg [Rt]);
1329 		// LDRH<c>.W <Rt>,[<Rn>{,#<imm12>}]
1330 		ARMword imm12 = ntBITS (0, 11);
1331 		address = state->Reg[Rn] + imm12;
1374 		// STRH<c>.W <Rt>,[<Rn>{,#<imm12>}]
1375 		ARMword imm12 = ntBITS (0, 11);
1377 		address = state->Reg[Rn] + imm12;
1423 	ARMword imm12 = ntBITS (0, 11);
1433 	address += imm12;
1457 	    ARMword imm12 = ntBITS (0, 11);
1458 	    address += (U ? imm12 : - imm12);
1462 	    // LDRSB<c> <Rt>,[<Rn>,#<imm12>]
1463 	    ARMword imm12 = ntBITS (0, 11);
1464 	    address += imm12;
1514 	    // Rn!=15 => LDRSH<c> <Rt>,[<Rn>,#<imm12>]
1515 	    ARMword imm12 = ntBITS (0, 11);
1517 	    address += (U ? imm12 : - imm12);