Lines Matching refs:UINT
58 #define GET_H_SR_V32(index) (ORIF (ORIF (((index) == (((UINT) 0))), ((index) == (((UINT) 4)))), ((index) == (((UINT) 8))))) ? (0) : (((index) == (((UINT) 1)))) ? (32) : (((index) == (((UINT) 13)))) ? (ORSI (ANDSI (CPU (h_sr_v32[((UINT) 13)]), 1073740800), ORSI (ZEXTBISI (CPU (h_cbit)), ORSI (SLLSI (ZEXTBISI (CPU (h_vbit)), 1), ORSI (SLLSI (ZEXTBISI (CPU (h_zbit)), 2), ORSI (SLLSI (ZEXTBISI (CPU (h_nbit)), 3), ORSI (SLLSI (ZEXTBISI (CPU (h_xbit)), 4), ORSI (SLLSI (ZEXTBISI (GET_H_IBIT ()), 5), ORSI (SLLSI (ZEXTBISI (GET_H_UBIT ()), 6), ORSI (SLLSI (ZEXTBISI (CPU (h_pbit)), 7), ORSI (SLLSI (ZEXTBISI (CPU (h_rbit)), 8), ORSI (SLLSI (ZEXTBISI (CPU (h_sbit)), 9), ORSI (SLLSI (ZEXTBISI (CPU (h_mbit)), 30), ORSI (SLLSI (ZEXTBISI (CPU (h_qbit)), 31), 0)))))))))))))) : (((index) == (((UINT) 14)))) ? (((GET_H_UBIT ()) ? (CPU (h_gr_acr[((UINT) 14)])) : (CPU (h_sr_v32[((UINT) 14)])))) : (CPU (h_sr_v32[index]))
61 if (ORIF (ORIF ((((index)) == (((UINT) 0))), (((index)) == (((UINT) 4)))), ORIF ((((index)) == (((UINT) 8))), (((index)) == (((UINT) 1)))))) {\
64 else if ((((index)) == (((UINT) 13)))) {\
81 else if ((((index)) == (((UINT) 14)))) {\
84 CPU (h_gr_acr[((UINT) 14)]) = (x);\
86 CPU (h_sr_v32[((UINT) 14)]) = (x);\
89 else if ((((index)) == (((UINT) 3)))) {\
91 CPU (h_sr_v32[((UINT) 3)]) = (x);\
94 else if ((((index)) == (((UINT) 9)))) {\
96 CPU (h_sr_v32[((UINT) 9)]) = (x);\
99 else if ((((index)) == (((UINT) 2)))) {\
103 CPU (h_sr_v32[((UINT) 2)]) = (x);\
107 else if ((((index)) == (((UINT) 15)))) {\
109 CPU (h_sr_v32[((UINT) 15)]) = (x);\
160 CPU (h_kernel_sp) = CPU (h_gr_acr[((UINT) 14)]);\
161 CPU (h_gr_acr[((UINT) 14)]) = CPU (h_sr_v32[((UINT) 14)]);\
320 #define GET_H_PREFIXREG_V32() GET_H_GR (((UINT) 15))
323 SET_H_GR (((UINT) 15), (x));\
331 SI crisv32f_h_gr_get (SIM_CPU *, UINT);
332 void crisv32f_h_gr_set (SIM_CPU *, UINT, SI);
333 SI crisv32f_h_gr_acr_get (SIM_CPU *, UINT);
334 void crisv32f_h_gr_acr_set (SIM_CPU *, UINT, SI);
335 SI crisv32f_h_raw_gr_acr_get (SIM_CPU *, UINT);
336 void crisv32f_h_raw_gr_acr_set (SIM_CPU *, UINT, SI);
337 SI crisv32f_h_sr_get (SIM_CPU *, UINT);
338 void crisv32f_h_sr_set (SIM_CPU *, UINT, SI);
339 SI crisv32f_h_sr_v32_get (SIM_CPU *, UINT);
340 void crisv32f_h_sr_v32_set (SIM_CPU *, UINT, SI);
341 SI crisv32f_h_supr_get (SIM_CPU *, UINT);
342 void crisv32f_h_supr_set (SIM_CPU *, UINT, SI);
403 UINT prev_prev_prev_modf_regs;
404 UINT prev_prev_modf_regs;
405 UINT prev_modf_regs;
406 UINT modf_regs;
407 UINT prev_prev_prev_movem_dest_regs;
408 UINT prev_prev_movem_dest_regs;
409 UINT prev_movem_dest_regs;
410 UINT movem_dest_regs;
420 UINT f_u4;
423 UINT f_dstsrc;
427 UINT f_operand2;
431 UINT f_operand2;
439 UINT f_operand2;
444 UINT f_operand2;
449 UINT f_operand2;
454 UINT f_operand2;
459 UINT f_operand2;
464 UINT f_operand2;
469 UINT f_operand2;
475 UINT f_operand2;
481 UINT f_operand2;
486 UINT f_operand2;
487 UINT f_u5;
493 UINT f_operand2;
499 UINT f_operand2;
505 UINT f_operand2;
511 UINT f_operand2;
516 UINT f_operand2;
517 UINT f_u6;
522 UINT f_operand1;
523 UINT f_operand2;
529 UINT f_operand1;
530 UINT f_operand2;
537 UINT f_memmode;
538 UINT f_operand1;
539 UINT f_operand2;
545 UINT f_memmode;
546 UINT f_operand1;
547 UINT f_operand2;
553 UINT f_memmode;
554 UINT f_operand1;
555 UINT f_operand2;
561 UINT f_memmode;
562 UINT f_operand1;
563 UINT f_operand2;
570 UINT f_memmode;
571 UINT f_operand1;
572 UINT f_operand2;
579 UINT f_memmode;
580 UINT f_operand1;
581 UINT f_operand2;
603 UINT f_memmode;
604 UINT f_operand1;
605 UINT f_operand2;
687 UINT f_operand2; \
688 UINT f_mode; \
689 UINT f_opcode; \
690 UINT f_size; \
691 UINT f_operand1; \
702 UINT f_operand2; \
703 UINT f_mode; \
704 UINT f_opcode; \
715 UINT f_operand2; \
717 UINT f_mode; \
718 UINT f_opcode; \
719 UINT f_size; \
720 UINT f_operand1; \
722 UINT word_1; \
735 UINT f_operand2; \
737 UINT f_mode; \
738 UINT f_opcode; \
739 UINT f_size; \
740 UINT f_operand1; \
742 UINT word_1; \
756 UINT f_operand2; \
757 UINT f_mode; \
758 UINT f_opcode; \
759 UINT f_size; \
760 UINT f_operand1; \
762 UINT word_1; \
775 UINT f_operand2; \
777 UINT f_mode; \
778 UINT f_opcode; \
779 UINT f_size; \
780 UINT f_operand1; \
782 UINT word_1; \
795 UINT f_operand2; \
797 UINT f_mode; \
798 UINT f_opcode; \
799 UINT f_size; \
800 UINT f_operand1; \
802 UINT word_1; \
815 UINT f_operand2; \
816 UINT f_mode; \
817 UINT f_opcode; \
818 UINT f_u6; \
828 UINT f_operand2; \
829 UINT f_membit; \
830 UINT f_memmode; \
831 UINT f_opcode; \
832 UINT f_size; \
833 UINT f_operand1; \
845 UINT f_operand2; \
846 UINT f_mode; \
847 UINT f_opcode; \
848 UINT f_size; \
849 UINT f_operand1; \
860 UINT f_operand2; \
861 UINT f_mode; \
862 UINT f_opcode; \
863 UINT f_size; \
864 UINT f_operand1; \
875 UINT f_operand2; \
876 UINT f_membit; \
877 UINT f_memmode; \
878 UINT f_opcode; \
879 UINT f_size; \
880 UINT f_operand1; \
893 UINT f_operand2; \
894 UINT f_mode; \
895 UINT f_opcode; \
896 UINT f_size; \
897 UINT f_operand1; \
899 UINT word_1; \
912 UINT f_operand2; \
913 UINT f_membit; \
914 UINT f_memmode; \
915 UINT f_opcode; \
916 UINT f_size; \
917 UINT f_operand1; \
929 UINT f_operand2; \
930 UINT f_mode; \
931 UINT f_opcode; \
932 UINT f_size; \
933 UINT f_operand1; \
944 UINT f_operand2; \
945 UINT f_mode; \
946 UINT f_opcode; \
947 UINT f_size; \
948 UINT f_operand1; \
960 UINT f_operand2; \
961 UINT f_mode; \
962 UINT f_opcode; \
963 UINT f_size; \
964 UINT f_operand1; \
966 UINT word_1; \
979 UINT f_operand2; \
980 UINT f_mode; \
981 UINT f_opcode; \
982 UINT f_size; \
994 UINT f_operand2; \
995 UINT f_membit; \
996 UINT f_memmode; \
997 UINT f_opcode; \
998 UINT f_size; \
999 UINT f_operand1; \
1011 UINT f_operand2; \
1012 UINT f_mode; \
1013 UINT f_opcode; \
1014 UINT f_size; \
1015 UINT f_operand1; \
1026 UINT f_operand2; \
1027 UINT f_mode; \
1028 UINT f_opcode; \
1029 UINT f_b5; \
1030 UINT f_u5; \
1041 UINT f_mode; \
1042 UINT f_opcode; \
1043 UINT f_size; \
1044 UINT f_operand2; \
1045 UINT f_operand1; \
1046 UINT f_dstsrc; \
1058 UINT f_operand2; \
1059 UINT f_mode; \
1060 UINT f_opcode; \
1061 UINT f_size; \
1062 UINT f_operand1; \
1073 UINT f_operand2; \
1074 UINT f_mode; \
1075 UINT f_opcode_hi; \
1077 UINT f_disp9_lo; \
1096 UINT f_operand2; \
1097 UINT f_mode; \
1098 UINT f_opcode_hi; \
1100 UINT f_disp9_lo; \
1119 UINT f_operand2; \
1121 UINT f_mode; \
1122 UINT f_opcode; \
1123 UINT f_size; \
1124 UINT f_operand1; \
1126 UINT word_1; \
1132 f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_V32 ()) ? (0) : (4)))))); \
1139 UINT f_operand2; \
1141 UINT f_mode; \
1142 UINT f_opcode; \
1143 UINT f_size; \
1144 UINT f_operand1; \
1146 UINT word_1; \
1152 f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_V32 ()) ? (0) : (4)))))); \
1160 UINT f_operand2; \
1161 UINT f_mode; \
1162 UINT f_opcode; \
1163 UINT f_size; \
1164 UINT f_operand1; \
1166 UINT word_1; \
1179 UINT f_operand2; \
1180 UINT f_mode; \
1181 UINT f_opcode; \
1182 UINT f_size; \
1183 UINT f_operand1; \
1195 UINT f_operand2; \
1196 UINT f_mode; \
1197 UINT f_opcode; \
1198 UINT f_size; \
1199 UINT f_operand1; \
1201 UINT word_1; \
1214 UINT f_operand2; \
1215 UINT f_mode; \
1216 UINT f_opcode; \
1217 UINT f_size; \
1218 UINT f_u4; \
1229 UINT f_operand2; \
1230 UINT f_mode; \
1231 UINT f_opcode; \
1232 UINT f_size; \
1233 UINT f_operand1; \
1244 UINT f_operand2; \
1245 UINT f_mode; \
1246 UINT f_opcode_hi; \
1257 UINT f_operand2; \
1258 UINT f_mode; \
1259 UINT f_opcode; \
1260 UINT f_size; \
1261 UINT f_operand1; \
Indexes created Sat Sep 26 00:25:34 UTC 2026