Lines Matching defs:war
871 /* Check the priorities of load requests waiting in WAR. These are one
875 FRV_CACHE_WAR *war = & pipeline->WAR[i];
876 if (war->valid && war->priority > lowest)
877 lowest = war->priority + 1;
890 /* Return a priority 2 lower than the lowest found. This allows a WAR
897 add_WAR_request (FRV_CACHE_PIPELINE* pipeline, FRV_CACHE_WAR *war)
902 req->reqno = war->reqno;
903 req->priority = war->priority;
904 req->address = war->address;
905 req->u.WAR.preload = war->preload;
906 req->u.WAR.lock = war->lock;
1104 /* Check for a collision with load requests waiting in WAR. */
1109 FRV_CACHE_WAR *war = & cache->pipeline[i].WAR[j];
1110 if (war->valid
1111 && (address == (war->address & line_mask)
1113 && priority > war->priority)
1116 /* If this is not a WAR request, then yield to any WAR requests in
1153 /* Wait for a free WAR register in BARS or NARS. */
1211 /* Find a free WAR register and wait for memory to fetch the data. */
1215 int war;
1218 /* Find a valid WAR to hold this request. */
1219 for (war = 0; war < NUM_WARS; ++war)
1220 if (! pipeline->WAR[war].valid)
1222 if (war >= NUM_WARS)
1228 pipeline->WAR[war].address = req->address;
1229 pipeline->WAR[war].reqno = req->reqno;
1230 pipeline->WAR[war].priority = req->priority - 1;
1231 pipeline->WAR[war].latency = cache->memory_latency + 1;
1235 pipeline->WAR[war].preload = 0;
1236 pipeline->WAR[war].lock = 0;
1239 pipeline->WAR[war].preload = 1;
1240 pipeline->WAR[war].lock = 0;
1243 pipeline->WAR[war].preload = 1;
1244 pipeline->WAR[war].lock = req->u.preload.lock;
1247 pipeline->WAR[war].valid = 1;
1278 wait for the memory unit to fetch it. Store this request in the WAR in
1336 unit to fetch it. Store this request in the WAR in the meantime.
1385 Store this request in the WAR and requeue the store request. */
1475 if (! req->u.WAR.preload)
1483 if (req->u.WAR.lock)
1492 if (! req->u.WAR.preload)
1540 /* Move a waiting ARS register to a free WAR register. */
1542 move_ARS_to_WAR (FRV_CACHE *cache, int pipe, FRV_CACHE_WAR *war)
1544 /* If BARS is valid for this pipe, then move it to the given WAR. Move
1548 war->address = cache->BARS.address;
1549 war->reqno = cache->BARS.reqno;
1550 war->priority = cache->BARS.priority;
1551 war->preload = cache->BARS.preload;
1552 war->lock = cache->BARS.lock;
1553 war->latency = cache->memory_latency + 1;
1554 war->valid = 1;
1564 /* If NARS is valid for this pipe, then move it to the given WAR. */
1567 war->address = cache->NARS.address;
1568 war->reqno = cache->NARS.reqno;
1569 war->priority = cache->NARS.priority;
1570 war->preload = cache->NARS.preload;
1571 war->lock = cache->NARS.lock;
1572 war->latency = cache->memory_latency + 1;
1573 war->valid = 1;
1583 /* Check the WAR registers. */
1589 FRV_CACHE_WAR *war = & pipeline->WAR[j];
1590 if (war->valid)
1592 --war->latency;
1593 /* If the latency has expired, then submit a WAR request to the
1595 if (war->latency <= 0)
1597 add_WAR_request (pipeline, war);
1598 war->valid = 0;
1599 move_ARS_to_WAR (cache, pipe, war);
Indexes created Wed Jul 08 00:27:11 UTC 2026