Lines Matching refs:CPU
58 return (((CPU (h_bpsw) & 0xc1) << 8)
59 | ((CPU (h_psw) & 0xc0) << 0)
62 return CPU (h_bbpsw) & 0xc1;
67 return CPU (h_gr[H_GR_SP]);
69 return CPU (h_cr[H_CR_SPI]);
72 return CPU (h_gr[H_GR_SP]);
74 return CPU (h_cr[H_CR_SPU]);
76 return CPU (h_cr[H_CR_BPC]) & 0xfffffffe;
78 return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe;
81 return CPU (h_cr[cr]);
94 int old_sm = (CPU (h_psw) & 0x80) != 0;
96 CPU (h_bpsw) = (newval >> 8) & 0xff;
97 CPU (h_psw) = newval & 0xff;
105 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]);
106 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]);
111 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]);
112 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]);
118 CPU (h_bbpsw) = newval & 0xff;
125 CPU (h_gr[H_GR_SP]) = newval;
127 CPU (h_cr[H_CR_SPI]) = newval;
131 CPU (h_gr[H_GR_SP]) = newval;
133 CPU (h_cr[H_CR_SPU]) = newval;
136 CPU (h_cr[H_CR_BPC]) = newval;
139 CPU (h_cr[H_CR_BBPC]) = newval;
143 CPU (h_cr[cr]) = newval;
156 return (CPU (h_psw) & 0xfe) | (CPU (h_cond) & 1);
162 CPU (h_psw) = newval;
163 CPU (h_cond) = newval & 1;
173 r = ANDDI (CPU (h_accum), MAKEDI (0xffffff, 0xffffffff));
182 CPU (h_accum) = newval;
193 r = CPU (h_accum);
195 r = CPU (h_accums[1]);
208 CPU (h_accum) = newval;
210 CPU (h_accums[1]) = newval;
221 m32rxf_model_insn_before (SIM_CPU *cpu, int first_p)
223 m32rbf_model_insn_before (cpu, first_p);
232 m32rxf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
234 m32rbf_model_insn_after (cpu, last_p, cycles);
238 check_load_stall (SIM_CPU *cpu, int regno)
240 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs;
245 CPU_M32R_MISC_PROFILE (cpu)->load_stall += 2;
246 if (TRACE_INSN_P (cpu))
247 cgen_trace_printf (cpu, " ; Load stall of 2 cycles.");
252 m32rxf_model_m32rx_u_exec (SIM_CPU *cpu, const IDESC *idesc,
256 check_load_stall (cpu, sr);
257 check_load_stall (cpu, sr2);
262 m32rxf_model_m32rx_u_cmp (SIM_CPU *cpu, const IDESC *idesc,
266 check_load_stall (cpu, src1);
267 check_load_stall (cpu, src2);
272 m32rxf_model_m32rx_u_mac (SIM_CPU *cpu, const IDESC *idesc,
276 check_load_stall (cpu, src1);
277 check_load_stall (cpu, src2);
282 m32rxf_model_m32rx_u_cti (SIM_CPU *cpu, const IDESC *idesc,
286 PROFILE_DATA *profile = CPU_PROFILE_DATA (cpu);
289 check_load_stall (cpu, sr);
292 CPU_M32R_MISC_PROFILE (cpu)->cti_stall += 2;
301 m32rxf_model_m32rx_u_load (SIM_CPU *cpu, const IDESC *idesc,
305 CPU_M32R_MISC_PROFILE (cpu)->load_regs_pending |= (1 << dr);
310 m32rxf_model_m32rx_u_store (SIM_CPU *cpu, const IDESC *idesc,
Indexes created Sat Feb 28 05:31:39 UTC 2026