Cross Reference: /src/external/gpl3/gdb.old/dist/sim/m32r/model.c

Lines Matching defs:in_src1
378     INT in_src1 = -1;
380     in_src1 = FLD (in_src1);
384     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
407     INT in_src1 = -1;
411     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
434     INT in_src1 = -1;
438     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
461     INT in_src1 = -1;
465     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
488     INT in_src1 = -1;
492     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
515     INT in_src1 = -1;
519     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
542     INT in_src1 = -1;
546     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
641     INT in_src1 = -1;
643     in_src1 = FLD (in_src1);
647     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
699     INT in_src1 = -1;
701     in_src1 = FLD (in_src1);
705     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
721     INT in_src1 = -1;
725     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
741     INT in_src1 = -1;
743     in_src1 = FLD (in_src1);
747     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
763     INT in_src1 = -1;
767     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1262     INT in_src1 = -1;
1264     in_src1 = FLD (in_src1);
1268     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1284     INT in_src1 = -1;
1286     in_src1 = FLD (in_src1);
1290     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1306     INT in_src1 = -1;
1308     in_src1 = FLD (in_src1);
1312     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1328     INT in_src1 = -1;
1330     in_src1 = FLD (in_src1);
1334     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1375     INT in_src1 = -1;
1377     in_src1 = FLD (in_src1);
1381     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1397     INT in_src1 = -1;
1399     in_src1 = FLD (in_src1);
1403     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1419     INT in_src1 = -1;
1421     in_src1 = FLD (in_src1);
1425     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1441     INT in_src1 = -1;
1443     in_src1 = FLD (in_src1);
1447     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1573     in_sr = FLD (in_src1);
1593     in_sr = FLD (in_src1);
1696     INT in_src1 = -1;
1698     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1714     INT in_src1 = -1;
1716     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1985     INT in_src1 = 0;
1987     in_src1 = FLD (in_src1);
1991     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2007     INT in_src1 = 0;
2009     in_src1 = FLD (in_src1);
2013     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2029     INT in_src1 = 0;
2031     in_src1 = FLD (in_src1);
2035     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2051     INT in_src1 = 0;
2053     in_src1 = FLD (in_src1);
2057     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2073     INT in_src1 = 0;
2075     in_src1 = FLD (in_src1);
2079     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2095     INT in_src1 = 0;
2097     in_src1 = FLD (in_src1);
2101     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2117     INT in_src1 = 0;
2119     in_src1 = FLD (in_src1);
2123     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2149     INT in_src1 = 0;
2151     in_src1 = FLD (in_src1);
2155     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
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