Cross Reference: /src/external/gpl3/gdb.old/dist/sim/m32r/sem-switch.c

Lines Matching defs:temp1

525   SI temp0;BI temp1;
527   temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
534     BI opval = temp1;
554   SI temp0;BI temp1;
556   temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
563     BI opval = temp1;
583   SI temp0;BI temp1;
585   temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
592     BI opval = temp1;
1179   SI temp0;USI temp1;
1181   temp1 = ANDSI (* FLD (i_sr), -4);
1188     USI opval = temp1;
1420   SI temp0;SI temp1;
1422   temp1 = ADDSI (* FLD (i_sr), 4);
1429     SI opval = temp1;
2382   SI temp0;BI temp1;
2384   temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
2391     BI opval = temp1;
2411   SI temp0;BI temp1;
2413   temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
2420     BI opval = temp1;

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