Cross Reference: /src/external/gpl3/gdb.old/dist/sim/m68hc11/dv-m68hc11spi.c

Lines Matching defs:controller
42         The SPI I/O controller is directly connected to the CPU
60         I/O controller. It should be connected to the RESET output of the cpu.
116                         struct m68hc11spi *controller)
127   struct m68hc11spi *controller;
129   controller = HW_ZALLOC (me, struct m68hc11spi);
130   set_hw_data (me, controller);
142   attach_m68hc11spi_regs (me, controller);
145   controller->spi_event = NULL;
146   controller->rx_clear_scsr = 0;
160   struct m68hc11spi *controller;
163   controller = hw_data (me);
171         controller->rx_clear_scsr = 0;
172         if (controller->spi_event)
174             hw_event_queue_deschedule (me, controller->spi_event);
175             controller->spi_event = 0;
241   struct m68hc11spi* controller;
246   controller = hw_data (me);
252   if (controller->spi_event)
254       hw_event_queue_deschedule (me, controller->spi_event);
255       controller->spi_event = 0;
259   if (controller->mode == SPI_START_BIT)
263                     (controller->tx_char & (1 << controller->tx_bit)));
264       controller->tx_bit--;
265       controller->mode = SPI_MIDDLE_BIT;
267   else if (controller->mode == SPI_MIDDLE_BIT)
269       controller->mode = SPI_START_BIT;
272   if (controller->mode == SPI_START_BYTE)
277       controller->mode = SPI_START_BIT;
278       controller->tx_bit = 7;
279       set_bit_port (me, cpu, M6811_PORTD, (1 << 4), ~controller->clk_pin);
284       controller->clk_pin = ~controller->clk_pin;
285       set_bit_port (me, cpu, M6811_PORTD, (1 << 4), controller->clk_pin);
289   if (controller->mode == SPI_START_BIT && controller->tx_bit < 0)
291       controller->rx_clear_scsr = 0;
298       controller->spi_event = hw_event_queue_schedule (me, controller->clock,
336   struct m68hc11spi *controller;
342   controller = hw_data (me);
356   if (controller->spi_event)
361                      controller->tx_bit + 1);
362       t = hw_event_remain_time (me, controller->spi_event);
366       t += (controller->tx_bit + 1) * 2 * controller->clock;
391   struct m68hc11spi *controller;
401   controller = hw_data (me);
406       controller->rx_clear_scsr = m68hc11_cpu->ios[M6811_SCSR]
415       if (controller->rx_clear_scsr)
417           m68hc11_cpu->ios[M6811_SPSR] &= ~controller->rx_clear_scsr;
418           controller->rx_clear_scsr = 0;
421       val = controller->rx_char;
439   struct m68hc11spi *controller;
449   controller = hw_data (me);
462           controller->clock = 1;
466           controller->clock = 2;
470           controller->clock = 8;
474           controller->clock = 16;
480           && (controller->spi_event == 0
481               || ((val & M6811_CPHA) && controller->mode == 1)))
482         controller->clk_pin = 1;
484         controller->clk_pin = 0;
486       set_bit_port (me, cpu, M6811_PORTD, (1 << 4), controller->clk_pin);
499       if (controller->rx_clear_scsr)
501           m68hc11_cpu->ios[M6811_SPSR] &= ~controller->rx_clear_scsr;
502           controller->rx_clear_scsr = 0;
508       if (controller->spi_event)
518       controller->tx_char = val;
519       controller->mode   = SPI_START_BYTE;
524         controller->clk_pin = ~controller->clk_pin;
OpenGrok
