Lines Matching defs:controller
205 struct tx3904tmr *controller)
232 controller->clock_ticks = (unsigned_4) hw_find_integer_property(me, "clock");
235 controller->ext_ticks = (unsigned_4) hw_find_integer_property(me, "ext");
237 controller->base_address = attach_address;
244 struct tx3904tmr *controller;
246 controller = HW_ZALLOC (me, struct tx3904tmr);
247 set_hw_data (me, controller);
254 controller->clock_ticks = 1;
255 controller->ext_ticks = 100;
258 attach_tx3904tmr_regs (me, controller);
261 controller->tcr =
262 controller->itmr =
263 controller->ccdr =
264 controller->pmgr =
265 controller->wtmr =
266 controller->tisr =
267 controller->trr = 0;
268 controller->cpra = controller->cprb = 0x00FFFFFF;
269 controller->ff = 0;
270 controller->last_ticks = controller->roundoff_ticks = 0;
271 controller->event = NULL;
285 struct tx3904tmr *controller = hw_data (me);
294 controller->ff = GET_PMGR_FFI(controller);
296 controller->tcr =
297 controller->itmr =
298 controller->ccdr =
299 controller->pmgr =
300 controller->wtmr =
301 controller->tisr =
302 controller->trr = 0;
303 controller->cpra = controller->cprb = 0x00FFFFFF;
304 controller->last_ticks = controller->roundoff_ticks = 0;
305 if (controller->event != NULL)
306 hw_event_queue_deschedule(me, controller->event);
307 controller->event = NULL;
327 struct tx3904tmr *controller = hw_data (me);
334 int reg_number = (address - controller->base_address) / 4;
335 int reg_offset = 3 - (address - controller->base_address) % 4;
341 case TCR_REG: register_value = controller->tcr; break;
342 case TISR_REG: register_value = controller->tisr; break;
343 case CPRA_REG: register_value = controller->cpra; break;
344 case CPRB_REG: register_value = controller->cprb; break;
345 case ITMR_REG: register_value = controller->itmr; break;
346 case CCDR_REG: register_value = controller->ccdr; break;
347 case PMGR_REG: register_value = controller->pmgr; break;
348 case WTMR_REG: register_value = controller->wtmr; break;
349 case TRR_REG: register_value = controller->trr; break;
369 struct tx3904tmr *controller = hw_data (me);
377 int reg_number = (address - controller->base_address) / 4;
378 int reg_offset = 3 - (address - controller->base_address) % 4;
387 controller->tcr = (unsigned_4) (write_byte & 0xef);
390 if (GET_TCR_TCE(controller) == 0 &&
391 GET_TCR_CRE(controller) == 1)
392 controller->trr = 0;
394 /* HW_TRACE ((me, "tcr: %08lx", (long) controller->tcr)); */
400 SET_ITMR_TIIE(controller, write_byte & 0x80);
404 SET_ITMR_TZCE(controller, write_byte & 0x01);
406 /* HW_TRACE ((me, "itmr: %08lx", (long) controller->itmr)); */
412 controller->ccdr = write_byte & 0x07;
414 /* HW_TRACE ((me, "ccdr: %08lx", (long) controller->ccdr)); */
420 SET_PMGR_TPIBE(controller, write_byte & 0x80);
421 SET_PMGR_TPIAE(controller, write_byte & 0x40);
425 SET_PMGR_FFI(controller, write_byte & 0x01);
427 /* HW_TRACE ((me, "pmgr: %08lx", (long) controller->pmgr)); */
433 SET_WTMR_TWIE(controller, write_byte & 0x80);
437 SET_WTMR_WDIS(controller, write_byte & 0x80);
438 SET_WTMR_TWC(controller, write_byte & 0x01);
440 /* HW_TRACE ((me, "wtmr: %08lx", (long) controller->wtmr)); */
450 if (controller->tisr != 0) /* any interrupts active? */
456 controller->tisr = 0;
458 /* HW_TRACE ((me, "tisr: %08lx", (long) controller->tisr)); */
464 MBLIT32(controller->cpra, (reg_offset*8)+7, (reg_offset*8), write_byte);
466 /* HW_TRACE ((me, "cpra: %08lx", (long) controller->cpra)); */
472 MBLIT32(controller->cprb, (reg_offset*8)+7, (reg_offset*8), write_byte);
474 /* HW_TRACE ((me, "cprb: %08lx", (long) controller->cprb)); */
496 struct tx3904tmr *controller = hw_data (me);
505 if (controller->last_ticks != 0)
506 warp = this_ticks - controller->last_ticks + controller->roundoff_ticks;
509 controller->last_ticks = this_ticks; /* initialize */
510 warp = controller->roundoff_ticks;
513 if (controller->event != NULL)
514 hw_event_queue_deschedule(me, controller->event);
515 controller->event = NULL;
520 switch ((int) GET_TCR_TMODE(controller))
524 if (GET_TCR_TCE(controller) == 0 ||
525 controller->trr == controller->cpra)
531 if (GET_TCR_TCE(controller) == 0)
537 if (GET_TCR_TCE(controller) == 0 &&
538 GET_WTMR_WDIS(controller) == 1)
554 if (GET_TCR_CCS(controller) == 0) /* internal system clock */
557 if (GET_TCR_CCDE(controller)) /* divisor circuit enabled? */
558 divisor = controller->clock_ticks * (1 << (1 + GET_CCDR_CDR(controller)));
560 divisor = controller->clock_ticks;
564 divisor = controller->ext_ticks;
578 controller->roundoff_ticks = remainder;
579 controller->last_ticks = this_ticks;
583 unsigned_4 next_trr = (controller
586 switch ((int) GET_TCR_TMODE(controller))
594 if (controller->trr == controller->cpra ||
595 next_trr == controller->cpra)
598 if (controller->trr == controller->cpra)
599 next_trr = controller->cpra;
601 SET_TISR_TIIS(controller);
606 if (GET_ITMR_TIIE(controller) &&
607 next_trr != controller->trr)
613 if (GET_ITMR_TZCE(controller))
624 if (next_trr == controller->cpra)
627 controller->ff ^= 1;
628 hw_port_event(me, FF_PORT, controller->ff);
629 SET_TISR_TPIAS(controller);
632 if (GET_PMGR_TPIAE(controller))
639 else if (next_trr == controller->cprb)
642 controller->ff ^= 1;
643 hw_port_event(me, FF_PORT, controller->ff);
644 SET_TISR_TPIBS(controller);
647 if (GET_PMGR_TPIBE(controller))
661 if (next_trr == controller->cpra)
663 SET_TISR_TWIS(controller);
666 if (GET_WTMR_TWIE(controller))
683 controller->trr = next_trr;
685 (long) controller->trr, (long) controller->tisr)); */
691 controller->event = hw_event_queue_schedule(me, divisor*3/4, deliver_tx3904tmr_tick, NULL);
Indexes created Sun Apr 12 00:22:20 UTC 2026