Lines Matching defs:tisr
58 4: TISR: timer interrupt status register
163 unsigned_4 tisr;
164 #define SET_TISR_TWIS(c) ((c)->tisr |= 0x08)
165 #define SET_TISR_TPIBS(c) ((c)->tisr |= 0x04)
166 #define SET_TISR_TPIAS(c) ((c)->tisr |= 0x02)
167 #define SET_TISR_TIIS(c) ((c)->tisr |= 0x01)
266 controller->tisr =
301 controller->tisr =
342 case TISR_REG: register_value = controller->tisr; break;
450 if (controller->tisr != 0) /* any interrupts active? */
456 controller->tisr = 0;
458 /* HW_TRACE ((me, "tisr: %08lx", (long) controller->tisr)); */
684 /* HW_TRACE ((me, "counter trr %ld tisr %lx",
685 (long) controller->trr, (long) controller->tisr)); */
Indexes created Mon Mar 16 00:23:04 UTC 2026