Cross Reference: /src/external/gpl3/gdb.old/dist/sim/mips/sim-main.c

Lines Matching refs:cia
54 	     address_word cia,
94 	unsigned_16 val = sim_core_read_aligned_16 (CPU, cia, read_map, pAddr);
100       value = sim_core_read_aligned_8 (CPU, cia, read_map, pAddr);
103       value = sim_core_read_misaligned_7 (CPU, cia, read_map, pAddr);
106       value = sim_core_read_misaligned_6 (CPU, cia, read_map, pAddr);
109       value = sim_core_read_misaligned_5 (CPU, cia, read_map, pAddr);
112       value = sim_core_read_aligned_4 (CPU, cia, read_map, pAddr);
115       value = sim_core_read_misaligned_3 (CPU, cia, read_map, pAddr);
118       value = sim_core_read_aligned_2 (CPU, cia, read_map, pAddr);
121       value = sim_core_read_aligned_1 (CPU, cia, read_map, pAddr);
171 	      address_word cia,
222 	sim_core_write_aligned_16 (CPU, cia, write_map, pAddr, val);
226       sim_core_write_aligned_8 (CPU, cia, write_map, pAddr, MemElem);
229       sim_core_write_misaligned_7 (CPU, cia, write_map, pAddr, MemElem);
232       sim_core_write_misaligned_6 (CPU, cia, write_map, pAddr, MemElem);
235       sim_core_write_misaligned_5 (CPU, cia, write_map, pAddr, MemElem);
238       sim_core_write_aligned_4 (CPU, cia, write_map, pAddr, MemElem);
241       sim_core_write_misaligned_3 (CPU, cia, write_map, pAddr, MemElem);
244       sim_core_write_aligned_2 (CPU, cia, write_map, pAddr, MemElem);
247       sim_core_write_aligned_1 (CPU, cia, write_map, pAddr, MemElem);
260 	  address_word cia,
284 	  address_word cia,
314 		address_word cia,
326 	  address_word cia,
344   sim_io_printf(SD,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia));
404 	      address_word cia)
407     sim_io_eprintf (SD, "PENDING_DRAIN - 0x%lx - pending_in = %d, pending_out = %d, pending_total = %d\n", (unsigned long) cia, PENDING_IN, PENDING_OUT, PENDING_TOTAL);
414 	sim_engine_abort (SD, CPU, cia, "PENDING_DRAIN - Mis-match on pending update pointers\n");
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