Lines Matching defs:REGISTERS
68 /* FPU registers must be one of the following types. All other values
110 /* For some MIPS targets, the HI/LO registers have certain timing
189 destinations, schedule two writes. For floating point registers,
326 vector of registers. The internal simulator engine then uses
329 unsigned_word registers[LAST_EMBED_REGNUM + 1];
332 #define REGISTERS (MIPS_SIM_CPU (CPU)->registers)
334 #define GPR (®ISTERS[0])
335 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
337 #define LO (REGISTERS[33])
338 #define HI (REGISTERS[34])
340 #define PC (REGISTERS[PCIDX])
341 #define CAUSE (REGISTERS[36])
343 #define SR (REGISTERS[SRIDX]) /* CPU status register */
345 #define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */
347 #define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */
349 #define Debug (REGISTERS[86])
350 #define DEPC (REGISTERS[87])
351 #define EPC (REGISTERS[88])
352 #define ACX (REGISTERS[89])
363 #define DSPLO(N) (REGISTERS[DSPLO_REGNUM[N]])
364 #define DSPHI(N) (REGISTERS[DSPHI_REGNUM[N]])
367 #define DSPCR (REGISTERS[DSPCRIDX])
412 /* The following are pseudonyms for standard registers */
413 #define ZERO (REGISTERS[0])
414 #define V0 (REGISTERS[2])
415 #define A0 (REGISTERS[4])
416 #define A1 (REGISTERS[5])
417 #define A2 (REGISTERS[6])
418 #define A3 (REGISTERS[7])
420 #define T8 (REGISTERS[T8IDX])
422 #define SP (REGISTERS[SPIDX])
424 #define RA (REGISTERS[RAIDX])
426 /* While space is allocated in the main registers arrray for some of
427 the COP0 registers, that space isn't sufficient. Unknown COP0
428 registers overflow into the array below */
435 /* While space is allocated for the floating point registers in the
436 main registers array, they are stored separatly. This is because
438 general-purpose or system specific registers. */
504 #define status_FR (1 << 26) /* enables MIPS III additional FP registers */
Indexes created Thu Apr 02 00:23:07 UTC 2026