Lines Matching defs:timer_nr
286 int timer_nr,
297 if ( timer_nr == 6 )
303 *(uint8_t*)dest = timers->reg[timer_nr].mode;
308 if ( timer_nr == 6 )
312 else if ( timer_nr == 0 || timer_nr == 2 )
314 val16 = (timers->reg[timer_nr].mode << 8)
315 | timers->reg[timer_nr+1].mode;
320 hw_abort (me, "bad read size of 2 bytes to TM%dMD.", timer_nr);
325 if ( timer_nr == 0 )
335 hw_abort (me, "bad read size of 4 bytes to TM%dMD.", timer_nr);
341 nr_bytes, timer_nr);
349 int timer_nr,
361 if ( timer_nr < NR_8BIT_TIMERS )
363 *(uint8_t*)dest = timers->reg[timer_nr].base;
368 if ( timer_nr == 1 || timer_nr == 3 )
370 hw_abort (me, "bad read size of 2 bytes to TM%dBR.", timer_nr);
374 if ( timer_nr < NR_8BIT_TIMERS )
376 val16 = (timers->reg[timer_nr].base<<8)
377 | timers->reg[timer_nr+1].base;
381 val16 = timers->reg[timer_nr].base;
388 if ( timer_nr == 0 )
394 else if ( timer_nr == 4 )
401 hw_abort (me, "bad read size of 4 bytes to TM%dBR.", timer_nr);
407 nr_bytes, timer_nr);
415 int timer_nr,
421 if ( NULL == timers->timer[timer_nr].event )
424 if ( timer_nr == 6 )
430 val = timers->reg[timer_nr].base;
435 if ( timer_nr == 6 ) /* timer 6 is an up counter. */
437 val = hw_event_queue_time(me) - timers->timer[timer_nr].start;
445 val = timers->timer[timer_nr].start + timers->timer[timer_nr].div_ratio
473 int timer_nr,
480 switch ( timer_nr ) {
504 if ( timer_nr == TM6CA )
508 else if ( timer_nr == TM6CB )
571 long timer_nr = (uintptr_t) data;
575 if ( (timers->reg[timer_nr].mode & count_mask) != 0 )
583 for ( next_timer = timer_nr+1; next_timer < NR_REG_TIMERS; ++next_timer )
593 timers->timer[timer_nr].start = hw_event_queue_time(me);
595 timers->timer[timer_nr].event
596 = hw_event_queue_schedule (me, timers->timer[timer_nr].div_ratio,
597 do_counter_event, (void *)(uintptr_t)timer_nr);
601 timers->timer[timer_nr].event = NULL;
612 long timer_nr = (uintptr_t) data;
615 if ( (timers->reg[timer_nr].mode & count_mask) != 0 )
618 hw_port_event (me, timer_nr, 1);
621 timers->timer[timer_nr].start = hw_event_queue_time(me);
623 timers->timer[timer_nr].event
624 = hw_event_queue_schedule (me, timers->timer[timer_nr].div_ratio,
625 do_counter6_event, (void *)(uintptr_t)timer_nr);
629 timers->timer[timer_nr].event = NULL;
637 int timer_nr,
655 timers->reg[timer_nr].base = buf8[0];
659 if ( timer_nr == 1 || timer_nr == 3 )
661 hw_abort (me, "bad write size of 2 bytes to TM%dBR.", timer_nr);
665 if ( timer_nr < NR_8BIT_TIMERS )
667 timers->reg[timer_nr].base = buf8[0];
668 timers->reg[timer_nr+1].base = buf8[1];
672 timers->reg[timer_nr].base = buf16[0];
678 if ( timer_nr == 0 )
685 else if ( timer_nr == 4 )
692 hw_abort (me, "bad write size of 4 bytes to TM%dBR.", timer_nr);
698 nr_bytes, timer_nr);
706 long timer_nr,
718 timer_nr);
722 timers->reg[timer_nr].mode = mode_val;
742 if ( timer_nr == 0 || timer_nr == 4 )
744 hw_abort(me, "Timer %ld cannot be cascaded.", timer_nr);
749 div_ratio = timers->reg[timer_nr].base;
752 if ( timer_nr < NR_8BIT_TIMERS )
754 for ( i = timer_nr + 1; i <= 3; ++i )
767 | (timers->reg[i].base << (8*(i-timer_nr)));
778 next_mode_val = timers->reg[timer_nr+1].mode;
786 ASSERT(timers->timer[timer_nr+1].event == NULL);
787 ASSERT(timers->timer[timer_nr+1].div_ratio == 0);
788 div_ratio = div_ratio | (timers->reg[timer_nr+1].base << 16);
792 timers->timer[timer_nr].div_ratio = div_ratio;
794 if ( NULL != timers->timer[timer_nr].event )
796 hw_event_queue_deschedule (me, timers->timer[timer_nr].event);
797 timers->timer[timer_nr].event = NULL;
803 timers->timer[timer_nr].start = hw_event_queue_time(me);
804 timers->timer[timer_nr].event
807 (void *)(uintptr_t)timer_nr);
814 if ( NULL != timers->timer[timer_nr].event )
816 ASSERT((timers->reg[timer_nr].mode & clock_mask) != clk_cascaded);
817 hw_event_queue_deschedule (me, timers->timer[timer_nr].event);
818 timers->timer[timer_nr].event = NULL;
822 if ( (timers->reg[timer_nr].mode & clock_mask) == clk_cascaded )
824 ASSERT(timers->timer[timer_nr].event == NULL);
841 long timer_nr = 6;
893 timers->timer[timer_nr].div_ratio = div_ratio;
894 if ( NULL != timers->timer[timer_nr].event )
896 hw_event_queue_deschedule (me, timers->timer[timer_nr].event);
897 timers->timer[timer_nr].event = NULL;
903 timers->timer[timer_nr].start = hw_event_queue_time(me);
904 timers->timer[timer_nr].event
907 (void *)(uintptr_t)timer_nr);
913 if ( NULL != timers->timer[timer_nr].event )
915 hw_event_queue_deschedule (me, timers->timer[timer_nr].event);
916 timers->timer[timer_nr].event = NULL;
926 int timer_nr,
933 switch ( timer_nr ) {
957 if ( timer_nr == TM6CA )
961 else if ( timer_nr == TM6CB )
Indexes created Tue Sep 15 00:24:42 UTC 2026