Lines Matching refs:timers
31 mn103tim - mn103002 timers (8 and 16 bit)
36 Implements the mn103002 8 and 16 bit timers as described in the mn103002 user guide.
41 reg = <8bit-timers-addr> <8bit-timers-size> <16bit-timers-addr> <16bit-timers-size>
49 /* The timers' register address blocks */
170 struct mn103tim *timers)
188 timers->block[i].base = attach_address;
192 timers->block[i].bound = attach_address + (attach_size - 1);
203 struct mn103tim *timers;
206 timers = HW_ZALLOC (me, struct mn103tim);
207 set_hw_data (me, timers);
213 attach_mn103tim_regs (me, timers);
215 /* Initialize the timers */
218 timers->reg[i].mode = 0x00;
219 timers->reg[i].base = 0;
223 timers->timer[i].event = NULL;
224 timers->timer[i].div_ratio = 0;
225 timers->timer[i].start = 0;
227 timers->tm6md0 = 0x00;
228 timers->tm6md1 = 0x00;
229 timers->tm6bc = 0x0000;
230 timers->tm6ca = 0x0000;
231 timers->tm6cb = 0x0000;
232 timers->tm6mda = 0x00;
233 timers->tm6mdb = 0x00;
242 struct mn103tim *timers,
246 offset = address - timers->block[0].base;
285 struct mn103tim *timers,
299 *(uint8_t*)dest = timers->tm6md0;
303 *(uint8_t*)dest = timers->reg[timer_nr].mode;
310 *(uint16_t *)dest = (timers->tm6md0 << 8) | timers->tm6md1;
314 val16 = (timers->reg[timer_nr].mode << 8)
315 | timers->reg[timer_nr+1].mode;
327 val32 = (timers->reg[0].mode << 24 )
328 | (timers->reg[1].mode << 16)
329 | (timers->reg[2].mode << 8)
330 | timers->reg[3].mode;
348 struct mn103tim *timers,
363 *(uint8_t*)dest = timers->reg[timer_nr].base;
376 val16 = (timers->reg[timer_nr].base<<8)
377 | timers->reg[timer_nr+1].base;
381 val16 = timers->reg[timer_nr].base;
390 val32 = (timers->reg[0].base << 24) | (timers->reg[1].base << 16)
391 | (timers->reg[2].base << 8) | timers->reg[3].base;
396 val32 = (timers->reg[4].base << 16) | timers->reg[5].base;
414 struct mn103tim *timers,
421 if ( NULL == timers->timer[timer_nr].event )
430 val = timers->reg[timer_nr].base;
437 val = hw_event_queue_time(me) - timers->timer[timer_nr].start;
445 val = timers->timer[timer_nr].start + timers->timer[timer_nr].div_ratio
472 struct mn103tim *timers,
482 *(uint8_t *)dest = timers->tm6mda;
486 *(uint8_t *)dest = timers->tm6mdb;
490 *(uint8_t *)dest = timers->tm6ca;
494 *(uint8_t *)dest = timers->tm6cb;
506 *(uint16_t *)dest = timers->tm6ca;
510 *(uint16_t *)dest = timers->tm6cb;
532 struct mn103tim *timers = hw_data (me);
537 timer_reg = decode_addr (me, timers, base);
543 read_mode_reg(me, timers, timer_reg-FIRST_MODE_REG, dest, nr_bytes);
547 read_base_reg(me, timers, timer_reg-FIRST_BASE_REG, dest, nr_bytes);
551 read_counter(me, timers, timer_reg-FIRST_COUNTER, dest, nr_bytes);
555 read_special_timer6_reg(me, timers, timer_reg, dest, nr_bytes);
570 struct mn103tim *timers = hw_data(me);
575 if ( (timers->reg[timer_nr].mode & count_mask) != 0 )
585 if ( (timers->reg[next_timer].mode & clock_mask) != clk_cascaded )
593 timers->timer[timer_nr].start = hw_event_queue_time(me);
595 timers->timer[timer_nr].event
596 = hw_event_queue_schedule (me, timers->timer[timer_nr].div_ratio,
601 timers->timer[timer_nr].event = NULL;
611 struct mn103tim *timers = hw_data(me);
615 if ( (timers->reg[timer_nr].mode & count_mask) != 0 )
621 timers->timer[timer_nr].start = hw_event_queue_time(me);
623 timers->timer[timer_nr].event
624 = hw_event_queue_schedule (me, timers->timer[timer_nr].div_ratio,
629 timers->timer[timer_nr].event = NULL;
636 struct mn103tim *timers,
655 timers->reg[timer_nr].base = buf8[0];
667 timers->reg[timer_nr].base = buf8[0];
668 timers->reg[timer_nr+1].base = buf8[1];
672 timers->reg[timer_nr].base = buf16[0];
680 timers->reg[0].base = buf8[0];
681 timers->reg[1].base = buf8[1];
682 timers->reg[2].base = buf8[2];
683 timers->reg[3].base = buf8[3];
687 timers->reg[4].base = buf16[0];
688 timers->reg[5].base = buf16[1];
705 struct mn103tim *timers,
709 /* for timers 0 to 5 */
722 timers->reg[timer_nr].mode = mode_val;
739 /* For cascaded timers, */
749 div_ratio = timers->reg[timer_nr].base;
756 next_mode_val = timers->reg[i].mode;
764 ASSERT(timers->timer[i].event == NULL);
765 ASSERT(timers->timer[i].div_ratio == 0);
767 | (timers->reg[i].base << (8*(i-timer_nr)));
778 next_mode_val = timers->reg[timer_nr+1].mode;
786 ASSERT(timers->timer[timer_nr+1].event == NULL);
787 ASSERT(timers->timer[timer_nr+1].div_ratio == 0);
788 div_ratio = div_ratio | (timers->reg[timer_nr+1].base << 16);
792 timers->timer[timer_nr].div_ratio = div_ratio;
794 if ( NULL != timers->timer[timer_nr].event )
796 hw_event_queue_deschedule (me, timers->timer[timer_nr].event);
797 timers->timer[timer_nr].event = NULL;
803 timers->timer[timer_nr].start = hw_event_queue_time(me);
804 timers->timer[timer_nr].event
814 if ( NULL != timers->timer[timer_nr].event )
816 ASSERT((timers->reg[timer_nr].mode & clock_mask) != clk_cascaded);
817 hw_event_queue_deschedule (me, timers->timer[timer_nr].event);
818 timers->timer[timer_nr].event = NULL;
822 if ( (timers->reg[timer_nr].mode & clock_mask) == clk_cascaded )
824 ASSERT(timers->timer[timer_nr].event == NULL);
834 struct mn103tim *timers,
843 unsigned_word offset = address - timers->block[0].base;
854 timers->tm6md0 = mode_val0;
874 timers->tm6md1 = mode_val1;
892 div_ratio = timers->tm6ca; /* binary counter for timer 6 */
893 timers->timer[timer_nr].div_ratio = div_ratio;
894 if ( NULL != timers->timer[timer_nr].event )
896 hw_event_queue_deschedule (me, timers->timer[timer_nr].event);
897 timers->timer[timer_nr].event = NULL;
903 timers->timer[timer_nr].start = hw_event_queue_time(me);
904 timers->timer[timer_nr].event
913 if ( NULL != timers->timer[timer_nr].event )
915 hw_event_queue_deschedule (me, timers->timer[timer_nr].event);
916 timers->timer[timer_nr].event = NULL;
925 struct mn103tim *timers,
935 timers->tm6mda = *(uint8_t *)source;
939 timers->tm6mdb = *(uint8_t *)source;
943 timers->tm6ca = *(uint8_t *)source;
947 timers->tm6cb = *(uint8_t *)source;
959 timers->tm6ca = *(uint16_t *)source;
963 timers->tm6cb = *(uint16_t *)source;
985 struct mn103tim *timers = hw_data (me);
991 timer_reg = decode_addr (me, timers, base);
999 write_tm6md(me, timers, base, source, nr_bytes);
1003 write_mode_reg(me, timers, timer_reg-FIRST_MODE_REG,
1009 write_base_reg(me, timers, timer_reg-FIRST_BASE_REG, source, nr_bytes);
1017 write_special_timer6_reg(me, timers, timer_reg, source, nr_bytes);
Indexes created Thu Apr 23 00:23:13 UTC 2026