Lines Matching refs:CPU
80 /* Extract a field value from CPU register using the given REGSEL selector.
106 /* Write a value into CPU subregister pointed by reg and regsel. */
131 imem_wordaddr_to_byteaddr (SIM_CPU *cpu, uint16_t wa)
133 struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
140 imem_byteaddr_to_wordaddr (SIM_CPU *cpu, uint32_t ba)
146 /* Store "nbytes" into DMEM "addr" from CPU register file, starting with
149 pru_reg2dmem (SIM_CPU *cpu, uint32_t addr, unsigned int nbytes,
152 struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
155 bool standalone = (STATE_OPEN_KIND (CPU_STATE (cpu)) == SIM_OPEN_STANDALONE);
159 sim_core_signal (CPU_STATE (cpu), cpu, PC_byteaddr, write_map,
166 sim_core_signal (CPU_STATE (cpu), cpu, PC_byteaddr, write_map,
172 sim_io_eprintf (CPU_STATE (cpu),
174 RAISE_SIGILL (CPU_STATE (cpu));
178 TRACE_MEMORY (cpu, "write of %d bytes to %08x", nbytes, addr);
181 sim_core_write_1 (cpu,
185 extract_regval (CPU.regs[regn], regb));
196 /* Load "nbytes" from DMEM "addr" into CPU register file, starting with
199 pru_dmem2reg (SIM_CPU *cpu, uint32_t addr, unsigned int nbytes,
202 struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
205 bool standalone = (STATE_OPEN_KIND (CPU_STATE (cpu)) == SIM_OPEN_STANDALONE);
209 sim_core_signal (CPU_STATE (cpu), cpu, PC_byteaddr, read_map,
219 sim_core_signal (CPU_STATE (cpu), cpu, PC_byteaddr, read_map,
225 sim_io_eprintf (CPU_STATE (cpu),
227 RAISE_SIGILL (CPU_STATE (cpu));
232 TRACE_MEMORY (cpu, "read of %d bytes from %08x", nbytes, addr);
235 b = sim_core_read_1 (cpu, PC_byteaddr, read_map, addr++);
239 write_regval (b, &CPU.regs[regn], regb);
252 set_initial_gprs (SIM_CPU *cpu)
254 struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
258 CPU_PC_SET (cpu, 0);
262 for (i = 0; i < ARRAY_SIZE (CPU.regs); i++)
263 CPU.regs[i] = 0;
264 for (i = 0; i < ARRAY_SIZE (CPU.macregs); i++)
265 CPU.macregs[i] = 0;
267 CPU.loop.looptop = CPU.loop.loopend = 0;
268 CPU.loop.loop_in_progress = 0;
269 CPU.loop.loop_counter = 0;
271 CPU.carry = 0;
272 CPU.insts = 0;
273 CPU.cycles = 0;
276 CPU.ctable[0] = 0x00020000;
277 CPU.ctable[1] = 0x48040000;
278 CPU.ctable[2] = 0x4802a000;
279 CPU.ctable[3] = 0x00030000;
280 CPU.ctable[4] = 0x00026000;
281 CPU.ctable[5] = 0x48060000;
282 CPU.ctable[6] = 0x48030000;
283 CPU.ctable[7] = 0x00028000;
284 CPU.ctable[8] = 0x46000000;
285 CPU.ctable[9] = 0x4a100000;
286 CPU.ctable[10] = 0x48318000;
287 CPU.ctable[11] = 0x48022000;
288 CPU.ctable[12] = 0x48024000;
289 CPU.ctable[13] = 0x48310000;
290 CPU.ctable[14] = 0x481cc000;
291 CPU.ctable[15] = 0x481d0000;
292 CPU.ctable[16] = 0x481a0000;
293 CPU.ctable[17] = 0x4819c000;
294 CPU.ctable[18] = 0x48300000;
295 CPU.ctable[19] = 0x48302000;
296 CPU.ctable[20] = 0x48304000;
297 CPU.ctable[21] = 0x00032400;
298 CPU.ctable[22] = 0x480c8000;
299 CPU.ctable[23] = 0x480ca000;
300 CPU.ctable[24] = 0x00000000;
301 CPU.ctable[25] = 0x00002000;
302 CPU.ctable[26] = 0x0002e000;
303 CPU.ctable[27] = 0x00032000;
304 CPU.ctable[28] = 0x00000000;
305 CPU.ctable[29] = 0x49000000;
306 CPU.ctable[30] = 0x40000000;
307 CPU.ctable[31] = 0x80000000;
330 pru_sim_xin_mac (SIM_DESC sd, SIM_CPU *cpu, unsigned int rd_regn,
333 struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
342 write_regval (CPU.macregs[rd_regn - 25] >> (rdb * 8),
343 &CPU.regs[rd_regn],
355 pru_sim_xin (SIM_DESC sd, SIM_CPU *cpu, unsigned int wba,
358 struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
362 pru_sim_xin_mac (sd, cpu, rd_regn, rdb, length);
371 val = extract_regval (CPU.scratchpads[wba][rd_regn], rdb);
372 write_regval (val, &CPU.regs[rd_regn], rdb);
386 write_regval (fillbyte, &CPU.regs[rd_regn], rdb);
402 pru_sim_xout_mac (SIM_DESC sd, SIM_CPU *cpu, unsigned int rd_regn,
405 struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
416 write_regval (CPU.regs[rd_regn] >> (rdb * 8),
417 &CPU.macregs[rd_regn - 25],
427 && (CPU.macregs[PRU_MACREG_MODE] & MAC_R25_MAC_MODE_MASK))
432 CPU.macregs[PRU_MACREG_OP_0] = CPU.regs[28];
433 CPU.macregs[PRU_MACREG_OP_1] = CPU.regs[29];
435 prod = CPU.macregs[PRU_MACREG_OP_0];
436 prod *= (uint64_t)CPU.macregs[PRU_MACREG_OP_1];
438 oldsum = CPU.macregs[PRU_MACREG_ACC_L];
439 oldsum += (uint64_t)CPU.macregs[PRU_MACREG_ACC_H] << 32;
442 CPU.macregs[PRU_MACREG_PROD_L] = sum & 0xfffffffful;
443 CPU.macregs[PRU_MACREG_PROD_H] = sum >> 32;
444 CPU.macregs[PRU_MACREG_ACC_L] = CPU.macregs[PRU_MACREG_PROD_L];
445 CPU.macregs[PRU_MACREG_ACC_H] = CPU.macregs[PRU_MACREG_PROD_H];
448 CPU.macregs[PRU_MACREG_MODE] |= MAC_R25_ACC_CARRY_MASK;
451 && (CPU.macregs[PRU_MACREG_MODE] & MAC_R25_ACC_CARRY_MASK))
454 CPU.macregs[PRU_MACREG_MODE] &= ~MAC_R25_ACC_CARRY_MASK;
455 CPU.macregs[PRU_MACREG_ACC_L] = 0;
456 CPU.macregs[PRU_MACREG_ACC_H] = 0;
463 pru_sim_xout (SIM_DESC sd, SIM_CPU *cpu, unsigned int wba,
466 struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
470 pru_sim_xout_mac (sd, cpu, rd_regn, rdb, length);
479 val = extract_regval (CPU.regs[rd_regn], rdb);
480 write_regval (val, &CPU.scratchpads[wba][rd_regn], rdb);
494 pru_sim_xchg (SIM_DESC sd, SIM_CPU *cpu, unsigned int wba,
497 struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
506 valr = extract_regval (CPU.regs[rd_regn], rdb);
507 vals = extract_regval (CPU.scratchpads[wba][rd_regn], rdb);
508 write_regval (valr, &CPU.scratchpads[wba][rd_regn], rdb);
509 write_regval (vals, &CPU.regs[rd_regn], rdb);
523 pru_sim_syscall (SIM_DESC sd, SIM_CPU *cpu)
525 struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
529 const uint32_t syscall_num = CPU.regs[1];
532 ret = sim_syscall (cpu, syscall_num,
533 CPU.regs[14], CPU.regs[15],
534 CPU.regs[16], CPU.regs[17]);
535 CPU.regs[14] = ret;
542 SIM_CPU *cpu = STATE_CPU (sd, 0);
543 struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
550 inst = sim_core_read_4 (cpu, PC_byteaddr, exec_map, PC_byteaddr);
551 TRACE_MEMORY (cpu, "read of insn 0x%08x from %08x", inst, PC_byteaddr);
562 TRACE_DISASM (cpu, PC_byteaddr);
566 if ((CPU
568 CPU.macregs[PRU_MACREG_OP_0] = CPU.regs[28];
569 CPU.macregs[PRU_MACREG_OP_1] = CPU.regs[29];
590 write_regval (_RDVAL, &CPU.regs[RD_REGN], RDSEL);
593 CPU.regs[30] = 0;
594 CPU.regs[31] = 0;
607 if ((CPU.macregs[PRU_MACREG_MODE] & MAC_R25_MAC_MODE_MASK) == 0)
610 prod = CPU.macregs[PRU_MACREG_OP_0];
611 prod *= (uint64_t)CPU.macregs[PRU_MACREG_OP_1];
612 CPU.macregs[PRU_MACREG_PROD_L] = prod & 0xfffffffful;
613 CPU.macregs[PRU_MACREG_PROD_H] = prod >> 32;
616 CPU.macregs[PRU_MACREG_ACC_L] = 0;
617 CPU.macregs[PRU_MACREG_ACC_H] = 0;
621 CPU.insts += 1; /* One instruction completed ... */
622 CPU.cycles += 1; /* ... and it takes a single cycle. */
629 CPU.cycles += 2;
652 pru_pc_get (sim_cpu *cpu)
654 struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
657 return imem_wordaddr_to_byteaddr (cpu, pru_cpu->pc);
662 pru_pc_set (sim_cpu *cpu, sim_cia pc)
664 struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
667 pru_cpu->pc = imem_byteaddr_to_wordaddr (cpu, pc);
673 pru_store_register (SIM_CPU *cpu, int rn, const void *memory, int length)
675 struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
684 CPU.regs[rn] = ival;
686 pru_pc_set (cpu, ival);
698 pru_fetch_register (SIM_CPU *cpu, int rn, void *memory, int length)
700 struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
708 ival = CPU.regs[rn];
710 ival = pru_pc_get (cpu);
737 pru_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt, char *arg,
776 /* The cpu data is kept in a separately allocated chunk of memory. */
820 /* CPU specific initialization. */
823 SIM_CPU *cpu = STATE_CPU (sd, i);
825 CPU_REG_STORE (cpu) = pru_store_register;
826 CPU_REG_FETCH (cpu) = pru_fetch_register;
827 CPU_PC_FETCH (cpu) = pru_pc_get;
828 CPU_PC_STORE (cpu) = pru_pc_set;
830 set_initial_gprs (cpu);
856 SIM_CPU *cpu = STATE_CPU (sd, 0);
857 struct pru_regset *pru_cpu = PRU_SIM_CPU (cpu);
863 sim_pc_set (cpu, addr);
Indexes created Sat Feb 28 05:31:39 UTC 2026