Lines Matching defs:riscv_cpu
72 struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
76 riscv_cpu->regs[rd] = val;
102 struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
110 riscv_cpu->csr.fcsr = (riscv_cpu->csr.fcsr & ~0xe0) | (val << 5);
115 riscv_cpu->csr.fcsr = (riscv_cpu->csr.fcsr & ~0x1f) | val;
120 riscv_cpu->csr.frm = (val >> 5) & 0x7;
121 riscv_cpu->csr.fflags = val & 0x1f;
159 struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
173 sim_cia pc = riscv_cpu->pc + 4;
182 riscv_cpu->regs[rs1],
184 riscv_cpu->regs[rs2],
192 store_rd (cpu, rd, riscv_cpu->regs[rs1] + riscv_cpu->regs[rs2]);
199 EXTEND32 (riscv_cpu->regs[rs1] + riscv_cpu->regs[rs2]));
204 store_rd (cpu, rd, riscv_cpu->regs[rs1] + i_imm);
210 store_rd (cpu, rd, EXTEND32 (riscv_cpu->regs[rs1] + i_imm));
215 store_rd (cpu, rd, riscv_cpu->regs[rs1] & riscv_cpu->regs[rs2]);
220 store_rd (cpu, rd, riscv_cpu->regs[rs1] & i_imm);
225 store_rd (cpu, rd, riscv_cpu->regs[rs1] | riscv_cpu->regs[rs2]);
230 store_rd (cpu, rd, riscv_cpu->regs[rs1] | i_imm);
235 store_rd (cpu, rd, riscv_cpu->regs[rs1] ^ riscv_cpu->regs[rs2]);
240 store_rd (cpu, rd, riscv_cpu->regs[rs1] ^ i_imm);
245 store_rd (cpu, rd, riscv_cpu->regs[rs1] - riscv_cpu->regs[rs2]);
252 EXTEND32 (riscv_cpu->regs[rs1] - riscv_cpu->regs[rs2]));
263 riscv_cpu->regs[rs1] << (riscv_cpu->regs[rs2] & u_imm));
270 (uint32_t) riscv_cpu->regs[rs1] << (riscv_cpu->regs[rs2] & 0x1f)));
276 sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
278 store_rd (cpu, rd, riscv_cpu->regs[rs1] << shamt_imm);
285 EXTEND32 ((uint32_t) riscv_cpu->regs[rs1] << shamt_imm));
292 riscv_cpu->regs[rs1] >> (riscv_cpu->regs[rs2] & u_imm));
299 (uint32_t) riscv_cpu->regs[rs1] >> (riscv_cpu->regs[rs2] & 0x1f)));
305 sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
307 store_rd (cpu, rd, riscv_cpu->regs[rs1] >> shamt_imm);
314 EXTEND32 ((uint32_t) riscv_cpu->regs[rs1] >> shamt_imm));
320 tmp = ashiftrt (riscv_cpu->regs[rs1], riscv_cpu->regs[rs2] & 0x1f);
322 tmp = ashiftrt64 (riscv_cpu->regs[rs1], riscv_cpu->regs[rs2] & 0x3f);
330 ashiftrt ((int32_t) riscv_cpu->regs[rs1],
331 riscv_cpu->regs[rs2] & 0x1f)));
339 sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
341 tmp = ashiftrt (riscv_cpu->regs[rs1], shamt_imm);
344 tmp = ashiftrt64 (riscv_cpu->regs[rs1], shamt_imm);
352 ashiftrt ((int32_t) riscv_cpu->regs[rs1], shamt_imm)));
357 !!((signed_word) riscv_cpu->regs[rs1] <
358 (signed_word) riscv_cpu->regs[rs2]));
362 store_rd (cpu, rd, !!((unsigned_word) riscv_cpu->regs[rs1] <
363 (unsigned_word) riscv_cpu->regs[rs2]));
367 store_rd (cpu, rd, !!((signed_word) riscv_cpu->regs[rs1] <
372 store_rd (cpu, rd, !!((unsigned_word) riscv_cpu->regs[rs1] <
378 store_rd (cpu, rd, riscv_cpu->pc + u_imm);
384 if (riscv_cpu->regs[rs1] == riscv_cpu->regs[rs2])
386 pc = riscv_cpu->pc + sb_imm;
394 if ((signed_word) riscv_cpu->regs[rs1] <
395 (signed_word) riscv_cpu->regs[rs2])
397 pc = riscv_cpu->pc + sb_imm;
405 if ((unsigned_word) riscv_cpu->regs[rs1] <
406 (unsigned_word) riscv_cpu->regs[rs2])
408 pc = riscv_cpu->pc + sb_imm;
416 if ((signed_word) riscv_cpu->regs[rs1] >=
417 (signed_word) riscv_cpu->regs[rs2])
419 pc = riscv_cpu->pc + sb_imm;
427 if ((unsigned_word) riscv_cpu->regs[rs1] >=
428 (unsigned_word) riscv_cpu->regs[rs2])
430 pc = riscv_cpu->pc + sb_imm;
438 if (riscv_cpu->regs[rs1] != riscv_cpu->regs[rs2])
440 pc = riscv_cpu->pc + sb_imm;
447 store_rd (cpu, rd, riscv_cpu->pc + 4);
448 pc = riscv_cpu->pc + EXTRACT_JTYPE_IMM (iw);
453 pc = riscv_cpu->regs[rs1] + i_imm;
454 store_rd (cpu, rd, riscv_cpu->pc + 4);
463 sim_core_read_unaligned_8 (cpu, riscv_cpu->pc, read_map,
464 riscv_cpu->regs[rs1] + i_imm));
470 sim_core_read_unaligned_4 (cpu, riscv_cpu->pc, read_map,
471 riscv_cpu
477 sim_core_read_unaligned_4 (cpu, riscv_cpu->pc, read_map,
478 riscv_cpu->regs[rs1] + i_imm));
484 sim_core_read_unaligned_2 (cpu, riscv_cpu->pc, read_map,
485 riscv_cpu->regs[rs1] + i_imm)));
491 sim_core_read_unaligned_2 (cpu, riscv_cpu->pc, read_map,
492 riscv_cpu->regs[rs1] + i_imm));
498 sim_core_read_unaligned_1 (cpu, riscv_cpu->pc, read_map,
499 riscv_cpu->regs[rs1] + i_imm)));
505 sim_core_read_unaligned_1 (cpu, riscv_cpu->pc, read_map,
506 riscv_cpu->regs[rs1] + i_imm));
512 sim_core_write_unaligned_8 (cpu, riscv_cpu->pc, write_map,
513 riscv_cpu->regs[rs1] + s_imm,
514 riscv_cpu->regs[rs2]);
519 sim_core_write_unaligned_4 (cpu, riscv_cpu->pc, write_map,
520 riscv_cpu->regs[rs1] + s_imm,
521 riscv_cpu->regs[rs2]);
526 sim_core_write_unaligned_2 (cpu, riscv_cpu->pc, write_map,
527 riscv_cpu->regs[rs1] + s_imm,
528 riscv_cpu->regs[rs2]);
533 sim_core_write_unaligned_1 (cpu, riscv_cpu->pc, write_map,
534 riscv_cpu->regs[rs1] + s_imm,
535 riscv_cpu->regs[rs2]);
545 fetch_csr (cpu, #name, num, &riscv_cpu->csr.name)); \
546 store_csr (cpu, #name, num, &riscv_cpu->csr.name, \
547 riscv_cpu->csr.name & !riscv_cpu->regs[rs1]); \
560 fetch_csr (cpu, #name, num, &riscv_cpu->csr.name)); \
561 store_csr (cpu, #name, num, &riscv_cpu->csr.name, \
562 riscv_cpu->csr.name | riscv_cpu->regs[rs1]); \
575 fetch_csr (cpu, #name, num, &riscv_cpu->csr.name)); \
576 store_csr (cpu, #name, num, &riscv_cpu->csr.name, \
577 riscv_cpu->regs[rs1]); \
587 fetch_csr (cpu, "cycle", CSR_CYCLE, &riscv_cpu->csr.cycle));
593 fetch_csr (cpu, "cycleh", CSR_CYCLEH, &riscv_cpu->csr.cycleh));
599 &riscv_cpu->csr.instret));
606 &riscv_cpu->csr.instreth));
611 fetch_csr (cpu, "time", CSR_TIME, &riscv_cpu->csr.time));
617 fetch_csr (cpu, "timeh", CSR_TIMEH, &riscv_cpu->csr.timeh));
628 sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_stopped, SIM_SIGTRAP);
632 riscv_cpu->a0 = sim_syscall (cpu, riscv_cpu->a7, riscv_cpu->a0,
633 riscv_cpu->a1, riscv_cpu->a2, riscv_cpu->a3);
637 sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL);
688 struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
697 sim_cia pc = riscv_cpu->pc + 4;
706 if (riscv_cpu->regs[rs1] == dividend_max && riscv_cpu->regs[rs2] == -1)
708 else if (riscv_cpu->regs[rs2])
709 tmp = (signed_word) riscv_cpu->regs[rs1] /
710 (signed_word) riscv_cpu->regs[rs2];
719 if (EXTEND32 (riscv_cpu->regs[rs2]) == -1)
721 else if (EXTEND32 (riscv_cpu->regs[rs2]))
722 tmp = EXTEND32 (riscv_cpu->regs[rs1]) / EXTEND32 (riscv_cpu->regs[rs2]);
730 if (riscv_cpu->regs[rs2])
731 store_rd (cpu, rd, (unsigned_word) riscv_cpu->regs[rs1]
732 / (unsigned_word) riscv_cpu->regs[rs2]);
740 if ((uint32_t) riscv_cpu->regs[rs2])
741 tmp = (uint32_t) riscv_cpu->regs[rs1] / (uint32_t) riscv_cpu->regs[rs2];
749 store_rd (cpu, rd, riscv_cpu->regs[rs1] * riscv_cpu->regs[rs2]);
755 store_rd (cpu, rd, EXTEND32 ((int32_t) riscv_cpu->regs[rs1]
756 * (int32_t) riscv_cpu->regs[rs2]));
763 ((int64_t)(signed_word) riscv_cpu->regs[rs1]
764 * (int64_t)(signed_word) riscv_cpu->regs[rs2]) >> 32);
766 store_rd (cpu, rd, mulh (riscv_cpu->regs[rs1], riscv_cpu->regs[rs2]));
772 store_rd (cpu, rd, ((uint64_t)riscv_cpu->regs[rs1]
773 * (uint64_t)riscv_cpu->regs[rs2]) >> 32);
775 store_rd (cpu, rd, mulhu (riscv_cpu->regs[rs1], riscv_cpu->regs[rs2]));
781 store_rd (cpu, rd, ((int64_t)(signed_word) riscv_cpu->regs[rs1]
782 * (uint64_t)riscv_cpu->regs[rs2]) >> 32);
784 store_rd (cpu, rd, mulhsu (riscv_cpu->regs[rs1], riscv_cpu->regs[rs2]));
789 if (riscv_cpu->regs[rs1] == dividend_max && riscv_cpu->regs[rs2] == -1)
791 else if (riscv_cpu->regs[rs2])
792 tmp = (signed_word) riscv_cpu->regs[rs1]
793 % (signed_word) riscv_cpu->regs[rs2];
795 tmp = riscv_cpu->regs[rs1];
802 if (EXTEND32 (riscv_cpu->regs[rs2]) == -1)
804 else if (EXTEND32 (riscv_cpu->regs[rs2]))
805 tmp = EXTEND32 (riscv_cpu->regs[rs1]) % EXTEND32 (riscv_cpu->regs[rs2]);
807 tmp = riscv_cpu->regs[rs1];
813 if (riscv_cpu->regs[rs2])
814 store_rd (cpu, rd, riscv_cpu->regs[rs1] % riscv_cpu->regs[rs2]);
816 store_rd (cpu, rd, riscv_cpu->regs[rs1]);
822 if ((uint32_t) riscv_cpu->regs[rs2])
823 tmp = (uint32_t) riscv_cpu->regs[rs1] % (uint32_t) riscv_cpu->regs[rs2];
825 tmp = riscv_cpu->regs[rs1];
830 sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL);
839 struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
850 sim_cia pc = riscv_cpu->pc + 4;
858 sim_core_read_unaligned_4 (cpu, riscv_cpu->pc, read_map,
859 riscv_cpu->regs[rs1]));
865 if (amo_curr->addr == riscv_cpu->regs[rs1])
872 amo_curr->addr = riscv_cpu->regs[rs1];
884 if (amo_curr->addr == riscv_cpu->regs[rs1])
887 sim_core_write_unaligned_4 (cpu, riscv_cpu->pc, write_map,
888 riscv_cpu->regs[rs1],
889 riscv_cpu->regs[rs2]);
911 tmp = sim_core_read_unaligned_8 (cpu, riscv_cpu->pc, read_map,
912 riscv_cpu->regs[rs1]);
914 tmp = EXTEND32 (sim_core_read_unaligned_4 (cpu, riscv_cpu->pc, read_map,
915 riscv_cpu->regs[rs1]));
922 tmp = riscv_cpu->regs[rd] + riscv_cpu->regs[rs2];
926 tmp = riscv_cpu->regs[rd] & riscv_cpu->regs[rs2];
930 tmp = max ((signed_word) riscv_cpu->regs[rd],
931 (signed_word) riscv_cpu->regs[rs2]);
935 tmp = max ((unsigned_word) riscv_cpu->regs[rd],
936 (unsigned_word) riscv_cpu->regs[rs2]);
940 tmp = min ((signed_word) riscv_cpu->regs[rd],
941 (signed_word) riscv_cpu->regs[rs2]);
945 tmp = min ((unsigned_word) riscv_cpu->regs[rd],
946 (unsigned_word) riscv_cpu->regs[rs2]);
950 tmp = riscv_cpu->regs[rd] | riscv_cpu->regs[rs2];
954 tmp = riscv_cpu->regs[rs2];
958 tmp = riscv_cpu->regs[rd] ^ riscv_cpu->regs[rs2];
962 sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL);
966 sim_core_write_unaligned_8 (cpu, riscv_cpu->pc, write_map,
967 riscv_cpu->regs[rs1], tmp);
969 sim_core_write_unaligned_4 (cpu, riscv_cpu->pc, write_map,
970 riscv_cpu->regs[rs1], tmp);
980 riscv_cpu = RISCV_SIM_CPU (cpu);
991 sim_cia pc = riscv_cpu->pc + 2;
1001 store_rd (cpu, rd, riscv_cpu->regs[rs2]);
1006 pc = riscv_cpu->regs[rd];
1015 pc = riscv_cpu->pc + imm;
1026 store_rd (cpu, SIM_RISCV_RA_REGNUM, riscv_cpu->pc + 2);
1027 pc = riscv_cpu->pc + imm;
1035 store_rd (cpu, rd, EXTEND32 (riscv_cpu->regs[rd] + imm));
1040 sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
1050 store_rd (cpu, rd, riscv_cpu->regs[rd] + riscv_cpu->regs[rs2]);
1055 store_rd (cpu, SIM_RISCV_RA_REGNUM, riscv_cpu->pc + 2);
1056 pc = riscv_cpu->regs[rd];
1061 sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_stopped,
1069 rs1_c_name, imm, rs1_c_name, riscv_cpu->pc + imm);
1070 if (riscv_cpu->regs[rs1_c] == riscv_cpu->regs[0])
1072 pc = riscv_cpu->pc + imm;
1080 rs1_c_name, imm, rs1_c_name, riscv_cpu->pc + imm);
1081 if (riscv_cpu->regs[rs1_c] != riscv_cpu->regs[0])
1083 pc = riscv_cpu->pc + imm;
1092 sim_core_read_unaligned_4 (cpu, riscv_cpu->pc, read_map,
1093 riscv_cpu->regs[SIM_RISCV_SP_REGNUM]
1101 sim_core_read_unaligned_4 (cpu, riscv_cpu->pc, read_map,
1102 riscv_cpu->regs[rs1_c] + imm)));
1108 sim_core_write_unaligned_4 (cpu, riscv_cpu->pc, write_map,
1109 riscv_cpu->regs[SIM_RISCV_SP_REGNUM] + imm,
1110 riscv_cpu->regs[rs2]);
1116 sim_core_write_unaligned_4 (cpu, riscv_cpu->pc, write_map,
1117 riscv_cpu->regs[rs1_c] + (imm),
1118 riscv_cpu->regs[rs2_c]);
1124 store_rd (cpu, rd, riscv_cpu->regs[rd] + imm);
1142 store_rd (cpu, rs2_c, riscv_cpu->regs[SIM_RISCV_SP_REGNUM] + (imm));
1148 store_rd (cpu, rd, riscv_cpu->regs[SIM_RISCV_SP_REGNUM] + imm);
1153 store_rd (cpu, rs1_c, riscv_cpu->regs[rs1_c] - riscv_cpu->regs[rs2_c]);
1158 store_rd (cpu, rs1_c, riscv_cpu->regs[rs1_c] & riscv_cpu->regs[rs2_c]);
1163 store_rd (cpu, rs1_c, riscv_cpu->regs[rs1_c] | riscv_cpu->regs[rs2_c]);
1168 store_rd (cpu, rs1_c, riscv_cpu->regs[rs1_c] ^ riscv_cpu->regs[rs2_c]);
1175 sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
1182 store_rd (cpu, rd, riscv_cpu->regs[rd] << imm);
1189 sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
1198 EXTEND32 ((uint32_t) riscv_cpu->regs[rs1_c] >> imm));
1200 store_rd (cpu, rs1_c, riscv_cpu->regs[rs1_c] >> imm);
1207 sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
1217 sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
1219 tmp = ashiftrt (riscv_cpu->regs[rs1_c], imm);
1222 tmp = ashiftrt64 (riscv_cpu->regs[rs1_c], imm);
1229 store_rd (cpu, rs1_c, riscv_cpu->regs[rs1_c] & imm);
1236 EXTEND32 (riscv_cpu->regs[rs1_c] + riscv_cpu->regs[rs2_c]));
1243 EXTEND32 (riscv_cpu->regs[rs1_c] - riscv_cpu->regs[rs2_c]));
1251 sim_core_read_unaligned_8 (cpu, riscv_cpu->pc, read_map,
1252 riscv_cpu->regs[SIM_RISCV_SP_REGNUM]
1261 sim_core_read_unaligned_8 (cpu, riscv_cpu->pc, read_map,
1262 riscv_cpu->regs[rs1_c] + imm));
1269 sim_core_write_unaligned_8 (cpu, riscv_cpu->pc, write_map,
1270 riscv_cpu->regs[SIM_RISCV_SP_REGNUM] + imm,
1271 riscv_cpu->regs[rs2]);
1278 sim_core_write_unaligned_8 (cpu, riscv_cpu->pc, write_map,
1279 riscv_cpu->regs[rs1_c] + imm,
1280 riscv_cpu->regs[rs2_c]);
1284 sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
1294 struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
1309 if (riscv_cpu->csr.misa & 4)
1314 sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
1324 sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL);
1327 return riscv_cpu->pc + riscv_insn_length (iw);
1333 struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
1337 sim_cia pc = riscv_cpu->pc;
1385 ++riscv_cpu->csr.cycle;
1386 ++riscv_cpu->csr.instret;
1388 riscv_cpu->pc = pc;
1396 struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
1398 return riscv_cpu->pc;
1405 struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
1407 riscv_cpu->pc = pc;
1413 struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
1424 memcpy (buf, &riscv_cpu->regs[rn], len);
1427 memcpy (buf, &riscv_cpu->fpregs[rn - SIM_RISCV_FIRST_FP_REGNUM], len);
1430 memcpy (buf, &riscv_cpu->pc, len);
1435 memcpy (buf, &riscv_cpu->csr.name, len); \
1448 struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
1459 memcpy (&riscv_cpu->regs[rn], buf, len);
1462 memcpy (&riscv_cpu->fpregs[rn - SIM_RISCV_FIRST_FP_REGNUM], buf, len);
1465 memcpy (&riscv_cpu->pc, buf, len);
1470 memcpy (&riscv_cpu->csr.name, buf, len); \
1486 struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
1490 riscv_cpu->regs, 0, sizeof (riscv_cpu->regs));
1506 riscv_cpu->csr.misa = 0;
1509 riscv_cpu->csr.misa |= (uint64_t)2 << 62;
1522 riscv_cpu->csr.misa |= 0x1129; /* G = IMAFD. */
1524 riscv_cpu->csr.misa |= (1 << i);
1528 riscv_cpu->csr.mimpid = 0x8000;
1529 riscv_cpu->csr.mhartid = mhartid;
1554 struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
1587 riscv_cpu->a0 = argc;
1588 riscv_cpu->sp = sp;
Indexes created Tue Sep 08 00:25:21 UTC 2026