Cross Reference: /src/external/gpl3/gdb.old/dist/sim/riscv/sim-main.c

Lines Matching refs:EXTEND32
199 		EXTEND32 (riscv_cpu->regs[rs1] + riscv_cpu->regs[rs2]));
210       store_rd (cpu, rd, EXTEND32 (riscv_cpu->regs[rs1] + i_imm));
252 		EXTEND32 (riscv_cpu->regs[rs1] - riscv_cpu->regs[rs2]));
269       store_rd (cpu, rd, EXTEND32 (
285 		EXTEND32 ((uint32_t) riscv_cpu->regs[rs1] << shamt_imm));
298       store_rd (cpu, rd, EXTEND32 (
314 		EXTEND32 ((uint32_t) riscv_cpu->regs[rs1] >> shamt_imm));
329       store_rd (cpu, rd, EXTEND32 (
351       store_rd (cpu, rd, EXTEND32 (
469       store_rd (cpu, rd, EXTEND32 (
719       if (EXTEND32 (riscv_cpu->regs[rs2]) == -1)
721       else if (EXTEND32 (riscv_cpu->regs[rs2]))
722 	tmp = EXTEND32 (riscv_cpu->regs[rs1]) / EXTEND32 (riscv_cpu->regs[rs2]);
725       store_rd (cpu, rd, EXTEND32 (tmp));
744       store_rd (cpu, rd, EXTEND32 (tmp));
755       store_rd (cpu, rd, EXTEND32 ((int32_t) riscv_cpu->regs[rs1]
802       if (EXTEND32 (riscv_cpu->regs[rs2]) == -1)
804       else if (EXTEND32 (riscv_cpu->regs[rs2]))
805 	tmp = EXTEND32 (riscv_cpu->regs[rs1]) % EXTEND32 (riscv_cpu->regs[rs2]);
808       store_rd (cpu, rd, EXTEND32 (tmp));
826       store_rd (cpu, rd, EXTEND32 (tmp));
914     tmp = EXTEND32 (sim_core_read_unaligned_4 (cpu, riscv_cpu->pc, read_map,
1035 	  store_rd (cpu, rd, EXTEND32 (riscv_cpu->regs[rd] + imm));
1091       store_rd (cpu, rd, EXTEND32 (
1100       store_rd (cpu, rs2_c, EXTEND32 (
1198 		  EXTEND32 ((uint32_t) riscv_cpu->regs[rs1_c] >> imm));
1236 		EXTEND32 (riscv_cpu->regs[rs1_c] + riscv_cpu->regs[rs2_c]));
1243 		EXTEND32 (riscv_cpu->regs[rs1_c] - riscv_cpu->regs[rs2_c]));
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