Cross Reference: /src/external/gpl3/gdb.old/dist/sim/riscv/sim-main.c

Lines Matching refs:rs1
161   int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
164   const char *rs1_name = riscv_gpr_names_abi[rs1];
177 		 "rs1:%-2i:%-4s %0*" PRIxTW "  "
181 		 rs1, rs1_name, (int) sizeof (unsigned_word) * 2,
182 		 riscv_cpu->regs[rs1],
192       store_rd (cpu, rd, riscv_cpu->regs[rs1] + riscv_cpu->regs[rs2]);
199 		EXTEND32 (riscv_cpu->regs[rs1] + riscv_cpu->regs[rs2]));
204       store_rd (cpu, rd, riscv_cpu->regs[rs1] + i_imm);
210       store_rd (cpu, rd, EXTEND32 (riscv_cpu->regs[rs1] + i_imm));
215       store_rd (cpu, rd, riscv_cpu->regs[rs1] & riscv_cpu->regs[rs2]);
220       store_rd (cpu, rd, riscv_cpu->regs[rs1] & i_imm);
225       store_rd (cpu, rd, riscv_cpu->regs[rs1] | riscv_cpu->regs[rs2]);
230       store_rd (cpu, rd, riscv_cpu->regs[rs1] | i_imm);
235       store_rd (cpu, rd, riscv_cpu->regs[rs1] ^ riscv_cpu->regs[rs2]);
240       store_rd (cpu, rd, riscv_cpu->regs[rs1] ^ i_imm);
245       store_rd (cpu, rd, riscv_cpu->regs[rs1] - riscv_cpu->regs[rs2]);
252 		EXTEND32 (riscv_cpu->regs[rs1] - riscv_cpu->regs[rs2]));
263 		riscv_cpu->regs[rs1] << (riscv_cpu->regs[rs2] & u_imm));
270 	(uint32_t) riscv_cpu->regs[rs1] << (riscv_cpu->regs[rs2] & 0x1f)));
278       store_rd (cpu, rd, riscv_cpu->regs[rs1] << shamt_imm);
285 		EXTEND32 ((uint32_t) riscv_cpu->regs[rs1] << shamt_imm));
292 		riscv_cpu->regs[rs1] >> (riscv_cpu->regs[rs2] & u_imm));
299 	(uint32_t) riscv_cpu->regs[rs1] >> (riscv_cpu->regs[rs2] & 0x1f)));
307       store_rd (cpu, rd, riscv_cpu->regs[rs1] >> shamt_imm);
314 		EXTEND32 ((uint32_t) riscv_cpu->regs[rs1] >> shamt_imm));
320 	tmp = ashiftrt (riscv_cpu->regs[rs1], riscv_cpu->regs[rs2] & 0x1f);
322 	tmp = ashiftrt64 (riscv_cpu->regs[rs1], riscv_cpu->regs[rs2] & 0x3f);
330 	ashiftrt ((int32_t) riscv_cpu->regs[rs1],
341 	  tmp = ashiftrt (riscv_cpu->regs[rs1], shamt_imm);
344 	tmp = ashiftrt64 (riscv_cpu->regs[rs1], shamt_imm);
352 	ashiftrt ((int32_t) riscv_cpu->regs[rs1], shamt_imm)));
357 		!!((signed_word) riscv_cpu->regs[rs1] <
362       store_rd (cpu, rd, !!((unsigned_word) riscv_cpu->regs[rs1] <
367       store_rd (cpu, rd, !!((signed_word) riscv_cpu->regs[rs1] <
372       store_rd (cpu, rd, !!((unsigned_word) riscv_cpu->regs[rs1] <
384       if (riscv_cpu->regs[rs1] == riscv_cpu->regs[rs2])
394       if ((signed_word) riscv_cpu->regs[rs1] <
405       if ((unsigned_word) riscv_cpu->regs[rs1] <
416       if ((signed_word) riscv_cpu->regs[rs1] >=
427       if ((unsigned_word) riscv_cpu->regs[rs1] >=
438       if (riscv_cpu->regs[rs1] != riscv_cpu->regs[rs2])
453       pc = riscv_cpu->regs[rs1] + i_imm;
464 				   riscv_cpu->regs[rs1] + i_imm));
471 rs1] + i_imm)));
478 				   riscv_cpu->regs[rs1] + i_imm));
485 				   riscv_cpu->regs[rs1] + i_imm)));
492 				   riscv_cpu->regs[rs1] + i_imm));
499 				   riscv_cpu->regs[rs1] + i_imm)));
506 				   riscv_cpu->regs[rs1] + i_imm));
513 				  riscv_cpu->regs[rs1] + s_imm,
520 				  riscv_cpu->regs[rs1] + s_imm,
527 				  riscv_cpu->regs[rs1] + s_imm,
534 				  riscv_cpu->regs[rs1] + s_imm,
547 		     riscv_cpu->csr.name & !riscv_cpu->regs[rs1]); \
562 		     riscv_cpu->csr.name | riscv_cpu->regs[rs1]); \
577 		     riscv_cpu->regs[rs1]); \
691   int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
694   const char *rs1_name = riscv_gpr_names_abi[rs1];
706       if (riscv_cpu->regs[rs1] == dividend_max && riscv_cpu->regs[rs2] == -1)
709 	tmp = (signed_word) riscv_cpu->regs[rs1] /
722 	tmp = EXTEND32 (riscv_cpu->regs[rs1]) / EXTEND32 (riscv_cpu->regs[rs2]);
731 	store_rd (cpu, rd, (unsigned_word) riscv_cpu->regs[rs1]
741 	tmp = (uint32_t) riscv_cpu->regs[rs1] / (uint32_t) riscv_cpu->regs[rs2];
749       store_rd (cpu, rd, riscv_cpu->regs[rs1] * riscv_cpu->regs[rs2]);
755       store_rd (cpu, rd, EXTEND32 ((int32_t) riscv_cpu->regs[rs1]
763 		  ((int64_t)(signed_word) riscv_cpu->regs[rs1]
766 	store_rd (cpu, rd, mulh (riscv_cpu->regs[rs1], riscv_cpu->regs[rs2]));
772 	store_rd (cpu, rd, ((uint64_t)riscv_cpu->regs[rs1]
775 	store_rd (cpu, rd, mulhu (riscv_cpu->regs[rs1], riscv_cpu->regs[rs2]));
781 	store_rd (cpu, rd, ((int64_t)(signed_word) riscv_cpu->regs[rs1]
784 	store_rd (cpu, rd, mulhsu (riscv_cpu->regs[rs1], riscv_cpu->regs[rs2]));
789       if (riscv_cpu->regs[rs1] == dividend_max && riscv_cpu->regs[rs2] == -1)
792 	tmp = (signed_word) riscv_cpu->regs[rs1]
795 	tmp = riscv_cpu->regs[rs1];
805 	tmp = EXTEND32 (riscv_cpu->regs[rs1]) % EXTEND32 (riscv_cpu->regs[rs2]);
807 	tmp = riscv_cpu->regs[rs1];
814 	store_rd (cpu, rd, riscv_cpu->regs[rs1] % riscv_cpu->regs[rs2]);
816 	store_rd (cpu, rd, riscv_cpu->regs[rs1]);
823 	tmp = (uint32_t) riscv_cpu->regs[rs1] % (uint32_t) riscv_cpu->regs[rs2];
825 	tmp = riscv_cpu->regs[rs1];
843   int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
846   const char *rs1_name = riscv_gpr_names_abi[rs1];
859 				   riscv_cpu->regs[rs1]));
865 	  if (amo_curr->addr == riscv_cpu->regs[rs1])
872       amo_curr->addr = riscv_cpu->regs[rs1];
884 	  if (amo_curr->addr == riscv_cpu->regs[rs1])
888 					  riscv_cpu->regs[rs1],
912 				     riscv_cpu->regs[rs1]);
915 					       riscv_cpu->regs[rs1]));
967 				riscv_cpu->regs[rs1], tmp);
970 				riscv_cpu->regs[rs1], tmp);
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