Lines Matching defs:saved_state
100 saved_state_type saved_state;
118 #define R0 saved_state.asregs.regs[0]
119 #define Rn saved_state.asregs.regs[n]
120 #define Rm saved_state.asregs.regs[m]
121 #define UR0 (unsigned int) (saved_state.asregs.regs[0])
124 #define SR0 saved_state.asregs.regs[0]
125 #define CREG(n) (saved_state.asregs.cregs[(n)])
126 #define GBR saved_state.asregs.gbr
127 #define VBR saved_state.asregs.vbr
128 #define DBR saved_state.asregs.dbr
129 #define TBR saved_state.asregs.tbr
130 #define IBCR saved_state.asregs.ibcr
131 #define IBNR saved_state.asregs.ibnr
132 #define BANKN (saved_state.asregs.ibnr & 0x1ff)
133 #define ME ((saved_state.asregs.ibnr >> 14) & 0x3)
134 #define SSR saved_state.asregs.ssr
135 #define SPC saved_state.asregs.spc
136 #define SGR saved_state.asregs.sgr
137 #define SREG(n) (saved_state.asregs.sregs[(n)])
138 #define MACH saved_state.asregs.mach
139 #define MACL saved_state.asregs.macl
140 #define PR saved_state.asregs.pr
141 #define FPUL saved_state.asregs.fpul
150 #define Rn_BANK(n) (saved_state.asregs.bank[(n)])
151 #define SET_Rn_BANK(n, EXP) do { saved_state.asregs.bank[(n)] = (EXP); } while (0)
172 #define BO ((saved_state.asregs.sr & SR_MASK_BO) != 0)
173 #define CS ((saved_state.asregs.sr & SR_MASK_CS) != 0)
174 #define M ((saved_state.asregs.sr & SR_MASK_M) != 0)
175 #define Q ((saved_state.asregs.sr & SR_MASK_Q) != 0)
176 #define S ((saved_state.asregs.sr & SR_MASK_S) != 0)
177 #define T ((saved_state.asregs.sr & SR_MASK_T) != 0)
178 #define LDST ((saved_state.asregs.ldst) != 0)
180 #define SR_BL ((saved_state.asregs.sr & SR_MASK_BL) != 0)
181 #define SR_RB ((saved_state.asregs.sr & SR_MASK_RB) != 0)
182 #define SR_MD ((saved_state.asregs.sr & SR_MASK_MD) != 0)
183 #define SR_DMY ((saved_state.asregs.sr & SR_MASK_DMY) != 0)
184 #define SR_DMX ((saved_state.asregs.sr & SR_MASK_DMX) != 0)
185 #define SR_RC ((saved_state.asregs.sr & SR_MASK_RC))
191 saved_state.asregs.sr |= (BIT); \
193 saved_state.asregs.sr &= ~(BIT); \
210 #define SET_LDST(EXP) (saved_state.asregs.ldst = ((EXP) != 0))
213 #define GET_SR() (saved_state.asregs.sr - 0)
218 (saved_state.asregs.sr \
219 = (saved_state.asregs.sr & 0xf000ffff) | ((x) & 0xfff) << 16)
234 int old = saved_state.asregs.fpscr;
235 saved_state.asregs.fpscr = (x);
237 if ((saved_state.asregs.fpscr ^ old) & FPSCR_MASK_FR
241 union fregs_u tmpf = saved_state.asregs.fregs[0];
242 saved_state.asregs.fregs[0] = saved_state.asregs.fregs[1];
243 saved_state.asregs.fregs[1] = tmpf;
248 #define GET_FPSCR() (saved_state.asregs.fpscr)
254 #define DSR (saved_state.asregs.fpscr)
257 (saved_state.asregs.exception = x, saved_state.asregs.insn_end = 0)
285 else if ((addr & saved_state.asregs.xyram_select) \
286 == saved_state.asregs.xram_start) \
287 ptr = (void *) &saved_state.asregs.xmem_offset[addr ^ endian]; \
288 else if ((addr & saved_state.asregs.xyram_select) \
289 == saved_state.asregs.yram_start) \
290 ptr = (void *) &saved_state.asregs.ymem_offset[addr ^ endian]; \
377 dr.i[1] = saved_state.asregs.fregs[0].i[n + 0];
378 dr.i[0] = saved_state.asregs.fregs[0].i[n + 1];
382 return (saved_state.asregs.fregs[0].d[n >> 1]);
398 saved_state.asregs.fregs[0].i[n + 0] = dr.i[1];
399 saved_state.asregs.fregs[0].i[n + 1] = dr.i[0];
402 saved_state.asregs.fregs[0].d[n >> 1] = exp;
405 #define SET_FI(n,EXP) (saved_state.asregs.fregs[0].i[(n)] = (EXP))
406 #define FI(n) (saved_state.asregs.fregs[0].i[(n)])
408 #define FR(n) (saved_state.asregs.fregs[0].f[(n)])
409 #define SET_FR(n,EXP) (saved_state.asregs.fregs[0].f[(n)] = (EXP))
412 #define XF(n) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f])
413 #define SET_XF(n,EXP) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f] = (EXP))
415 #define RS saved_state.asregs.rs
416 #define RE saved_state.asregs.re
417 #define MOD (saved_state.asregs.mod)
423 #define DSP_R(n) saved_state.asregs.sregs[(n)]
490 tmp = saved_state.asregs.bank[i];
491 saved_state.asregs.bank[i] = saved_state.asregs.regs[i];
492 saved_state.asregs.regs[i] = tmp;
495 saved_state.asregs.sr = new_sr;
586 saved_state.asregs.fregs[i].i[(j + 0)] = f0;
587 saved_state.asregs.fregs[i].i[(j + 1)] = f1;
599 f0 = saved_state.asregs.fregs[i].i[(j + 0)];
600 f1 = saved_state.asregs.fregs[i].i[(j + 1)];
684 if (saved_state.asregs.exception || PH2T (p) & maskw) \
685 saved_state.asregs.insn_end = 0; \
687 saved_state.asregs.insn_end = loop.end; \
689 saved_state.asregs.insn_end = mem_end; \
814 return (char *) (x + saved_state.asregs.memory);
824 unsigned char *memory = saved_state.asregs.memory;
1279 int *R = &(saved_state.asregs.regs[0]);
1280 unsigned char *memory = saved_state.asregs.memory;
1281 int maskb = ~((saved_state.asregs.msize - 1) & ~0);
1282 unsigned char *insn_ptr = PT2H (saved_state.asregs.pc);
1335 saved_state.asregs.memstalls += memstalls;
1521 if (saved_state.asregs.memory)
1523 mfree (saved_state.asregs.memory, saved_state.asregs.msize);
1526 saved_state.asregs.msize = 1 << power;
1528 saved_state.asregs.memory =
1529 (unsigned char *) mcalloc (1, saved_state.asregs.msize);
1531 if (!saved_state.asregs.memory)
1535 saved_state.asregs.msize);
1537 saved_state.asregs.msize = 1;
1538 saved_state.asregs.memory = (unsigned char *) mcalloc (1, 1);
1576 if (saved_state.asregs.xyram_select != new_select)
1578 saved_state.asregs.xyram_select = new_select;
1579 free (saved_state.asregs.xmem);
1580 free (saved_state.asregs.ymem);
1581 saved_state.asregs.xmem =
1583 saved_state.asregs.ymem =
1587 if (! saved_state.asregs.xmem || ! saved_state.asregs.ymem)
1589 saved_state.asregs.xyram_select = 0;
1590 if (saved_state.asregs.xmem)
1591 free (saved_state.asregs.xmem);
1592 if (saved_state.asregs.ymem)
1593 free (saved_state.asregs.ymem);
1596 saved_state.asregs.xram_start = xram_start;
1597 saved_state.asregs.yram_start = yram_start;
1598 saved_state.asregs.xmem_offset = saved_state.asregs.xmem - xram_start;
1599 saved_state.asregs.ymem_offset = saved_state.asregs.ymem - yram_start;
1604 if (saved_state.asregs.xyram_select)
1606 saved_state.asregs.xyram_select = 0;
1607 free (saved_state.asregs.xmem);
1608 free (saved_state.asregs.ymem);
1612 if (! saved_state.asregs.xyram_select)
1614 saved_state.asregs.xram_start = 1;
1615 saved_state.asregs.yram_start = 1;
1618 if (saved_state.asregs.regstack == NULL)
1619 saved_state.asregs.regstack =
1620 calloc (512, sizeof *saved_state.asregs.regstack);
1638 if (saved_state.asregs.msize != 1 << sim_memory_size)
1643 if (saved_state.asregs.profile && !profile_file)
1657 saved_state.asregs.profile_hist =
1678 swapout16 (saved_state.asregs.profile_hist[i]);
1690 #define MMASKB ((saved_state.asregs.msize -1) & ~0)
1719 register int *R = &(saved_state.asregs.regs[0]);
1725 register int maskb = ~((saved_state.asregs.msize - 1) & ~0);
1726 register int maskw = ~((saved_state.asregs.msize - 1) & ~1);
1727 register int maskl = ~((saved_state.asregs.msize - 1) & ~3);
1734 saved_state.asregs.exception = 0;
1736 memory = saved_state.asregs.memory;
1737 mem_end = memory + saved_state.asregs.msize;
1744 insn_ptr = PT2H (saved_state.asregs.pc);
1748 PR = saved_state.asregs.pr;
1751 prevlock = saved_state.asregs.prevlock;
1752 thislock = saved_state.asregs.thislock;
1753 doprofile = saved_state.asregs.profile;
1761 if (step && insn_ptr < saved_state.asregs.insn_end)
1763 if (saved_state.asregs.exception)
1766 saved_state.asregs.insn_end = insn_ptr;
1769 saved_state.asregs.exception = SIGTRAP;
1770 saved_state.asregs.insn_end = insn_ptr + 2;
1774 while (insn_ptr < saved_state.asregs.insn_end)
1811 saved_state.asregs.cycles += doprofile;
1813 if (saved_state.asregs.profile_hist)
1818 int i = saved_state.asregs.profile_hist[n];
1820 saved_state.asregs.profile_hist[n] = i + 1;
1827 if (saved_state.asregs.insn_end == loop.end)
1829 saved_state.asregs.sr += SR_RC_INCREMENT;
1834 saved_state.asregs.insn_end = mem_end;
1840 if (saved_state.asregs.exception == SIGILL
1841 || saved_state.asregs.exception == SIGBUS)
1846 else if (! saved_state.asregs.exception)
1847 saved_state.asregs.exception = SIGBUS;
1849 saved_state.asregs.ticks += get_now () - tick_start;
1850 saved_state.asregs.cycles += cycles;
1851 saved_state.asregs.stalls += stalls;
1852 saved_state.asregs.memstalls += memstalls;
1853 saved_state.asregs.insts += insts;
1854 saved_state.asregs.pc = PH2T (insn_ptr);
1856 saved_state.asregs.pr = PR;
1859 saved_state.asregs.prevlock = prevlock;
1860 saved_state.asregs.thislock = thislock;
1880 saved_state.asregs.memory[(MMASKB & (addr + i)) ^ endianb] = data[i];
1895 data[i] = saved_state.asregs.memory[(MMASKB & (addr + i)) ^ endianb];
1924 saved_state.asregs.regs[rn] = val;
1927 saved_state.asregs.pc = val;
2015 if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
2018 saved_state.asregs.regstack[gdb_bank_number].regs[rn] = val;
2024 saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM] = val;
2030 if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
2033 saved_state.asregs.regstack[gdb_bank_number].regs[rn + 8] = val;
2037 saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM] = val;
2062 saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACL] = val;
2065 saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_GBR] = val;
2068 saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_PR] = val;
2071 saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_IVN] = val;
2074 saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACH] = val;
2096 val = saved_state.asregs.regs[rn];
2099 val = saved_state.asregs.pc;
2187 if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
2190 val = saved_state.asregs.regstack[gdb_bank_number].regs[rn];
2195 : saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM]);
2201 if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
2204 val = saved_state.asregs.regstack[gdb_bank_number].regs[rn + 8];
2209 : saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM]);
2232 val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACL];
2235 val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_GBR];
2238 val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_PR];
2241 val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_IVN];
2244 val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACH];
2258 if (saved_state.asregs.exception == SIGQUIT)
2261 *sigrc = saved_state.asregs.regs[5];
2266 *sigrc = saved_state.asregs.exception;
2274 (double) saved_state.asregs.ticks / (double) now_persec ();
2275 double virttime = saved_state.asregs.cycles / 36.0e6;
2278 saved_state.asregs.insts);
2280 saved_state.asregs.cycles);
2282 saved_state.asregs.stalls);
2284 saved_state.asregs.memstalls);
2289 saved_state.asregs.profile);
2296 (int) (saved_state.asregs.cycles / timetaken));
2305 return saved_state.asregs.pc;
2311 saved_state.asregs.pc = pc;
2435 memset (&saved_state, 0,
2436 (char*) &saved_state.asregs.end_of_registers - (char*) &saved_state);
2440 saved_state.asregs.pc = bfd_get_start_address (prog_bfd);
2444 saved_state.asregs.bfd_mach = bfd_get_mach (prog_bfd);
Indexes created Sun Aug 30 00:27:18 UTC 2026